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Serial ATA Native Command Queuing 

The commands also contain a force unit access (FUA) bit for high availability applications.  When 
the FUA bit is set for a Write FPDMA Queued command, the drive will commit the data to media 
before returning success for the command.  By using the FUA bit as necessary on writes, the 
host can manage the amount of data that has not been committed to media within the drive’s 
internal cache.   

 

Register 

7 6 5 4 3 2 1 

Features Sector 

Count 

7:0 

Features (exp) 

Sector Count 15:8 

Sector Count 

TAG 

Reserved 

Sector Count (exp) 

Reserved 

Sector Number 

LBA 7:0 

Sector Number (exp) 

LBA 31:24 

Cylinder Low 

LBA 15:8 

Cylinder Low (exp) 

LBA 39:32 

Cylinder High 

LBA 23:16 

Cylinder High (exp) 

LBA 47:40 

Device/Head 

FUA 1 Res 0 

Reserved 

Command 60h 

Figure 1 

Read FPDMA Queued Command 

One interesting field is the TAG field in the Sector Count register.  Each queued command issued 
has a tag associated with it.  The tag is a shorthand mechanism used between the host and the 
device to identify a particular outstanding command.  Tag values can be between 0 and 31, 
although the drive can report support for a queue depth less than 32.  In this case, tag values are 
limited to the maximum tag value the drive supports.  Having tag values limited to be between 0 
and 31 has some nice advantages, including that status for all commands can be reported in one 
32-bit value.  Each outstanding command must have a unique tag value.   

The Read and Write FPDMA Queued commands are issued just like any other command would 
be, i.e. the taskfile is written with the particular register values and then the Command register is 
written with the command opcode.  The difference between queued and non-queued commands 
is what happens after the command is issued.  If a non-queued command was issued, the drive 
would transfer the data for that command and then clear the BSY bit in the Status register to tell 
the host that the command was completed.  When a queued command is issued, the drive will 
clear BSY immediately, before any data is transferred to the host.  In queuing, the BSY bit is not 
used to convey command completion.  Instead, the BSY bit is used to convey whether the drive is 
ready to accept a new command.  As soon as the BSY bit is cleared, the host can issue another 
queued command to the drive.  In this way a queue of commands can be built within the drive. 

Transferring Data 

NCQ takes advantage of a feature called First Party DMA to transfer data between the drive and 
the host.  First Party DMA allows the drive to have control over programming the DMA engine for 
a data transfer.  This is an important enhancement since only the drive knows the current angular 
and rotational position of the drive head.  The drive can then select the next data transfer to 
minimize both seek and rotational latencies.  The First Party DMA mechanism is effectively what 
allows the drive to re-order commands in the most optimal way. 

As an additional optimization, the drive can also return data out-of-order to further minimize the 
rotational latency.  First Party DMA allows the drive to return partial data for a command, send 
partial data for another command, and then finish sending the data for the first command if this is 
the most efficient means for completing the data transfers. 

 

6

Summary of Contents for ST3250620AS - Barracuda 250GB 7200 RPM 16MB Cache SATA 3.0Gb/s Perpendicular Recording Hard Drive

Page 1: ...July 2003 Serial ATA Native Command Queuing An Exciting New Performance Feature for Serial ATA A JOINT WHITEPAPER BY Intel Corporation and Seagate Technology www intel com www seagate com...

Page 2: ...mands to be outstanding within a drive at the same time Drives that support NCQ have an internal queue where outstanding commands can be dynamically rescheduled or re ordered along with the necessary...

Page 3: ...onal Position Ordering to optimally re order commands to maximize performance Seek Latency Optimization Seek latencies are caused by the time it takes the read write head to position and settle over t...

Page 4: ...ve almost simultaneously Higher RPM spindles are one approach to reduce rotational latencies However increasing RPM spindle rates carries a substantial additional cost Rotational latencies can also be...

Page 5: ...nding a DMA Setup FIS Frame Information Structure to the host controller This FIS specifies the tag of the command for which the DMA is being set up Based on the tag value the host controller will loa...

Page 6: ...s written with the particular register values and then the Command register is written with the command opcode The difference between queued and non queued commands is what happens after the command i...

Page 7: ...alled Auto Activate which can eliminate one FIS transfer during a write command One important note for HBA designers is that new commands cannot be issued between the DMA Setup FIS and the completion...

Page 8: ...the drive can return a Set Device Bits FIS without a host handshake it is possible to receive two Set Device Bits FISes very close together in time If the second Set Device Bits FIS arrives before hos...

Page 9: ...ointer to buffer to place data in 1024 Want to read 1024 bytes from the file numBytesRead Number of bytes read from the file NULL Synchronous so overlapped parameter is NULL Code for checking the stat...

Page 10: ...50 Wait up to 50 milliseconds for completion could be infinity Check the value of dwResult and also call GetOverlappedResult to ensure that each IO that completed was with good status As can be seen...

Page 11: ...ntroller Interface AHCI definition Amber holds a BSE in Computer Engineering from the University of Michigan and has been with Intel for 6 years Joni Clark Product Marketing Manager Seagate Technology...

Page 12: ...Serial ATA Native Command Queuing 12...

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