Schweitzer Engineering Laboratories SEL-311A, Instruction Manual

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Date Code 20011205 Inputs, Outputs, Timers, and Other Control Logic 7-17
SEL-311A Instruction Manual
If the individual settings change or active setting group change causes a change in SEL
OGIC
control equation settings SET n or RST n ( n = 1 through 16), the retained states of the latch bits
can be changed, subject to the newly enabled settings SET n or RST n .
Reset Latch Bits for Active Setting Group Change
If desired, the latch bits can be reset to logical 0 right after a settings group change, using
SEL
OGIC
control equation setting RST n ( n = 1 through 16). Relay Word bits SG1 through SG6
indicate the active setting Group 1 through 6, respectively (see Table 7.3).
For example, when setting Group 4 becomes the active setting group, latch bit LT2 should be
reset. Make the following SEL
OGIC
control equation settings in setting Group 4:
SV7 = SG4
RST2 = !SV7T + ... [= NOT(SV7T) + ...]
Figure 7.15: Time Line for Reset of Latch Bit LT2 After Active Setting Group Change
In Figure 7.15, latch bit LT2 is reset (deasserted to logical 0) when reset setting RST2 asserts to
logical 1 for the short time right after setting Group 4 is activated. This logic can be repeated for
other latch bits.
Note: Make Latch Control Switch Settings with Care
The latch bit states are stored in nonvolatile memory so they can be retained during power loss,
settings change, or active setting group change. The nonvolatile memory is rated for a finite
number of “writes” for all cumulative latch bit state changes. Exceeding the limit can result in an