– 4 –
Fig. 1-3. IC932 Block Diagram
3. IC932 (V Driver)
A V driver (IC932) is necessary in order to generate the clocks
(vertical transfer clock and electronic shutter clock) which
driver the CCD.
In addition the XV1-XV8 signals which are output from IC102
are vertical transfer clocks, and the XSG signal is superim-
posed onto XV1, XV3, XV5 and XV7 at IC932 in order to gen-
erate a ternary pulse. In addition, the XSUB signal which is
output from IC102 is used as the sweep pulse for the elec-
tronic shutter.
Fig. 1-4. IC931 Block Diagram
4. IC931 (H Driver, CDS, AGC and A/D converter)
IC931 contains the functions of H driver, CDS, AGC and A/D
converter. As horizontal clock driver for CCD image sensor,
HØ1, HØ2, HØL and RG are generated inside, and output to
CCD.
The video signal which is output from the CCD is input to pin
(1) and pin (74) of IC931. There are sampling hold blocks
generated from the SHP and SHD pulses, and it is here that
CDS (correlated double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier (VGA: Variable Gain Amplifier). It
is A/D converted internally into a 14-bit signal, and is then
input to MOVIC (IC102). The gain of the VGA amplifier is con-
trolled by pins (4), (5), (6), (69), (70) and (71) serial signal
which is output from ASIC (IC101).
43
4
5
6
46
45
44
55
54
RESET
SUBCNT
SUB
VDC
V6
V4
V2
V7R
V5R
Level
conversion
50
V8
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
37
VM
12
VM
29
OV8
31
OV4
13
VMSUB
30
OV6
3-level
25
OV7R
2-level
2-level
2-level
2-level
2-level
41
VL
26
OV5R
8
VL
14
OSUB
52
58
57
56
61
60
59
3
62
38
7
CH1
V3
CH2
CH6
V5
CH3
CH7
V7
CH8
GND
VH
53 V1
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
10
19
21
15
VH
OV7A
OV7B
OV5A
23
20 OV5B
OV3A
63 CH4
3-level
3-level
3-level
3-level
3-level
3-level
3-level
28
22 OV3B
OV1A
11
27 OV1B
VHH
Level
conversion
Level
conversion
Level
conversion
Level
conversion
3-level
CCDIN_A
RG_B
H1A TO H4A
HD_B
HD_A
CLI_B
CLI_A
DOUT_A
REFB_B
REFT_B
PRECISION
TIMING
CORE
SYNC
GENERATOR
VGA
ADC
14
0~18 dB
VREF_B
CLAMP
INTERNAL
REGISTERS
INTERNAL CLOCKS
CDS
HORIZONTAL
DRIVERS
4
AD9942
VD_A
H1B TO H4B
4
RG_A
REFB_A
REFT_A
VREF_A
CCDIN_B
DOUT_B
VGA
ADC
14
0~18 dB
CLAMP
CDS
VD_B
SL_B
SL_A
SDATA_A SDATA_B
SCK_A
SCK_B
