SSD P4 (PATA) Solid State Drive
Product Manual
Rev 0.4
© 2010 SanDisk® Corporation
22
Document No. 80-11-XXXX1
7.3
Detailed Pin-Description
Signal Name
Dir.
Description
RESET-
I
This input pin is the active low hardware reset from the host.
D00 - D15
I/O
16-bit data bus. All Task File operations occur in byte mode on the
low order bus D00-D07 while all data transfers are 16-bits using
D00-D15.
DMARQ
O
This signal is used for DMA data transfers between host and
device and is asserted by the device when it is ready to transfer
data to or from the host. The direction of data transfer is
controlled by DIOR- and DIOW-. This signal is used in a
handshake manner with DMACK- (i.e., the device waits until the
host asserts DMACK- before negating DMARQ, and reasserting
DMARQ if there is more data to transfer).
DIOW-
I
The I/O Write strobe signal is asserted by the host to write device
registers or the data port. The latching of data occurs on the
negative to positive edge of the signal (trailing edge).
STOP
Assertion of this signal by the host during a UDMA burst signals
the termination of the UDMA burst.
DIOR-
I
The I/O Read strobe signal is asserted by the host to read device
registers or the data port. The latching of data occurs on the
negative to positive edge of the signal (trailing edge).
HDMARDY-
This signal is the flow control signal for UDMA read (data in)
transfers. This signal is asserted by the host to indicate that the
host is ready to receive UDMA data in bursts.
HSTROBE
This signal is the data out strobe signal from the host for a UDMA
data out burst. Data is latched on both rising and failing edges.
IORDY
O
This signal is negated to extend the host transfer cycle of any host
register access when the device is not ready to respond to a data
transfer request.
DDMARDY-
This signal is the flow control signal for UDMA write (data out)
transfers. This signal is asserted by the device to indicate to the
host that the device is ready to receive UDMA data out bursts.
DSTROBE
This signal is the data in strobe signal from the device for a UDMA
data in burst. Data is latched on both rising and failing edges.
DMACK-
I
This signal is used by the host in response to DMARQ to initiate
DMA transfers. This signal may be negated by the host to
suspend the DMA transfers in process.
INTRQ
O
This signal is the active high Interrupt Request to the host. This
signal is enabled when the nIEN bit in the Device Control Register
is set to 0.
DA0 – DA2
I
This is the 3-bit binary coded address asserted by the host to
access a register or data port in the device.
PDIAG-
I/O This input/output is the Pass Diagnostic signal in the master/slave
handshake protocol.
CS0-
I
This chip select is for access to the Task File registers (e.g.,
Command, Status, Feature, Sector Count, etc).
