SanDisk SDIB-4, Product Manual

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FlashDrive Product Manual
FlashDrive Product Manual © 1999 SANDISK CORPORATION 36
6.0 ATA Command Description
This section defines the software requirements and
the format of the commands the host sends to the
FlashDrives. Commands are issued to the
FlashDrive by loading the required registers in
the command block with the supplied parameters,
and then writing the command code to the
Command Register. The manner in which a
command is accepted varies. There are three
classes (see Table 6-1) of command acceptance, all
dependent on the host not issuing commands unless
the FlashDrive is not busy . (The BUSY bit in the
status and alternate status registers is 0.)
• Upon receipt of a Class 1 command, the
FlashDrive sets the BUSY bit within 400
nsec.
• Upon receipt of a Class 2 command, the
FlashDrive sets the BUSY bit within 400
nsec, sets up the sector buffer for a write
operation, sets DRQ within 700 µsec, and
clears the BUSY bit within 400 nsec of setting
DRQ.
• Upon receipt of a Class 3 command, the
FlashDrive sets the BUSY bit within 400
nsec, sets up the sector buffer for a write
operation, sets DRQ within 20 msec (assuming
no re-assignments), and clears the BUSY bit
within 400 nsec of setting DRQ.
6.1 ATA Command Set
Table 6-1 summarizes the ATA command set with
the paragraphs that follow describing the
individual commands and the task file for each.