Samsung YEPP YP-S2, Service Manual

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7-2 Samsung Electronics
Schematic Diagram
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7-1 Overall Block Diagram
Battery
Charger
NF_0
[0-7]
Audio_R/L
VIO_3.0
USB+, USB-
3.7V
VBUS 5V
Nand Flash Memory
Processor (S5L8424)
- 16bit Calm risk (120 Mhz)
- 24bit DSP (Calm MAC2424)
- 2 CH PMU (1.2V, 3.0V)
Memory
Interface
Li-Polymer
Battery
(200mAhl)
CODEC
SDRAM (5M)
+ROM (50k)
USB
Controller
ADC
USB CLK
12 Mhz
Main CLK
32.768 Khz
Key Input
(Tact SW)
Earphone
USB
JACK

If power is supplied through the external input (3.7V-battery, 5V-USB), in the Main IC’s PMU the core voltage 1.2V
needed in the operation of the Main IC and the IO voltage 3.0V needed in the peripheral circuit (Nand memory) is
supplied.
VIO_3.0V Core_1.2V