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Samsung S3C80M4/F80M4, User Manual

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CONTROL REGISTERS 

 

S3C80M4/F80M4 

4-8  

 

IMR

 — Interrupt Mask Register 

DDH 

Set 1 

Bit 

Identifier 

.7 .6 .5 .4 .3 .2 .1 .0 

RESET Value 

x x x x x x x x 

Read/Write 

R/W R/W R/W R/W R/W R/W R/W R/W 

Addressing Mode 

Register addressing mode only 

 

.7 

Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.3

 

 

0 Disable 

(mask) 

 

 

1 Enable 

(unmask) 

 

 

.6 

Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.2 

 

0 Disable 

(mask) 

 

 

1 Enable 

(unmask) 

 

 

.5 

Interrupt Level 5 (IRQ5) Enable Bit; External Interrupts P0.1 

 

0 Disable 

(mask) 

 

 

1 Enable 

(unmask) 

 

 

.4 

Interrupt Level 4 (IRQ4) Enable Bit; External Interrupts P0.0 

 

0 Disable 

(mask) 

 

 

1 Enable 

(unmask) 

 

 

.3 

Reserved 

 

 

.2 

Interrupt Level 2 (IRQ2) Enable Bit; PWM 

 

0 Disable 

(mask) 

 

 

1 Enable 

(unmask) 

 

 

.1 

Reserved 

 

.0 

Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match 

 

0 Disable 

(mask) 

 

 

1 Enable 

(unmask) 

 

NOTE:

  When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU. 

Summary of Contents for S3C80M4/F80M4

Page 1: ...S3C80M4 F80M4 8 BIT CMOS MICROCONTROLLERS USER S MANUAL Revision 1 ...

Page 2: ...ntended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless aga...

Page 3: ...4 interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3C8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each instruction are prese...

Page 4: ...escriptions 1 6 Pin Circuits 1 7 Chapter 2 Address Spaces Overview 2 1 Program Memory ROM 2 2 Register Architecture 2 3 Register Page Pointer PP 2 5 Register Set 1 2 6 Register Set 2 2 6 Prime Register Space 2 7 Working Registers 2 8 Using The Register Points 2 9 Register Addressing 2 11 Common Working Register Area C0H CFH 2 13 4 Bit Working Register Addressing 2 14 8 Bit Working Register Address...

Page 5: ...stem Level Interrupt Control Registers 5 6 Interrupt Processing Control Points 5 7 Peripheral Interrupt Control Registers 5 8 System Mode Register SYM 5 9 Interrupt Mask Register IMR 5 10 Interrupt Priority Register IPR 5 11 Interrupt Request Register IRQ 5 13 Interrupt Pending Function Types 5 14 Interrupt Source Polling Sequence 5 15 Interrupt Service Routines 5 15 Generating Interrupt Vector Ad...

Page 6: ...ON 7 4 Clock Output Control Register CLOCON 7 5 Stop Control Register STPCON 7 6 Chapter 8 RESET and Power Down System Reset 8 1 Overview 8 1 Normal Mode Reset Operation 8 1 Hardware Reset Values 8 2 Power Down Modes 8 4 Power Down Modes 8 4 Stop Mode 8 4 Idle Mode 8 5 Chapter 9 I O Ports Overview 9 1 Port Data Registers 9 1 Port 0 9 2 Port 1 9 5 Chapter 10 Basic Timer Overview 10 1 Basic Timer BT...

Page 7: ... Overview 12 1 8 bit Pulse Width Modulation PWMCON 12 2 Block Diagram 12 3 Chapter 13 Electrical Data Overview 13 1 Chapter 14 Mechanical Data Overview 14 1 Chapter 15 S3F80M Flash MCU Overview 15 1 Operating Mode Characteristics 15 5 Chapter 16 Development Tools Overview 16 1 SHINE 16 1 SAMA Assembler 16 1 SASM88 16 1 HEX2ROM 16 1 Target Boards 16 1 TB80M4 Target Board 16 3 SMDS2 Selection SAM8 1...

Page 8: ...Addressing 2 12 2 10 Common Working Register Area 2 13 2 11 4 Bit Working Register Addressing 2 15 2 12 4 Bit Working Register Addressing Example 2 15 2 13 8 Bit Working Register Addressing 2 16 2 14 8 Bit Working Register Addressing Example 2 17 2 15 Stack Operations 2 18 3 1 Register Addressing 3 2 3 2 Working Register Addressing 3 2 3 3 Indirect Register Addressing to Register File 3 3 3 4 Indi...

Page 9: ...llator fx 7 2 7 4 System Clock Circuit Diagram 7 3 7 5 System Clock Control Register CLKCON 7 4 7 6 Clock Output Control Register CLOCON 7 5 7 7 Clock Output Block Diagram 7 5 7 8 STOP Control Register STPCON 7 6 9 1 Port 0 High Byte Control Register P0CONH 9 3 9 2 Port 0 Low Byte Control Register P0CONL 9 3 9 3 Port 0 Interrupt Control Register 9 4 9 4 Port 0 Interrupt Pending Register P0PND 9 4 ...

Page 10: ...9 13 6 Operating Voltage Range 13 9 14 1 20 DIP 300A Package Dimensions 14 1 14 2 20 SOP 375 Package Dimensions 14 2 14 3 16 DIP 300A Package Dimensions 14 3 14 4 16 SOP 375 Package Dimensions 14 4 15 1 S3F80M4 Pin Assignments 20 DIP 300A 20 SOP 375 15 2 15 2 S3F80M4 Pin Assignments 16 DIP 300A 16 SOP 375 15 3 15 3 Operating Voltage Range 15 6 16 1 SMDS Product Configuration SMDS2 16 2 16 2 TB80M4...

Page 11: ...r Overview 5 6 5 3 Interrupt Source Control and Data Registers 5 8 6 1 Instruction Group Summary 6 2 6 2 Flag Notation Conventions 6 8 6 3 Instruction Set Symbols 6 8 6 4 Instruction Notation Conventions 6 9 6 5 Opcode Quick Reference 6 10 6 6 Condition Codes 6 12 8 1 S3C80M4 F80M4 Set 1 Register and Values after RESET 8 2 8 2 S3C80M4 F80M4 Set 1 Bank 0 Register and Values after RESET 8 3 9 1 S3C8...

Page 12: ... 13 7 Main Oscillation Stabilization Time 13 9 15 1 Descriptions of Pins Used to Read Write the EPROM 15 4 15 2 Comparison of S3F80M4 and F80M4 Features 15 4 15 3 Operating Mode Selection Criteria 15 5 15 4 D C Electrical Characteristics 15 5 16 1 Power Selection Settings for TB80M4 16 4 16 2 Main clock Selection Settings for TB80M4 16 4 16 3 Device Selection Settings for TB80M4 16 5 16 4 The SMDS...

Page 13: ... Using the Page Pointer for RAM clear Page 0 Page1 2 5 Setting the Register Pointers 2 9 Using the RPs to Calculate the Sum of a Series of Registers 2 10 Addressing the Common Working Register Area 2 14 Standard Stack Operations Using PUSH and POP 2 19 Chapter 7 Clock Circuit How to Use Stop Instruction 7 6 ...

Page 14: ...egister 4 11 P0CONH Port 0 Control Register High Byte 4 12 P0CONL Port 0 Control Register Low Byte 4 13 P0INT Port 0 Interrupt Control Register 4 14 P0PND Port 0 Interrupt Pending Register 4 15 P1CONH Port 1 Control Register High Byte 4 16 P1CONL Port 1 Control Register Low Byte 4 17 P1PUR Port 1 Pull up Resistor Enable Register 4 18 PP Register Page Pointer 4 19 PWMCON Pulse Width Modulation Cont...

Page 15: ...R 6 25 CALL Call Procedure 6 26 CCF Complement Carry Flag 6 27 CLR Clear 6 28 COM Complement 6 29 CP Compare 6 30 CPIJE Compare Increment and Jump on Equal 6 31 CPIJNE Compare Increment and Jump on Non Equal 6 32 DA Decimal Adjust 6 33 DEC Decrement 6 35 DECW Decrement Word 6 36 DI Disable Interrupts 6 37 DIV Divide Unsigned 6 38 DJNZ Decrement and Jump if Non Zero 6 39 EI Enable Interrupts 6 40 E...

Page 16: ...tack Decrementing 6 64 POPUI Pop User Stack Incrementing 6 65 PUSH Push to Stack 6 66 PUSHUD Push User Stack Decrementing 6 67 PUSHUI Push User Stack Incrementing 6 68 RCF Reset Carry Flag 6 69 RET Return 6 70 RL Rotate Left 6 71 RLC Rotate Left through Carry 6 72 RR Rotate Right 6 73 RRC Rotate Right through Carry 6 74 SB0 Select Bank 0 6 75 SB1 Select Bank 1 6 76 SBC Subtract with Carry 6 77 SCF...

Page 17: ...s fabricated using the highly advanced CMOS process Its design is based on the SAM88RC CPU core Stop and Idle Power down modes were implemented to reduce power consumption The S3C80M4 is a microcontroller with a 4K byte mask programmable ROM embedded The S3F80M4 is a microcontroller with a 4K byte Flash ROM embedded Using a proven modular design approach Samsung engineers have successfully develop...

Page 18: ...8 bit internal timer External event counter function 8 Bit High Speed PWM 8 bit PWM 1 ch 6 bit base 2 bit extension Oscillation Sources Crystal ceramic or RC for main clock Main clock frequency 0 4 MHz 10 MHz Two Power Down Modes Idle only CPU clock stops Stop selected system clock and CPU clock stop Power Consumption RUM Mode 4mA at 10MHz 5V Stop Mode 100uA at 5V Instruction Execution Times 400nS...

Page 19: ...U 4 Kbyte ROM 128 byte Register File VDD 8 Bit Timer Counter 0 T0OUT P1 0 T0CLK P1 1 I O Port 0 I O Port 1 P0 0 INT0 P0 1 INT1 P0 2 INT2 P0 3 INT3 P0 4 P0 5 P0 6 PWM P0 7 PWM Watchdog Timer Basic Timer XIN XOUT PWM P0 6 OSC P1 0 T0OUT P1 1 T0CLK P1 2 P1 3 P1 4 P1 5 P1 6 CLKOUT Figure 1 1 Block Diagram ...

Page 20: ...1 0 T0OUT P1 1 T0CLK P1 2 P1 3 P1 4 P1 5 S3C80M4 F80M4 20 DIP 300A 20 SOP 375 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 VDD P0 0 INT0 P0 1 INT1 P0 2 INT2 P0 3 INT3 P0 4 P0 5 P0 6 PWM P0 7 P1 6 CLKOUT Figure 1 2 S3C80M4 F80M4 Pin Assignments 20 DIP 300A 20 SOP 375 ...

Page 21: ...80M4 16 DIP 300A 16 SOP 375 VSS XIN XOUT nRESET P1 0 T0OUT P1 1 T0CLK P1 2 P1 3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD P0 0 INT0 P0 1 INT1 P0 2 INT2 P0 3 INT3 P0 4 P0 5 P0 6 PWM Figure 1 3 S3C80M4 F80M4 Pin Assignments 16 DIP 300A 16 SOP 375 ...

Page 22: ...itt trigger input or push pull open drain output and software assignable pull ups E 4 5 8 5 8 T0OUT T0CLK P1 4 P1 5 P1 6 I O I O port with bit programmable pins Input or push pull open drain output and software assignable pull ups E 2 9 11 CLKOUT INT0 INT3 I O External interrupts input pins D 4 19 16 15 12 P0 0 P0 3 T0CLK I O Timer 0 external clock input E 4 6 6 P1 1 T0OUT I O Timer 0 clock output...

Page 23: ...UITS P Channel N Channel In VDD Figure 1 4 Pin Circuit Type A In Schmitt Trigger Figure 1 5 Pin Circuit Type B VDD Output Disable Data Pull up Resistor VDD I O P CH N CH Open drain Enable Pull up Enable Figure 1 6 Pin Circuit Type E 2 P1 4 P1 6 ...

Page 24: ...sable Data Pull up Resistor VDD I O P CH N CH Pull up Enable IN Figure 1 7 Pin Circuit Type D 4 P0 VDD Output Disable Data Pull up Resistor VDD I O P CH N CH Schmitt Trigger Open drain Enable Resistor Enable Figure 1 8 Pin Circuit Type E 4 P1 0 P1 3 ...

Page 25: ...OM Internal register file A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addresses and data between the CPU and the register file The S3C80M4 has an internal 4 Kbyte mask programmable ROM The 256 byte physical register space is expanded into an addressable area of 320 bytes using addressing modes ...

Page 26: ...resses Unused locations in this address range can be used as normal program memory If you use the vector address area to store a program code be careful not to overwrite the vector addresses stored in these locations The ROM address at which a program execution starts after a reset is 0100H in the S3C80M4 S3C80M4 F80M4 Decimal 4 095 255 Hex FFFH 00H 0 4K bytes Internal Program Memory Area Interrup...

Page 27: ...general purpose use page 0 You can always address set 1 register locations regardless of which of the ten register pages is currently selected Set 1 locations however can only be addressed using register addressing modes The extension of register space into separately addressable areas sets banks and pages is supported by various addressing mode restrictions the select bank instructions SB0 and SB...

Page 28: ...ose Register Files All Addressing Modes FFH E0H DFH D0H CFH C0H System Control Registers Register Addressing Mode Working Registers Register Addressing Mode Peripheral Control Registers Register Addressing Mode Set1 64 Bytes Figure 2 2 Internal Register File Organization ...

Page 29: ...ter PP DFH Set 1 R W LSB MSB 7 6 5 4 3 2 1 0 Destination register page selection bits 0000 Destination Page 0 Others Not used for the S3C80M4 Source register page selection bits 0000 Source page 0 Others Not used for the S3C80M4 NOTE In the S3C80M4 microcontroller the internal register file is configured as eleven pages Pages 0 The pages 0 is used for general purpose register file Figure 2 3 Regis...

Page 30: ...her areas of the register file Registers in set 1 locations are directly accessible at all times using Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations C0H F...

Page 31: ...sing any of the seven addressing modes see Chapter 3 Addressing Modes The prime register area is immediately addressable following a reset FFH FCH E0H D0H C0H Set 1 Bank 0 Peripheral and I O General purpose CPU and system control LCD data register FFH C0H 00H 7FH Set 2 Not used for the S3C80M4 Page 0 Prime Space Bank 1 Not used for the S3C80M4 Figure 2 4 Set 1 Set2 Prime Area Register Map ...

Page 32: ... locations of selected working register spaces One working register slice is 8 bytes eight 8 bit working registers R0 R7 or R8 R15 One working register block is 16 bytes sixteen 8 bit working registers R0 R15 All the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one ...

Page 33: ...elected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RP0 point to the lower slice and RP1 point to the upper slice see Figure 2 6 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 7 RP0 points to the upper slice and RP1 to ...

Page 34: ...0 R1 ADC R0 R2 R0 R0 R2 C ADC R0 R3 R0 R0 R3 C ADC R0 R4 R0 R0 R4 C ADC R0 R5 R0 R0 R5 C The sum of these six registers 6FH is located in the register R0 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be...

Page 35: ... an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the least significan...

Page 36: ... Bank 1 Bank 0 NOTE In the S3C80M4 microcontroller pages 0 is implemented Pages 0 contain all of the addressable registers in the internal register file Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RP0 points to locations C0H C7H and RP1 to locations C8H CFH that is to the common working register area FFH C0H Se...

Page 37: ...ations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages FFH FCH E0H D0H C0H Set 1 Following a hardware reset register pointers RP0 and RP1 point to the common working register area locations C0H CFH RP0 RP1 1 1 0 0 0 0 0 0 1 ...

Page 38: ...he address bits are concatenated in the following way to form a complete 8 bit address The high order bit of the 4 bit address selects one of the register pointers 0 selects RP0 1 selects RP1 The five high order bits in the register pointer select an 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 ...

Page 39: ...bits Address OPCODE Selects RP0 or RP1 RP1 RP0 4 bit address provides three low order bits Figure 2 11 4 Bit Working Register Addressing Register address 76H RP0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 R6 0 1 1 0 1 1 1 0 Selects RP0 Instruction INC R6 OPCODE RP1 0 1 1 1 1 0 0 0 Figure 2 12 4 Bit Working Register Addressing Example ...

Page 40: ...ete address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 4 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provi...

Page 41: ...it address form instruction LD R11 R2 RP0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 Selects RP1 R11 Register address 0ABH RP1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 Specifies working register addressing Figure 2 14 8 Bit Working Register Addressing Example ...

Page 42: ...u can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack pointer SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and the least ...

Page 43: ...al register file using PUSH and POP instructions LD SPL 0FFH SPL FFH Normally the SPL is set to 0FFH by the initialization routine PUSH PP Stack address 0FEH PP PUSH RP0 Stack address 0FDH RP0 PUSH RP1 Stack address 0FCH RP1 PUSH R3 Stack address 0FBH R3 POP R3 R3 Stack address 0FBH POP RP1 RP1 Stack address 0FCH POP RP0 RP0 Stack address 0FDH POP PP PP Stack address 0FEH ...

Page 44: ...ADDRESS SPACES S3C80M4 F80M4 2 20 NOTES ...

Page 45: ...ine the location of the data operand The operands specified in SAM88RC instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are Register R Indirect Re...

Page 46: ...PCODE OPERAND 8 bit Register File Address Point to One Register in Register File One Operand Instruction Example Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Program Memory Register File Figure 3 1 Register Addressing dst OPCODE 4 bit Working Register Point to the Working Register 1 of 8 Two Operand Instruction Example Sample Instruction ADD R1 R2 Where R1 and R...

Page 47: ...r to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations C0H FFH in set 1 using the Indirect Register addressing mode dst Address of Operand used by Instruction OPCODE ADDRESS 8 bit Register File Address Point to One Register in Register File One Operand Instruction Example Sampl...

Page 48: ...IR Points to Register Pair Example Instruction References Program Memory Sample Instructions CALL RR2 JP RR2 Program Memory Register File Value used in Instruction OPERAND REGISTER Program Memory 16 Bit Address Points to Program Memory Figure 3 4 Indirect Register Addressing to Program Memory ...

Page 49: ...g Register Address Point to the Working Register 1 of 8 Sample Instruction OR R3 R6 Program Memory Register File src 3 LSBs Value used in Instruction OPERAND Selected RP points to start fo working register block RP0 or RP1 MSB Points to RP0 or RP1 Figure 3 5 Indirect Working Register Addressing to Register File ...

Page 50: ...ogram Memory Register File src Value used in Instruction OPERAND Example Instruction References either Program Memory or Data Memory Program Memory or Data Memory Next 2 bit Point to Working Register Pair 1 of 4 LSB Selects Register Pair 16 Bit address points to program memory or data memory RP0 or RP1 MSB Points to RP0 or RP1 Selected RP points to start of working register block Figure 3 6 Indire...

Page 51: ... added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction LD The LDC ...

Page 52: ... to start of working register block dst src OPCODE Program Memory x OFFSET 4 bit Working Register Address Sample Instructions LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed NEXT 2 Bits Register Pair Value used in Instruction 8 Bits 16 Bits 16 Bits Figure 3 8 Index...

Page 53: ...o start of working register block Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed NEXT 2 Bits Register Pair Value used in Instruction 8 Bits 16 Bits 16 Bits dst src OPCODE Program Memory src OFFSET 4 bit Working Register Address OFFSET Fig...

Page 54: ...ode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H Identical operation to LDC example except that external program memory is accessed dst src OPCODE Program Memory 0 or 1 Lower Address Byte LSB Select...

Page 55: ... Program Memory Lower Address Byte Memory Address Used Upper Address Byte Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Next OPCODE Figure 3 11 Direct Addressing for Call and Jump Instructions ...

Page 56: ...s mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Current Instruction Program Memory Locations 0 255 Program Memory OPCODE dst Lower Address Byte Upper Address Byte Next Instruction LSB Must be Zero Sample I...

Page 57: ...curs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR OPCODE Program Memory Displacement Program Memory Address Used Sample Instructions JR ULT OFFSET Where OFFSET is a value ...

Page 58: ...alue supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers The Operand value is in the instruction OPCODE Sample Instruction LD R0 0AAH Program Memory OPERAND Figure 3 14 Immediate Addressing ...

Page 59: ...ic peripheral is presented in the corresponding peripheral descriptions in Part II of this manual The locations and read write characteristics of all mapped registers in the S3C80M4 register file are listed in Table 4 1 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 Set 1 Registers Register Name Mnemonic Decimal Hex R W Locations D0 D2H a...

Page 60: ...ister PWMCON 232 E8H R W Locations E9 EEH are not mapped Port 1 Control Register High Byte P1CONH 240 EFH R W Port 1 Control Register Low Byte P1CONL 241 F0H R W Port 1 Pull up Resistor Enable Register P1PUR 242 F1H R W Port 0 Control Register High Byte P0CONH 243 F2H R W Port 0 Control Register Low Byte P0CONL 244 F3H R W Port 0 Interrupt Control Register P0INT 245 F4H R W Port 0 Interrupt Pendin...

Page 61: ...ual bit or related bits Full Register name Register ID Sign Flag S 0 Operation does not generate a carry or borrow condition 0 Operation generates carry out or borrow into high order bit 7 0 Operation result is a non zero value 0 Operation result is zero 0 Operation generates positive number MSB 0 0 Operation generates negative number MSB 1 Description of the effect of specific bit settings Set 1 ...

Page 62: ... 0 0 fxx 4096 0 1 fxx 1024 1 0 fxx 128 1 1 fxx 16 1 Basic Timer Counter Clear Bit 1 0 No effect 1 Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer and Timer Counters 2 0 No effect 1 Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to 00H Immediately following the write operation the BTCON 1 val...

Page 63: ...up Function Bit 0 Enable IRQ for main wake up in power down mode 1 Disable IRQ for main wake up in power down mode 6 5 Not used for the S3C80M4 4 3 CPU Clock System Clock Selection Bits note 0 0 fxx 16 0 1 fxx 8 1 0 fxx 2 1 1 fxx 2 0 Not used for the S3C80M4 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values ...

Page 64: ...Control Register E3H Set 1 Bank0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 Read Write R W R W Addressing Mode Register addressing mode only 7 2 Not used for the S3C80M4 1 0 Clock Output Frequency Selection Bits 0 0 fxx 64 0 1 fxx 16 1 0 fxx 8 1 1 fxx 4 ...

Page 65: ...g S 0 Operation generates a positive number MSB 0 1 Operation generates a negative number MSB 1 4 Overflow Flag V 0 Operation result is 127 or 128 1 Operation result is 127 or 128 3 Decimal Adjust Flag D 0 Add operation completed 1 Subtraction operation completed 2 Half Carry Flag H 0 No carry out of bit 3 or no borrow into bit 3 by addition or subtraction 1 Addition generated carry out of bit 3 o...

Page 66: ...Q6 Enable Bit External Interrupts P0 2 0 Disable mask 1 Enable unmask 5 Interrupt Level 5 IRQ5 Enable Bit External Interrupts P0 1 0 Disable mask 1 Enable unmask 4 Interrupt Level 4 IRQ4 Enable Bit External Interrupts P0 0 0 Disable mask 1 Enable unmask 3 Reserved 2 Interrupt Level 2 IRQ2 Enable Bit PWM 0 Disable mask 1 Enable unmask 1 Reserved 0 Interrupt Level 0 IRQ0 Enable Bit Timer 0 Match 0 D...

Page 67: ...s of the 16 bit instruction pointer address IP15 IP8 The lower byte of the IP address is located in the IPL register DBH IPL Instruction Pointer Low Byte DBH Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the l...

Page 68: ... 0 1 0 A B C 0 1 1 B A C 1 0 0 C A B 1 0 1 C B A 1 1 0 A C B 1 1 1 Group priority undefined 6 Interrupt Subgroup C Priority Control Bit 0 IRQ6 IRQ7 1 IRQ7 IRQ6 5 Interrupt Group C Priority Control Bit 0 IRQ5 IRQ6 IRQ7 1 IRQ6 IRQ7 IRQ5 3 Interrupt Subgroup B Priority Control Bit 0 IRQ3 IRQ4 1 IRQ4 IRQ3 2 Interrupt Group B Priority Control Bit 0 IRQ2 IRQ3 IRQ4 1 IRQ3 IRQ4 IRQ2 0 Interrupt Group A Pr...

Page 69: ...al Interrupts P0 3 0 Not pending 1 Pending 6 Level 6 IRQ6 Request Pending Bit External Interrupts P0 2 0 Not pending 1 Pending 5 Level 5 IRQ5 Request Pending Bit External Interrupts P0 1 0 Not pending 1 Pending 4 Level 4 IRQ4 Request Pending Bit External Interrupts P0 0 0 Not pending 1 Pending 3 Reserved 2 Level 2 IRQ2 Request Pending Bit PWM 0 Not pending 1 Pending 1 Reserved 0 Level 0 IRQ0 Reque...

Page 70: ... input mode with pull up resistor 1 0 Not available 1 1 Output mode push pull 5 4 P0 6 PWM 0 0 Schmitt trigger input mode 0 1 Schmitt trigger input mode with pull up resistor 1 0 Alternative function PWM 1 1 Output mode push pull 3 2 P0 5 0 0 Schmitt trigger input mode 0 1 Schmitt trigger input mode with pull up resistor 1 0 Not available 1 1 Output mode push pull 1 0 P0 4 0 0 Schmitt trigger inpu...

Page 71: ...er input mode with pull up resistor 1 0 Not available 1 1 Output mode push pull 5 4 P0 2 INT2 0 0 Schmitt trigger input mode 0 1 Schmitt trigger input mode with pull up resistor 1 0 Not available 1 1 Output mode push pull 3 2 P0 1 INT1 0 0 Schmitt trigger input mode 0 1 Schmitt trigger input mode with pull up resistor 1 0 Not available 1 1 Output mode push pull 1 0 P0 0 INT0 0 0 Schmitt trigger in...

Page 72: ...both falling and rising edge 5 4 P0 2 External interrupt INT2 Enable Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enable interrupt by both falling and rising edge 3 2 P0 1 External interrupt INT1 Enable Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enable interrupt by both falling a...

Page 73: ...t when write 0 1 P0 3 INT3 interrupt request is pending when read 2 P0 2 External Interrupt INT2 Pending Bit 0 Interrupt request is not pending When read Clear pending bit when write 0 1 P0 2 INT2 interrupt request is pending when read 1 P0 1 External Interrupt INT1 Pending Bit 0 Interrupt request is not pending When read Clear pending bit when write 0 1 P0 1 INT1 interrupt request is pending when...

Page 74: ...ode Register addressing mode only 7 6 Not used for the S3C80M4 5 4 P1 6 CLKOUT 0 0 Input mode 0 1 Output mode N channel open drain 1 0 Alternative function CLKOUT 1 1 Output mode push pull 3 2 P1 5 0 0 Input mode 0 1 Output mode N channel open drain 1 0 Not available 1 1 Output mode push pull 1 0 P1 4 0 0 input mode 0 1 Output mode N channel open drain 1 0 Not available 1 1 Output mode push pull ...

Page 75: ...ode 0 1 Output mode N channel open drain 1 0 Not available 1 1 Output mode push pull 5 4 P1 2 0 0 Schmitt trigger input mode 0 1 Output mode N channel open drain 1 0 Not available 1 1 Output mode push pull 3 2 P1 1 T0CLK 0 0 Schmitt trigger input mode T0CLK 0 1 Output mode N channel open drain 1 0 Not available 1 1 Output mode push pull 1 0 P1 0 T0OUT 0 0 Schmitt trigger input mode 0 1 Output mode...

Page 76: ...p Resistor Enable Bit 0 Pull up disable 1 Pull up enable 4 P1 4 Pull up Resistor Enable Bit 0 Pull up disable 1 Pull up enable 3 P1 3 Pull up Resistor Enable Bit 0 Pull up disable 1 Pull up enable 2 P1 2 Pull up Resistor Enable Bit 0 Pull up disable 1 Pull up enable 1 P1 1 Pull up Resistor Enable Bit 0 Pull up disable 1 Pull up enable 0 P1 0 Pull up Resistor Enable Bit 0 Pull up disable 1 Pull up ...

Page 77: ... Mode Register addressing mode only 7 4 Destination Register Page Selection Bits 0 0 0 0 Destination page 0 Others Not used for the S3C80M4 3 0 Source Register Page Selection Bits 0 0 0 0 Source page 0 Others Not used for the S3C80M4 NOTE In the S3C80M4 microcontroller the internal register file is configured as one pages pages 0 The page 0 is used for general purpose register file ...

Page 78: ...oad Interval Selection Bit 0 Reload from 8 bit up counter overflow 1 Reload from 6 bit up counter overflow 3 PWM Counter Clear Bit 0 No effect 1 Clear the PWM counter when write 2 PWM Counter Enable Bit 0 Counter STOP 1 Counter RUN Resume countering 1 PWM Overflow Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt 0 PWM Overflow Interrupt Pending Bit 0 Interrupt is not pending when read C...

Page 79: ...ints to address C0H in register set 1 selecting the 8 byte working register slice C0H C7H 2 0 Not used for the S3C80M4 RP1 Register Pointer 1 D7H Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 byte working register are...

Page 80: ... SP8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset SPL Stack Pointer Low Byte D9H Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address Low Byte The low byte stack pointer value is the lower eight bits o...

Page 81: ...te R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 STOP Control Bits 1 0 1 0 0 1 0 1 Enable stop instruction Other values Disable stop instruction NOTE Before execute the STOP instruction You must set this STPCON register as 10100101b Otherwise the STOP instruction will not execute as well as reset will be generated ...

Page 82: ...RQ4 1 0 1 IRQ5 1 1 0 IRQ6 1 1 1 IRQ7 1 Fast Interrupt Enable Bit 2 0 Disable fast interrupt processing 1 Enable fast interrupt processing 0 Global Interrupt Enable Bit 3 0 Disable all interrupt processing 1 Enable all interrupt processing NOTES 1 You can select only one interrupt level at a time for fast interrupt processing 2 Setting SYM 1 to 1 enables fast interrupt processing for the interrupt ...

Page 83: ...alling edge 1 1 0 External clock T0CLK rising edge 1 1 1 Counter stop 4 Not used for the S3C80M4 3 Timer 0 Counter Clear Bit 0 No effect 1 Clear the timer 0 counter when write 2 Timer 0 Counter Enable Bit 0 Disable counting operation 1 Enable counting operation 1 Timer 0 Match Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt 0 Timer 0 Interrupt Pending Bit 0 Interrupt request is not pen...

Page 84: ...CONTROL REGISTERS S3C80M4 F80M4 4 26 NOTES ...

Page 85: ... levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more inte...

Page 86: ... the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V1 one source S1 Type 2 One level IRQn one vector V1 multiple sources S1 Sn Type 3 One level IRQn multiple vectors V1 Vn multiple sources S1 Sn Sn 1 Sn m In the S3C80M4 microcontroller two interrupt types are implemented Vectors Sources Levels S1 V1 S2 Type 2 IRQn S3 Sn V1 S1 V2 S2 T...

Page 87: ... first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate ...

Page 88: ... see Figure 5 3 You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H S3C80M4 F80M4 Decimal 4 095 255 Hex FFFH 00H 0 4K bytes Internal Program Memory Area Interrupt Vector Area FFH Figure 5 3 ROM Vector...

Page 89: ...al Value Hex Value Interrupt Level H W S W 256 100H Basic timer overflow Reset 238 EEH Timer 0 match IRQ0 236 ECH Reserved IRQ1 234 EAH PWM interrupt IRQ2 232 E8H Reserved IRQ3 230 E6H P0 0 external interrupt IRQ4 228 E4H P0 1 external interrupt IRQ5 226 E2H P0 2 external interrupt IRQ6 224 E0H P0 3 external interrupt IRQ7 ...

Page 90: ...lags for each interrupt level as opposed to each interrupt source The system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register ID R W Function Description Interrupt mask register IMR R W Bit settings in the IMR registe...

Page 91: ...ble settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the necessary register file address register pointer information Interrupt Request Register Read only IRQ0 IRQ7 Interrupts Interrupt Mask Regi...

Page 92: ...Interrupt Level Register s Location s in Set 1 Timer 0 match IRQ0 T0CON T0DATA T0CNT E6H bank 0 E5H bank 0 E4H bank 0 Reserved IRQ1 PWM interrupt IRQ2 PWMCON PWMDATA E8H bank 0 E7H bank 0 Reserved IRQ3 P0 0 external interrupt IRQ4 P0CONL P0INT P0PND F3H bank 0 F4H bank 0 F5H bank 0 P0 1 external interrupt IRQ5 P0CONL P0INT P0PND F3H bank 0 F4H bank 0 F5H bank 0 P0 2 external interrupt IRQ6 P0CONL ...

Page 93: ... the normal operation it is recommended to use the EI and DI instructions for this purpose System Mode Register SYM DEH Set 1 R W 7 6 5 4 3 2 1 0 MSB LSB Global interrupt enable bit 3 0 Disable all interrupts processing 1 Enable all interrupts processing Fast interrupt enable bit 2 0 Disable fast interrupts processing 1 Enable fast interrupts processing Fast interrupt level selection bits 1 0 0 0 ...

Page 94: ... cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set 1 R W 7 6 5 4 3 2 1 0 MSB LSB Reserved IRQ2 IRQ4 IRQ5 I...

Page 95: ...that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 Group A IRQ0 IRQ1 Group B IRQ2 IRQ3 IRQ4 Group C IRQ5 IRQ6 IRQ7 IPR Group B IPR Group C IRQ2 B1 IRQ4 B2 IRQ3 B22 B21 IRQ5 C1 IRQ7 C2 IRQ6 C22 C21 IPR Group A IRQ1 A2 IRQ0 A1 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the re...

Page 96: ... 1 IRQ1 IRQ0 Subgroup B 0 IRQ3 IRQ4 1 IRQ4 IRQ3 Group C 0 IRQ5 IRQ6 IRQ7 1 IRQ6 IRQ7 IRQ5 Subgroup C 0 IRQ6 IRQ7 1 IRQ7 IRQ6 Group B 0 IRQ2 IRQ3 IRQ4 1 IRQ3 IRQ4 IRQ2 Group priority 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Undefined B C A A B C B A C C A B C B A A C B Undefined D7 D4 D1 Figure 5 8 Interrupt Priority Register IPR ...

Page 97: ...me using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however st...

Page 98: ...ting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the S3C80M4 interrupt structure the timer 0 overflow interrupt IRQ0 belongs to this category of interrupts in which pending condition is cleared automat...

Page 99: ...SYM 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one levels are currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates an interrupt mac...

Page 100: ...e to the stack PUSH IMR 2 Load the IMR register with a new mask value that enables only the higher priority interrupt 3 Execute an EI instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR 5 Execute...

Page 101: ...e FLAG register values are written to the FLAGS FLAGS prime register 3 The fast interrupt status bit in the FLAGS register is set 4 The interrupt is serviced 5 Assuming that the fast interrupt status bit is set when the fast interrupt service routine ends the instruction pointer and PC values are swapped back 6 The content of FLAGS FLAGS prime is copied automatically back to the FLAGS register 7 T...

Page 102: ...INTERRUPT STRUCTURE S3C80M4 F80M4 5 18 NOTES ...

Page 103: ... and shift operations DATA TYPES The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working re...

Page 104: ...c Load external data memory and increment LDCI dst src Load program memory and increment LDEPD dst src Load external data memory with pre decrement LDCPD dst src Load program memory with pre decrement LDEPI dst src Load external data memory with pre increment LDCPI dst src Load program memory with pre increment LDW dst src Load word POP dst Pop from stack POPUD dst src Pop user stack decrementing ...

Page 105: ...carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ...

Page 106: ...src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit rese...

Page 107: ...ight RRC dst Rotate right through carry SRA dst Shift right arithmetic SWAP dst Swap nibbles CPU Control Instructions CCF Complement carry flag DI Disable interrupts EI Enable interrupts IDLE Enter Idle mode NOP No operation RCF Reset carry flag SB0 Set bank 0 SB1 Set bank 1 SCF Set carry flag SRP src Set register pointers SRP0 src Set register pointer 0 SRP1 src Set register pointer 1 STOP Enter ...

Page 108: ...et or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneousl...

Page 109: ...tions D Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition H Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a su...

Page 110: ...o logic one Set or cleared according to operation Value is unaffected x Value is undefined Table 6 3 Instruction Set Symbols Symbol Description dst Destination operand src Source operand Indirect register address prefix PC Program counter IP Instruction pointer FLAGS Flags register D5H RP Register pointer Immediate operand or register address prefix H Hexadecimal number suffix D Decimal number suf...

Page 111: ...even number only Ir Indirect working register only Rn n 0 15 IR Indirect register or indirect working register Rn or reg reg 0 255 n 0 15 Irr Indirect working register pair only RRp p 0 2 14 IRR Indirect register pair or indirect working register pair RRp or reg reg 0 254 even only where p 0 2 14 X Indexed addressing mode reg Rn reg 0 255 n 0 15 XS Indexed short offset addressing mode addr RRp add...

Page 112: ...CM r1 Ir2 TCM R2 R1 TCM IR2 R1 TCM R1 IM BAND r0 Rb I 7 PUSH R2 PUSH IR2 TM r1 r2 TM r1 Ir2 TM R2 R1 TM IR2 R1 TM R1 IM BIT r1 b B 8 DECW RR1 DECW IR1 PUSHUD IR1 R2 PUSHUI IR1 R2 MULT R2 RR1 MULT IR2 RR1 MULT IM RR1 LD r1 x r2 B 9 RL R1 RL IR1 POPUD IR2 R1 POPUI IR2 R1 DIV R2 RR1 DIV IR2 RR1 DIV IM RR1 LD r2 x r1 L A INCW RR1 INCW IR1 CP r1 r2 CP r1 Ir2 CP R2 R1 CP IR2 R1 CP R1 IM LDC r1 Irr2 xL E...

Page 113: ...P LOWER NIBBLE HEX 8 9 A B C D E F U 0 LD r1 R2 LD r2 R1 DJNZ r1 RA JR cc RA LD r1 IM JP cc DA INC r1 NEXT P 1 ENTER P 2 EXIT E 3 WFI R 4 SB0 5 SB1 N 6 IDLE I 7 STOP B 8 DI B 9 EI L A RET E B IRET C RCF H D SCF E E CCF X F LD r1 R2 LD r2 R1 DJNZ r1 RA JR cc RA LD r1 IM JP cc DA INC r1 NOP ...

Page 114: ...1110 note NZ Not zero Z 0 1101 PL Plus S 0 0101 MI Minus S 1 0100 OV Overflow V 1 1100 NOV No overflow V 0 0110 note EQ Equal Z 1 1110 note NE Not equal Z 0 1001 GE Greater than or equal S XOR V 0 0001 LT Less than S XOR V 1 1010 GT Greater than Z OR S XOR V 0 0010 LE Less than or equal Z OR S XOR V 1 1111 note UGE Unsigned greater than or equal C 0 0111 note ULT Unsigned less than C 1 1011 UGT Un...

Page 115: ...cing The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and address...

Page 116: ... if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Examples Given R1 10H R2 03H...

Page 117: ...ame sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if a carry from the low order nibble occurred Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 R R 6 05 R IR opc dst src 3 6 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH ADD R1 R2 R1 15H R2 03H ADD R1 R2 R1 1CH ...

Page 118: ...rwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 R R 6 55 R IR opc dst src 3 6 56 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH AND R1 R2 R1 02H R2 03H AND R1 R2 R1 02H R2 03H AND 01H 02H Register 01H 01H register 02H 03H AND 01H 02H Register 01H 00H regi...

Page 119: ...Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst b 0 src 3 6 67 r0 Rb opc src b 1 dst 3 6 67 Rb r0 NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H and register 01H 05H BAND R1 01H 1 R1 06H register 01H 05H BAND 01H 1 R1 Register 01H 0...

Page 120: ... Cycles Opcode Hex Addr Mode dst src opc dst b 0 src 3 6 17 r0 Rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H and register 01H 01H BCP R1 01H 1 R1 07H register 01H 01H If destination working register R1 contains the value 07H 00000111B and the source regist...

Page 121: ...at Bytes Cycles Opcode Hex Addr Mode dst opc dst b 0 2 4 57 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITC R1 1 R1 05H If working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination and leaves the...

Page 122: ...d Format Bytes Cycles Opcode Hex Addr Mode dst opc dst b 0 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITR R1 1 R1 05H If the value of working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination register R1 leav...

Page 123: ...at Bytes Cycles Opcode Hex Addr Mode dst opc dst b 1 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITS R1 3 R1 0FH If working register R1 contains the value 07H 00000111B the statement BITS R1 3 sets bit three of the destination register R1 to 1 le...

Page 124: ...f the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Examples Given R1 07H and register 01H 03H BOR R1 01H 1 R1 07H register 01H 03H BOR 01H 2 R1 Register 01H 07H R1 07H In the first example destination working register R1 contains the value 07H 00000111B and source register 01H the value 03H 00000011B ...

Page 125: ...cted Format Note 1 Bytes Cycles Opcode Hex Addr Mode dst src opc src b 0 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRF SKIP R1 3 PC jumps to SKIP location If working register R1 contains the value 07H 00000111B the statement BTJRF SKIP R1 3...

Page 126: ...d Format Note 1 Bytes Cycles Opcode Hex Addr Mode dst src opc src b 1 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 00000111B the statement BTJRT SKIP R1 1 tests bit one in the source ...

Page 127: ...st src opc dst b 0 src 3 6 27 r0 Rb opc src b 1 dst 3 6 27 Rb r0 NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H 00000111B and register 01H 03H 00000011B BXOR R1 01H 1 R1 06H register 01H 03H BXOR 01H 2 R1 Register 01H 07H R1 07H In the first...

Page 128: ...e instruction CALL RR0 SP 0000H 0000H 1AH 0001H 49H CALL 40H SP 0000H 0000H 1AH 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location 0000H The PC is then loaded with the value 3521H the address of the first ins...

Page 129: ...y flag is changed to logic zero if C 0 the value of the carry flag is changed to logic one Flags C Complemented No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 EF Example Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register 0D5H changing its value from logic zero to logic one ...

Page 130: ...pc dst 2 4 B0 R 4 B1 IR Examples Given Register 00H 4FH register 01H 02H and register 02H 5EH CLR 00H Register 00H 00H CLR 01H Register 01H 02H register 02H 00H In Register R addressing mode the statement CLR 00H clears the destination register 00H value to 00H In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to 00H ...

Page 131: ...d Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 60 R 4 61 IR Examples Given R1 07H and register 07H 0F1H COM R1 R1 0F8H COM R1 R1 07H register 07H 0EH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value 0F8H 11111000B In the sec...

Page 132: ... src dst 3 6 A4 R R 6 A5 R IR opc dst src 3 6 A6 R IM Examples 1 Given R1 02H and R2 03H CP R1 R2 Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are 1 2 Given ...

Page 133: ... Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst RA 3 12 C2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Example Given R1 02H R2 03H and register 03H 02H CPIJE R1 R2 SKIP R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The statement C...

Page 134: ...les Opcode Hex Addr Mode dst src opc src dst RA 3 12 D2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Example Given R1 02H R2 03H and register 03H 04H CPIJNER1 R2 SKIP R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value 03H and general register 03 the value 04H The statement CPIJNE...

Page 135: ...efore DA Bits 4 7 Value Hex H Flag Before DA Bits 0 3 Value Hex Number Added to Byte Carry After DA 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1 0 3 06 0 ADD 0 A F 0 0 9 60 1 ADC 0 9 F 0 A F 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 SUB 0 0 8 1 6 F FA 06 0 SBC 1 7 F 0 0 9 A0 60 1 1 6 F 1 6 F 9A 66 1 Flags C Set if there was a carry from the most sign...

Page 136: ...nd 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0 0 0 1 0 1 0 1 15 0 0 1 0 0 1 1 1 27 0 0 1 1 1 1 0 0 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 42 Assuming the same values given above th...

Page 137: ...d cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 00 R 4 01 IR Examples Given R1 03H and register 03H 10H DEC R1 R1 02H DEC R1 Register 03H 0FH In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements...

Page 138: ...les Opcode Hex Addr Mode dst opc dst 2 8 80 RR 8 81 IR Examples Given R0 12H R1 34H R2 30H register 30H 0FH and register 31H 21H DECW RR0 R0 12H R1 33H DECW R2 Register 30H 0FH register 31H 20H In the first example destination register R0 contains the value 12H and register R1 the value 34H The statement DECW RR0 addresses R0 and the following operand R1 as a 16 bit word and decrements the value o...

Page 139: ...ective interrupt pending bits but the CPU will not service them while interrupt processing is disabled Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 8F Example Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending and interrupt...

Page 140: ...tient 1 cleared otherwise V Set if quotient is 28 or if divisor 0 cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Examples Given R0 10H R1 03H R2 40H register 40H 80H DIV RR0 R2 R0 03H R1 40H DIV RR0 R2...

Page 141: ...being used as a counter should be set at the one of location 0C0H to 0CFH with SRP SRP0 or SRP1 instruction Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst r opc dst 2 8 jump taken rA RA 8 no jump r 0 to F Example Given R1 02H and LOOP is the label of a relative address SRP 0C0H DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is ...

Page 142: ... pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the EI instruction Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 9F Example Given SYM 00H EI If the SYM register contains the value 00H that is if interrupts are currently disabled the statement EI sets the SYM register to 01H enabling all interrupts ...

Page 143: ...by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 1F Example The diagram below shows one example of how to use an ENTER statement 0050 IP 0022 SP 22 Data Address Data 0040 PC 40 41 42 43 Enter Address H Address L Address H Address Data 1F 01 10 Memory 0043 IP 0020 SP 20 21 22 IPH IP...

Page 144: ...er is then loaded into the program counter and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 internal stack 2F 16 internal stack Example The diagram below shows one example of how to use an EXIT statement 0050 IP 0022 SP Address Data 0040 PC Address Data Memory 0052 IP 0022 SP Address Data 0060 PC Address Data Memory Stack Stack B...

Page 145: ... clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc 1 4 6F Example The instruction IDLE stops the CPU clock but not the system clock ...

Page 146: ...ode dst dst opc 1 4 rE r r 0 to F opc dst 2 4 20 R 4 21 IR Examples Given R0 1BH register 00H 0CH and register 1BH 0FH INC R0 R0 1CH INC 00H Register 00H 0DH INC R0 R0 1BH register 01H 10H In the first example if destination working register R0 contains the value 1BH the statement INC R0 leaves the value 1CH in that same register The next example shows the effect an INC instruction has on register...

Page 147: ...register 02H 0FH and register 03H 0FFH INCW RR0 R0 1AH R1 03H INCW R1 Register 02H 10H register 03H 00H In the first example the working register pair RR0 contains the value 1AH in register R0 and 02H in register R1 The statement INCW RR0 increments the 16 bit destination by one leaving the value 03H in register R1 In the second example the statement INCW R1 uses Indirect Register IR addressing mo...

Page 148: ...T Fast Bytes Cycles Opcode Hex opc 1 6 BF Example In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine normally is a jump t...

Page 149: ... 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 In the first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Examples Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL_W LABEL_W 1000H PC 1000H JP 00H PC 0120H The first example shows a conditional JP Assuming that th...

Page 150: ...e original value of the program counter is taken to be the address of the first instruction byte following the JR statement Flags No flags are affected Format 1 Bytes Cycles Opcode Hex Addr Mode dst cc opc dst 2 6 ccB RA cc 0 to F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits Example Given The carry flag 1 and LABEL_X 1FF7H JR C LABE...

Page 151: ...contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src dst opc src 2 4 rC r IM 4 r8 r R src opc dst 2 4 r9 R r r 0 to F opc dst src 2 4 C7 r lr 4 D7 Ir r opc src dst 3 6 E4 R R 6 E5 R IR opc dst src 3 6 E6 R IM 6 D6 IR IM opc src dst 3 6 F5 IR R opc dst src x 3 6 87 r x r opc src dst x 3 6 97 x r r ...

Page 152: ...ster 01H 20H LD 01H R0 Register 01H 01H R0 01H LD R1 R0 R1 20H R0 01H LD R0 R1 R0 01H R1 0AH register 01H 0AH LD 00H 01H Register 00H 20H register 01H 20H LD 02H 00H Register 02H 20H register 00H 01H LD 00H 0AH Register 00H 0AH LD 00H 10H Register 00H 01H register 01H 10H LD 00H 02H Register 00H 01H register 01H 02 register 02H 02H LD R0 LOOP R1 R0 0FFH R1 0AH LD LOOP R0 R1 Register 31H 0AH R0 01H...

Page 153: ...ats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R0 06H and general register 00H 05H LDB R0 00H 2 R0 07H register 00H 05H LDB 00H 0 R0 R0 06H register 00H 04H In the first example destination working register R0 contains the value 06H and the source general register 00H the value 05H The statement LD R0...

Page 154: ...12 E7 r XS rr 4 opc src dst XS 3 12 F7 XS rr r 5 opc dst src XLL XLH 4 14 A7 r XL rr 6 opc src dst XLL XLH 4 14 B7 XL rr r 7 opc dst 0000 DAL DAH 4 14 A7 r DA 8 opc src 0000 DAL DAH 4 14 B7 DA r 9 opc dst 0001 DAL DAH 4 14 A7 r DA 10 opc src 0001 DAL DAH 4 14 B7 DA r NOTES 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 For formats 3 and 4 the destin...

Page 155: ...cation 0105H 01H RR2 R0 6DH R2 01H R3 04H LDE R0 01H RR2 R0 contents of external data memory location 0105H 01H RR2 R0 7DH R2 01H R3 04H LDC note 01H RR2 R0 11H contents of R0 is loaded into program memory location 0105H 01H 0104H LDE 01H RR2 R0 11H contents of R0 is loaded into external data memory location 0105H 01H 0104H LDC R0 1000H RR2 R0 contents of program memory location 1104H 1000H 0104H ...

Page 156: ...ected LDCD references program memory and LDED references external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 10 E2 r Irr Examples Given R6 10H R7 33H R8 12H program memory location 1033H 0CDH and external data memory location 1033H 0DDH LDCD R8 RR6...

Page 157: ...naffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Irr even for program memory and odd for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 10 E3 r Irr Examples Given R6 10H R7 33H R8 12H program memory locations 1033H 0CDH and 1034H 0C5H external data memory locations 1033H 0DDH and 1034H 0D5H L...

Page 158: ...ocation The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes Irr an even number for program memory and an odd number for external data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 2 14 F2 Irr r Examples Given R0 77H R6 30H and R7 00H LDCPD RR6 R0 RR6 RR6 1 77H content...

Page 159: ... location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 2 14 F3 Irr r Examples Given R0 7FH R6 21H and R7 0FFH LDCPI RR6 R0 RR6 RR6 1 7FH contents of R...

Page 160: ...03H and register 03H 0FH LDW RR6 RR4 R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H Register 00H 03H register 01H 0FH register 02H 03H register 03H 0FH LDW RR2 R7 R2 03H R3 0FH LDW 04H 01H Register 04H 03H register 05H 0FH LDW RR6 1234H R6 12H R7 34H LDW 02H 0FEDH Register 02H 0FH register 03H 0EDH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H ...

Page 161: ...e result is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Examples Given Register 00H 20H register 01H 03H register 02H 09H register 03H 06H MULT 00H 02H Register 00H 01H register 01H 20H register 02H 09H MULT 00H 01H Register 00H 00H register 01H 0C0H MULT 00H 30H Register 00H 06H registe...

Page 162: ...ogram counter The instruction pointer is then incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 10 0F Example The following diagram shows one example of how to use the NEXT instruction Data 01 10 Before After 0045 IP Address Data 0130 PC 43 44 45 Address H Address L Address H Address Data Memory 130 Routine 0043 IP Address Data 0120 PC 43 44 45 Address H Address L...

Page 163: ...truction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 FF Example When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ...

Page 164: ... Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 R R 6 45 R IR opc dst src 3 6 46 R IM Examples Given R0 15H R1 2AH R2 01H register 00H 08H register 01H 37H and register 08H 8AH OR R0 R1 R0 3FH R1 2AH OR R0 R2 R0 37H R2 01H register 01H 37H OR 00H 01H Register 00H 3FH register 01H 37H OR 01H 00H Register 00H 08H register 01H 0BFH OR 00H 02H Regi...

Page 165: ... opc dst 2 8 50 R 8 51 IR Examples Given Register 00H 01H register 01H 1BH SPH 0D8H 00H SPL 0D9H 0FBH and stack register 0FBH 55H POP 00H Register 00H 55H SP 00FCH POP 00H Register 00H 01H register 01H 55H SP 00FCH In the first example general register 00H contains the value 01H The statement POP 00H loads the contents of location 00FBH 55H into destination register 00H and then increments the sta...

Page 166: ... decremented Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 8 92 R IR Example Given Register 00H 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H Register 00H 41H register 02H 6FH register 42H 6FH If general register 00H contains the value 42H and register 42H the value 6FH the statement POPUD 02H 00H loads the contents...

Page 167: ...pointer is then incremented Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 8 93 R IR Example Given Register 00H 01H and register 01H 70H POPUI 02H 00H Register 00H 02H register 01H 70H register 02H 70H If general register 00H contains the value 01H and register 01H the value 70H the statement POPUI 02H 00H loads the value 70H into the destination general...

Page 168: ... internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Examples Given Register 40H 4FH register 4FH 0AAH SPH 00H and SPL 00H PUSH 40H Register 40H 4FH stack register 0FFH 4FH SPH 0FFH SPL 0FFH PUSH 40H Register 40H 4FH register 4FH 0AAH stack register 0FFH 0AAH SPH 0FFH SPL 0FFH In the first example if the stack pointer contains the value 0000H and general register 40H the v...

Page 169: ...k pointer Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 3 8 82 IR R Example Given Register 00H 03H register 01H 05H and register 02H 1AH PUSHUD 00H 01H Register 00H 02H register 01H 05H register 02H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUD 00H 01H decrements the user stack pointer by one leaving th...

Page 170: ...r stack pointer Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 3 8 83 IR R Example Given Register 00H 03H register 01H 05H and register 04H 2AH PUSHUI 00H 01H Register 00H 04H register 01H 05H register 04H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leav...

Page 171: ...RCF Operation C 0 The carry flag is cleared to logic zero regardless of its previous value Flags C Cleared to 0 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 CF Example Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero ...

Page 172: ...executed is the one that is addressed by the new program counter value Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 8 internal stack AF 10 internal stack Example Given SP 00FCH SP 101AH and PC 1234 RET PC 101AH SP 00FEH The statement RET pops the contents of stack pointer location 00FCH 10H into the high byte of the program counter The stack pointer then pops the value in locat...

Page 173: ...s 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 90 R 4 91 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H RL 00H Register 00H 55H C 1 RL 01H Register 01H 02H register 02H 2EH C 0 In the first example if general...

Page 174: ...hmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 10 R 4 11 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H C 0 RLC 00H Register 00H 54H C 1 RLC 01H Register 01H 02H register 02H 2EH C 0 In the first example if general register 00H has...

Page 175: ...occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 E0 R 4 E1 IR Examples Given Register 00H 31H register 01H 02H and register 02H 17H RR 00H Register 00H 98H C 1 RR 01H Register 01H 02H register 02H 8BH C 1 In the first example if general register 00H contains the value 31H 001...

Page 176: ...metic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 C0 R 4 C1 IR Examples Given Register 00H 55H register 01H 02H register 02H 17H and C 0 RRC 00H Register 00H 2AH C 1 RRC 01H Register 01H 02H register 02H 0BH C 1 In the first example if general register 00H conta...

Page 177: ...ars the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The statement SB0 clears FLAGS 0 to 0 selecting bank 0 register addressing ...

Page 178: ... register FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the register file Bank 1 is not implemented in some S3C8 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 5F Example The statement SB1 sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented ...

Page 179: ...that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 R R 6 35 R IR opc...

Page 180: ...Carry Flag SCF Operation C 1 The carry flag C is set to logic one regardless of its previous value Flags C Set to 1 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 DF Example The statement SCF sets the carry flag to logic one ...

Page 181: ... Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 D0 R 4 D1 IR Examples Given Register 00H 9AH register 02H 03H register 03H 0BCH and C 1 SRA 00H Register 00H 0CD C 0 SRA 02H Register 02H 03H register 03H 0DEH C 0 In the first example if general register 00H contains the value 9AH 10011010B the ...

Page 182: ...to write one or both of the register pointers RP0 and RP1 Bits 3 7 of the selected register pointer are written unless both register pointers are selected RP0 3 is then cleared to logic zero and RP1 3 is set to logic one Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode src opc src 2 4 31 IM Examples The statement SRP 40H sets register pointer 0 RP0 at location 0D6H to 40H and r...

Page 183: ...rs peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc 1 4 7F Example The statement ...

Page 184: ...herwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 R R 6 25 R IR opc dst src 3 6 26 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH SUB R1 R2 R1 0FH R2 ...

Page 185: ...t 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 F0 R 4 F1 IR Examples Given Register 00H 3EH register 02H 03H and register 03H 0A4H SWAP 00H Register 00H 0E3H SWAP 02H Register 02H 03H register 03H 4AH In the first example if general register 00H contains the value 3EH 00111110B the statement SWAP 00H swaps the lower and u...

Page 186: ...eared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 R R 6 65 R IR opc dst src 3 6 66 R IM Examples Given R0 0C7H R1 02H R2 12H register 00H 2BH register 01H 02H and register 02H 23H TCM R0 R1 R0 0C7H R1 02H Z 1 TCM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TCM 00H 01H Register 00H 2BH register 01H 02H Z 1 TCM 00H...

Page 187: ...ed Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 R R 6 75 R IR opc dst src 3 6 76 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H TM R0 R1 R0 0C7H R1 02H Z 0 TM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TM 00H 01H Register 00H 2BH register 01H 02H Z 0 TM 00H 01H Register 00H 2BH register 01H 02H...

Page 188: ...released by an internal interrupt including a fast interrupt Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4n 3F n 1 2 3 Example The following sample program structure shows the sequence of operations that follow a WFI statement EI WFI Next instruction Main program Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed Enable global interr...

Page 189: ...naffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 B2 r r 6 B3 r lr opc src dst 3 6 B4 R R 6 B5 R IR opc dst src 3 6 B6 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H XOR R0 R1 R0 0C5H R1 02H XOR R0 R1 R0 0E4H R1 02H register 02H 23H XOR 00H 01H Register 00H 29H register 01H 02H XOR 00H 01H Register 00H 08H regi...

Page 190: ...INSTRUCTION SET S3C80M4 F80M4 6 88 NOTES ...

Page 191: ...M CLOCK CIRCUIT The system clock circuit has the following components External crystal or ceramic resonator oscillation source or an external clock source Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 System clock control register CLKCON Clock output control register CLOCON STOP control register STPCON CPU CLOCK NOTATION In this d...

Page 192: ...CLOCK CIRCUIT S3C80M4 F80M4 7 2 MAIN OSCILLATOR CIRCUITS XIN XOUT Figure 7 1 Crystal Ceramic Oscillator fx XIN XOUT Figure 7 2 External Oscillator fx XIN XOUT R Figure 7 3 RC Oscillator fx ...

Page 193: ...terrupt too when the sub system oscillator is running and watch timer is operating with sub system clock In Idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers and timer counters Idle mode is released by a reset or by an external or internal interrupt 1 1 1 4096 Frequency Dividing Circuit Main System Oscillator Circuit INT Selector STPCON STOP OSC inst CLK...

Page 194: ... CPU clock speed fxx 8 fxx 2 or fxx 1 System Clock Control Register CLKCON D4H Set 1 R W 7 6 5 4 3 2 1 0 MSB LSB Not used for the S3C80M4 Not used for the S3C80M4 Divide by selection bits for CPU clock frequency 00 fXX 16 01 fXX 8 10 fXX 2 11 fXX 1 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster speeds load the appropriate values to CLKCON 3 and ...

Page 195: ... Selection After a reset fxx 64 is select for Clock Output Frequency because the reset value of CLOCON 1 0 is 0 Clock Output Control Register CLOCON E3H Set 1 bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB Clock Output Frequency Selection Bits 00 fxx 64 01 fxx 16 10 fxx 8 11 fxx 4 Not used for the S3C80M4 Figure 7 6 Clock Output Control Register CLOCON CLOCON 1 0 CLKOUT MUX fxx 64 fxx 16 fxx 8 fxx 4 P1CONH 5 ...

Page 196: ...l Register STPCON FBH Set 1 bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB STOP Control bits Other values Disable STOP instruction 10100101 Enable STOP instruction NOTE Before executing the STOP instruction set the STPCON register as 10100101b Otherwise the STOP instruction will not be executed and reset will be generated Figure 7 8 STOP Control Register STPCON PROGRAMMING TIP How to Use Stop Instruction This...

Page 197: ... the following sequence of events occurs during a reset operation All interrupt is disabled The watchdog function basic timer is enabled Ports 0 1 and set to input mode and all pull up resistors are disabled for the I O port Peripheral control and data register settings are disabled and reset to their default hardware values The program counter PC is loaded with the program reset address in the RO...

Page 198: ...Name Mnemonic Address Bit Values After RESET Dec Hex 7 6 5 4 3 2 1 0 Locations D0H D2H are not mapped Basic timer control register BTCON 211 D3H 0 0 0 0 0 0 0 0 System clock control register CLKCON 212 D4H 0 0 0 System flags register FLAGS 213 D5H x x x x x x 0 0 Register pointer 0 RP0 214 D6H 1 1 0 0 0 Register pointer 1 RP1 215 D7H 1 1 0 0 1 Stack pointer high byte SPH 216 D8H x x x x x x x x St...

Page 199: ... Control Register PWMCON 232 E8H 0 0 0 0 0 0 0 Locations E9H EEH are not mapped Port 1 Control Register High Byte P1CONH 240 EFH 0 0 0 0 0 0 Port 1 Control Register Low Byte P1CONL 241 F0H 0 0 0 0 0 0 0 0 Port 1 Pull up Resistor Enable Register P1PUR 242 F1H 1 1 1 0 0 0 0 Port 0 Control Register High Byte P0CONH 243 F2H 0 1 0 0 0 0 0 0 Port 0 Control Register Low Byte P0CONL 244 F3H 0 0 0 0 0 0 0 ...

Page 200: ...errupts with an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The external interrupts in the S3C80M4 F80M4 interrupt structure that can be used to release Stop mode are External interrupts P0 0 P0 3 INT0 INT3 Please note the following conditions fo...

Page 201: ...eral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slow clock fxx 16 because CLKCON 4 and CLKCON 3 are cleared to 00B If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idle mode the C...

Page 202: ...RESET and POWER DOWN S3C80M4 F80M4 8 6 NOTES ...

Page 203: ...gger input or push pull output mode selected by software software assignable pull ups P0 0 P0 3 can be used as inputs for external interrupts INT0 INT3 with interrupt enable and pending control Alternately P0 6 can be used as PWM 1 1 bit programmable I O port Input or push pull open drain output mode selected by software software assignable pull ups Alternately P1 0 P1 0 P1 6 can be used as T0OUT ...

Page 204: ...interrupt generation on falling rising signal edges Port 0 Interrupt Enable and Pending Registers P0INT To process external interrupts at the port 0 pins the additional control registers are provided the port 0 interrupt enable register P0INT F4H set 1 bank 0 and the port 0 interrupt pending register P0PND F5H set 1 bank 0 The port 0 interrupt pending register P0PND lets you check for interrupt pe...

Page 205: ... Alternative function PWM not used for P0 7 P0 5 P0 4 Output mode push pull Figure 9 1 Port 0 High Byte Control Register P0CONH Port 0 Control Register Low Byte P0CONL F3H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB P0 3 INT3 P0 2 INT2 P0 1 INT1 P0 0 INT0 P0CONL bit pair pin configuration settings 00 01 10 11 Schmitt trigger input mode Schmitt trigger input mode pull up Not available Output mode push...

Page 206: ... interrupt by rising edge 11 Enable interrupt by both falling and rising edge Figure 9 3 Port 0 Interrupt Control Register Port 0 Interrupt Pending Register P0PND F5H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB Not used for the S3C80M4 PND3 PND2 PND1 PND0 P0PND bit configuration settings 0 1 Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending Figure 9 4 Port 0...

Page 207: ...ters settings to select input or output mode push pull or open drain and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 1 control registers must also be enabled in the associated peripheral module Port 1 Pull up Resistor Enable Register P1PUR Using the port 1 pull up resistor enable register P1PUR...

Page 208: ...used for P1 3 P1 2 P1 1 P1 2 P1 1 T0CLK P1 0 T0OUT Output mode N channel open drain Input mode T0CLK Figure 9 6 Port 1 Low Byte Control Register P1CONL Port 1 Pull up Resistor Enable Register P1PUR F1H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB P1PUR bit configuration settings 0 1 Pull up Disable Not used for the S3C80M4 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 Pull up Enable Figure 9 7 Port 1 Pull up Res...

Page 209: ...er BTCON set 1 D3H read write BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in set 1 address D3H and is read write addressable using Register addressing mode A reset clears BTCON to 00H This enables the wa...

Page 210: ...ar bit 0 No effect 1 Clear dvider Basic timer counter clear bit 0 No effect 1 Clear BTCNT Basic timer input clock selection bits 00 fXX 4096 01 fXX 1024 10 fXX 128 11 fXX 16 Watchdog timer enable bits 1010B Disable watchdog function Other value Enable watchdog function Figure 10 1 Basic Timer Control Register BTCON ...

Page 211: ...BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval after a reset or when stop mode has been released by an external interrupt In stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT valu...

Page 212: ...abilization interval until bit 4 of the basic timer counter overflows MUX fXX 4096 DIV fXX 1024 fXX 128 fXX 16 fXX Bits 3 2 Bit 0 Basic Timer Control Register Write 1010xxxxB to Disable Clear Bit 1 RESET or STOP Data Bus 8 Bit Up Counter BTCNT Read Only Start the CPU NOTE OVF RESET R Figure 10 2 Basic Timer Block Diagram ...

Page 213: ...s assigned the separate vector address EEH The T0INT pending condition should be cleared by software when it has been serviced Even though T0INT is disabled the application s service routine can detect a pending condition of T0INT by the software and execute its sub routine When this case is used the T0INT pending bit must be cleared by application sub routine by writing a 0 to the T0CON 0 pending...

Page 214: ... pending condition when T0INT is disabled the application program polls pending bit T0CON 0 When a 1 is detected a timer 0 interrupt is pending When the interrupt request has been serviced the pending condition must be cleared by software by writing a 0 to the timer 0 interrupt pending bit T0CON 0 Timer 0 Control Register T0CON E6H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB Timer 0 match interrupt e...

Page 215: ... bit Comparator 8 bit Up Counter Read Only Clear Match T0CON 7 5 fXX 1024 fXX 64 fXX 8 T0CLK T0CON 3 M U X T0INT T0CON 1 T0OUT T0CON 0 Data Bus 8 Data Bus 8 fXX 256 fXX 1 Counter stop Counter clear signal T0CON 3 or Match signal IRQ0 R Pending T0CON 2 Figure 11 2 Timer 0 Functional Block Diagram ...

Page 216: ...8 BIT TIMER 0 S3C80M4 F80M4 11 4 NOTES ...

Page 217: ...oller has a 8 bit PWM The PWM have the following components Clock frequency dividers fOSC divider by 64 8 2 and 1 6 bit counter 6 bit comparators and data registers PWMDATA 8 bit counter overflow interrupt generations Selectors for data reload 6 and 8 bit overflow PWM control register PWMON set 1 bank 0 E8H read write ...

Page 218: ...a 1 is detected a PWM interrupt is pending When PWMINT sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the PWM interrupt pending bit PWMCON 0 PWM input clock selection bits 00 fosc 64 01 fosc 8 10 fosc 2 11 fosc 1 PWM Control Register PWMCON E8H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB PWMDATA reload interval Selection bit 0 Reload from 8 bit up co...

Page 219: ...Bit Counter 6 Bit Comparator 6 Bit Data Buffer 6 Bit Data Register 2 Bit Counter Extension Control Logic Extension Data Buffer PWM Extension Data Register Clear PWMCON 3 PWMCON 4 8 Data Bus PWMCON 7 6 From 8 Bit Up Counter 7 6 PWM P0 6 1 When REG Count 1 When REG Count PWMDATA 7 2 PWMDATA 1 0 8 Data Bus Figure 12 2 PWM Circuit Diagram ...

Page 220: ...8 BIT PULSE WIDTH MODULATION S3C80M4 F80M4 12 4 NOTES ...

Page 221: ...re presented in tables and graphs The information is arranged in the following order Absolute maximum ratings D C electrical characteristics Input output capacitance A C electrical characteristics Oscillation characteristics Oscillation stabilization time Data retention supply voltage in stop mode Operating voltage range ...

Page 222: ...al pin current for ports 100 Peak value Operating temperature TA 25 to 85 C Storage temperature TSTG 65 to 150 Table 13 2 D C Electrical Characteristics TA 25 C to 85 C VDD 2 4 V to 5 5V Parameter Symbol Conditions Min Typ Max Unit Operating voltage VDD fx 0 4 4 2 MHz 2 4 5 5 V fx 0 4 10 0 MHz 2 7 5 5 Input high voltage VIH1 All input pins except VIH2 VIH3 0 7VDD VDD VIH2 Ports0 Ports1 0 1 3 nRESE...

Page 223: ...tput ports except VOL1 2 0 Input high leakage current ILIH1 VIN VDD All input pins except ILIH2 3 µA ILIH2 VIN VDD XIN XOUT 20 Input low leakage current ILIL1 VIN 0 V All input pins except for nRESET ILIL2 3 ILIL2 VIN 0 V XIN XOUT 20 Output high leakage current ILOH VOUT VDD All output pins 3 Output low leakage current ILOL VOUT 0 V All output pins 3 Oscillator feed back resistors ROSC1 VDD 5 V TA...

Page 224: ...Hz 1 2 2 4 Idle mode Crystal oscillator C1 C2 22pF VDD 5 0V 10 4 0 MHz 1 0 2 0 IDD2 VDD 3 0V 10 4 0 MHz 0 5 1 0 Stop mode VDD 5V 10 TA 25 C 100 200 µA Supply current 1 IDD3 2 VDD 3V 10 TA 25 C 80 160 NOTES 1 Supply current does not include current drawn through internal pull up resistors and external output current loads 2 IDD3 is current when main clock oscillation stops 3 Every values in this ta...

Page 225: ...rameter Symbol Conditions Min Typ Max Unit Interrupt input high low width tINTH tINTL All interrupt VDD 3 0 V 500 700 ns nRESET input low width tRSL VDD 3 0 V 10 µs tINTH tINTL 0 8 VDD 0 2 VDD External Interrupt Figure 13 1 Input Timing for External Interrupts nRESET tRSL 0 2 VDD Figure 13 2 Input Timing for nRESET ...

Page 226: ...tion Supply Voltage in Stop Mode TA 25 C to 85 C VDD 2 4 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR 2 4 5 5 V Data retention supply current IDDDR VDDDR 2 4V Stop mode TA 25 C 1 uA Execution of STOP Instrction RESET Occurs VDDDR Stop Mode Oscillation Stabilization Time Normal Operating Mode Data Retention Mode tWAIT nRESET VDD NOTE tWAIT is the same ...

Page 227: ... Execution of STOP Instruction VDDDR Stop Mode Idle Mode Basic Timer Active Data Retention Mode tWAIT VDD Normal Operating Mode 0 8VDD NOTE tWAIT is the same as 16 x 1 BT clock Figure 13 4 Stop Mode Release Timing Initiated by Interrupt ...

Page 228: ...ition Min Typ Max Units 2 7 V 5 5 V 0 4 10 MHz Crystal XIN C1 XOUT C2 Main oscillation frequency 2 4 V 5 5 V 0 4 4 2 2 7 V 5 5 V 0 4 10 Ceramic Oscillator XIN C1 XOUT C2 Main oscillation frequency 2 4 V 5 5 V 0 4 4 2 2 7 V 5 5 V 0 4 10 External Clock XIN XOUT XIN input frequency 2 4 V 5 5 V 0 4 4 2 5 0 V 0 4 2 MHz RC Oscillator XIN XOUT R Frequency 3 0 V 0 4 1 ...

Page 229: ...l to the minimum oscillator voltage range 10 ms External clock XIN input high and low width tXH tXL 62 5 1250 ns XIN 1 fx 0 1V tXL tXH VDD 0 1V 0 1V Figure 13 5 Clock Timing Measurement at XIN 2 5 MHz Instruction Clock 6 25 kHz Main 2 4 5 Supply Voltage V Minimum instruction clock 1 4n x oscillator frequency n 1 2 8 16 5 5 1 05 MHz fx Main oscillation frequency 10 MHz 4 2 MHz 2 7 400 kHz Main 1 6 ...

Page 230: ...ELECTRICAL DATA S3C80M4 F80M4 13 10 NOTES ...

Page 231: ...ently available in 20 DIP 300A 20 SOP 375 and 16 DIP 300A 16 SOP 375 package NOTE Dimensions are in millimeters 26 80 MAX 26 40 0 20 1 77 20 DIP 300A 6 40 0 20 20 1 0 46 0 10 1 52 0 10 11 10 0 15 0 2 5 0 1 0 0 0 5 7 62 2 54 0 51 MIN 3 30 0 30 3 25 0 20 5 08 MAX Figure 14 1 20 DIP 300A Package Dimensions ...

Page 232: ...NOTE Dimensions are in millimeters 20 SOP 375 10 30 0 30 11 20 1 10 13 14 MAX 12 74 0 20 0 66 0 8 0 203 0 10 0 05 9 53 7 50 0 20 0 85 0 20 0 05 MIN 2 30 0 10 2 50 MAX 0 40 0 10 MAX 0 10 0 05 1 27 Figure 14 2 20 SOP 375 Package Dimensions ...

Page 233: ...AL DATA 14 3 NOTE Dimensions are in millimeters 19 80 MAX 19 40 0 20 0 81 6 40 0 20 16 1 16 DIP 300A 0 46 1 50 9 8 0 15 0 2 5 0 1 0 0 0 5 7 62 2 54 0 38 MIN 3 30 0 30 3 25 5 08 MAX Figure 14 3 16 DIP 300A Package Dimensions ...

Page 234: ... NOTE Dimensions are in millimeters 16 SOP 375 9 16 1 8 10 50 MAX 10 10 0 20 0 8 0 203 0 10 0 05 9 53 7 50 0 20 0 85 0 20 2 30 0 10 2 50 MAX 1 27 10 30 0 30 0 40 0 10 0 05 0 66 0 05 MIN 0 10 MAX Figure 14 4 16 SOP 375 Package Dimensions ...

Page 235: ...ion of the S3C80M4 microcontroller It has an on chip Flash MCU ROM instead of a masked ROM The Flash ROM is accessed by serial data format The S3F80M4 is fully compatible with the S3C80M4 both in function and in pin configuration Because of its simple programming requirements the S3F80M4 is ideal as an evaluation chip for the S3C80M4 ...

Page 236: ...0 T0OUT P1 1 T0CLK P1 2 P1 3 P1 4 P1 5 S3F80M4 20 DIP 300A 20 SOP 375 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 VDD VDD P0 0 INT0 SCLK P0 1 INT1 SDAT P0 2 INT2 P0 3 INT3 P0 4 P0 5 P0 6 PWM P0 7 P1 6 CLKOUT Figure 15 1 S3F80M4 Pin Assignments 20 DIP 300A 20 SOP 375 ...

Page 237: ...300A 16 SOP 375 VSS VSS XIN XIN XOUT VPP nRESET P1 0 T0OUT P1 1 T0CLK P1 2 P1 3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD VDD P0 0 INT0 SCLK P0 1 INT1 SDAT P0 2 INT2 P0 3 INT3 P0 4 P0 5 P0 6 PWM Figure 15 2 S3F80M4 Pin Assignments 16 DIP 300A 16 SOP 375 ...

Page 238: ...en 12 5 V is applied FLASH MCU is in writing mode and when 3 3 V is applied FLASH MCU is in reading mode Option VDD VSS VDD VSS 20 16 1 1 Power supply pin for logic circuit VDD should be tied to 3 3V during programming XIN XIN 2 2 I This pin should be connected to VSS in the tool program mode NOTE Parentheses indicate pin number for 16 DIP 300A 16 SOP 375 package Table 15 2 Comparison of S3F80M4 a...

Page 239: ... level 1 means High level Table 15 4 D C Electrical Characteristics TA 25 C to 85 C VDD 2 4 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit 10 MHz 4 0 8 0 Run mode Crystal oscillator C1 C2 22pF VDD 5 0V 10 4 0 MHz 2 0 4 0 IDD1 VDD 3 0V 10 4 0 MHz 1 5 3 0 10 MHz 1 2 2 4 Idle mode Crystal oscillator C1 C2 22pF VDD 5 0V 10 4 0 MHz 1 0 2 0 IDD2 VDD 3 0V 10 4 0 MHz 0 5 1 0 mA Stop mode VDD 5V 1...

Page 240: ...MHz Instruction Clock 6 25 kHz Main 2 4 5 Supply Voltage V Minimum instruction clock 1 4n x oscillator frequency n 1 2 8 16 5 5 1 05 MHz fx Main oscillation frequency 10 MHz 4 2 MHz 2 7 400 kHz Main 1 6 4 3 Figure 15 3 Operating Voltage Range ...

Page 241: ...le Microcontroller SAM Assembler SAMA is a universal assembler and generates object code in standard hexadecimal format Assembled program code includes the object code that is used for ROM data and required SMDS program control data To assemble programs SAMA requires a source file and an auxiliary definition DEF file with device specific information SASM88 The SASM88 is a relocatable assembler for...

Page 242: ...S2 RS 232C POD Probe Adapter PROM OTP Writer Unit RAM Break Display Unit Trace Timer Unit SAM8 Base Unit Power Supply Unit IBM PC AT or Compatible TB80M4 Target Board EVA Chip Target Application System Figure 16 1 SMDS Product Configuration SMDS2 ...

Page 243: ... 13 100 Pin Connector 25 1 J102 Device Selection SMDS2 SMDS2 Smart Option Source Idle Stop GND V CC 20 Pin Connector To User_VCC Off On RESET 7411 XI XTAL MDS JP5 Smart Option Selection ON SW1 B0 B1 B2 B3 B4 B5 B6 B7 B8 High Low External Internal JP1 S3C80M4 S3C84G5 JP2 128 QFP S3E84G0 EVA Chip 1 38 65 39 64 102 103 128 S3C84G5 24 SDIP S3C84G5 S3C80M4 20 DIP Figure 16 2 TB80M4 Target Board Configu...

Page 244: ...d evaluation chip The target system must have its own power supply NOTE The following symbol in the To User_Vcc Setting column indicates the electrical short off configuration Table 16 2 Main clock Selection Settings for TB80M4 Main Clock Settings Operating Mode Comments XIN XTAL MDS No Connection SMDS2 SMDS2 100 Pin Connector EVA Chip S3E84G0 XIN XOUT Set the XI switch to MDS when the target boar...

Page 245: ...N SAM8 In order to write data into program memory that is available in SMDS2 the target board should be selected to be for SMDS2 through a switch as follows Otherwise the program memory writing function is not available Table 16 4 The SMDS2 Tool Selection Setting SMDS2 Setting Operating Mode SMDS2 SMDS2 Target System R W R W SMDS2 IDLE LED The Yellow LED is ON when the evaluation chip S3E84G0 is i...

Page 246: ...al External Select Smart Option Source Target System TB80M4 Always must keep the External Internal External Select Smart Option Source Target System TB80M4 Do not setting on left figure Table 16 6 Smart Option Switch Setting for TB80M4 Smart Option Setting Comments Smart Option Low 0 High 1 B0 B1 B2 B3 B4 B5 B6 B7 B8 ON Always must keep all High 1 ...

Page 247: ... 2 3 4 5 6 7 8 9 1 0 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 20 Pin DIP Connector S3C80M4 20 DIP Figure 16 3 20 Pin Connectors J101 for TB80M4 Target Board Target System Target Cable for 16 20 Pin Connector Part Name AS40D A Order Code SM6306 1 20 10 11 J101 J101 1 20 10 11 16 20 P DIP Connector 16 20 P DIP Connector 8 9 8 9 1 16 1 16 Figure 16 4 S3E80M0 Cables for 16 20 DIP Package ...

Page 248: ...DEVELOPMENT TOOLS S3C80M4 F80M4 16 8 NOTES ...

Page 249: ...This datasheet has been downloaded from www DatasheetCatalog com Datasheets for electronic components ...

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