Samsung S3C80M4/F80M4, User Manual

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I/O PORTS S3C80M4/F80M4
9-2
PORT 0
Port 0 is an 8-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading
the port 0 data register, P0 at location E0H in set 1, bank 0. P0.0–P0.7 can serve inputs, as output push pull
or you can configure the following alternative functions:
— Low-byte pins (P0.0–P0.3): INT0–INT3
— High-byte pins (P0.4–P0.7): PWM
Port 0 Control Register (P0CONH, P0CONL)
Port 0 has two 8-bit control registers: P0CONH for P0.4-P0.7 and P0CONL for P0.0-P0.3. A reset clears the
P0CONH and P0CONL registers to "40H" and "00H", configuring all pins to input mode. In input mode, three
different selections are available:
— Schmitt trigger input with interrupt generation on falling signal edges.
— Schmitt trigger input with interrupt generation on rising signal edges.
— Schmitt trigger input with interrupt generation on falling/rising signal edges.
Port 0 Interrupt Enable and Pending Registers (P0INT)
To process external interrupts at the port 0 pins, the additional control registers are provided: the port 0 interrupt
enable register P0INT (F4H, set 1, bank 0) and the port 0 interrupt pending register P0PND (F5H, set 1, bank 0).
The port 0 interrupt pending register P0PND lets you check for interrupt pending conditions and clear the pending
condition when the interrupt service routine has been initiated. The application program detects interrupt requests
by polling the P0PND register at regular intervals.
When the interrupt enable bit of any port 0 pin is “1”, a rising or falling signal edge at that pin will generate an
interrupt request. The corresponding P0PND bit is then automatically set to “1” and the IRQ level goes low to
signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application
software must the clear the pending condition by writing a “0” to the corresponding P0PND bit.