8-6
R530/R730
8. Block Diagram and Schematic
- 이 문서는 삼성전자의 기술 자산으로 승인자만이 사용할 수 있습니다 -
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Confidential
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Confidential
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Confidential
CLK1_MCLK4/4#
CLK1_MCLK0/0#
CLK1_MCLK1/1#
SODIMM #0
SODIMM #1
333/400 MH
z
266 MH
z
CLK0_HCLK/CLK#
266 MH
z
10 MH
z
Page
8
MCH3_CLKREQ
#
CLK1_DREFSSCLK/DREFSSCLK
#
100 MHz (SRC 6)
1
SPI
KBC3_SPI_CLK
17.86 MHz
HPLL
xSLG8SP513r05)
100 MH
z
CLK1_DREFCLK/DREFCLK#
96 MH
z
CLK1_PCIEICH/PCIEICH
#
100 MHz (SRC 3)
CLK1_PCIELOM/PCIELOM#
100 MHz (SRC 9)
32.768 KH
z
PCI Express Gfx
100 MHz (SRC0)
OSC
HD Audi
o
WIRED LA
N
LOM3_CLKREQ*#
CLK3_USB48
48 MHz
CLK1_SATA/SATA
#
100 MHz (SRC 2)
CLOCK DISTRIBUTIO
N
667/800 MH
z
CLK1_MCLK3/3#
CLK3_PCLKICH
33 MHz
33 MHz
CLK3_PCLKMICO
M
BSE
L
14 MHz
OSC
Main PLL
SS
C
48MHz PL
L
CLK0_HCLK1/HCLK1#
CLK1_DREFSSCCLK/DREFSSCCLK#
#L
L
P
G3
H
C
M/
LL
P
G3
H
C
M_
1
KL
C
)4
C
R
S(
z
H
M
00
1
AUD3_BCLK
CP
U
MC
H
KBC
14.318 MH
z
CK-505M (w/ CLKREQ* & SSDC)
FS(2:0)
CPU_STP*
ITP_EN
SS(96/100) SE
L
PCI_STP
*
P3.3V
CLK3_PWRGD
*
100 MHz (SRC 6,9)
WLAN
CLK1_MINIPCIE/MINIPCIE#
RTC Cloc
k
25 MHz
333/400 MH
z
A
A
SAMSUN
G
2
OF
3
B
C
2
PCIE PLL
DPLLA
MPLL
DPLL
B
ICH9-M
USBPLL
SATAPLL
32.768 KH
z
PCIEPL
L
Cantiga
3
PART NO
.
PAGE
DAT
E
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHER
S
CHECK
B
LAST EDIT
RE
V
14.318 MHz
CHP3_SATACLKREQ#
Jun PARK
4
THIS DOCUMENT CONTAINS CONFIDENTIA
L
1
D
D
C
4
ELECTRONICS
1
PLL3
SS
C
33 MHz
Buffe
r
MUX
MUX
MUX
FSB
PE
G
DMI
DEV. STEP
SAMSUNG ELECTRONICS CO’S PROPERTY.
TITLE
MODULE CODE
EXCEPT AS AUTHORIZED BY SAMSUNG
.
APPROVAL
SAMSUNG PROPRIETAR
Y
PROPRIETARY INFORMATION THAT IS
DRA
W
MIN3_CLKREQ*#
333/400 MH
z
333/400 MH
z
D:/users/mobile24/mentor/Bremen-L/PV/Bremen-L_MAI
N
CLOCK DIAGRAM
MAI
N
Bremen-
L
59
6
BA41-xxxxxA
October 27, 2009 14:27:43 PM
1.0
PV
9/23/2008
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HJ.KIM
YM.AHN
