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Samsung MUXONENAND A-DIE KFN4G16Q2A Specification Download Page 169

MuxOneNAND2G(KFM2G16Q2A-DEBx)

- 169 -

FLASH MEMORY

MuxOneNAND4G(KFN4G16Q2A-DEBx)

7.1.3  Determining Rp Value (DDP, QDP only)  

For general operation, INT operates as normal output pin, so that tF is equivalent to tR (below 10ns). But since INT operates as open drain
with 50K ohm for Reset (Hot/Warm/NAND Flash Core) operations and ‘2X program operation(007Dh)’ case at DDP option, the pull-up resis-
tor value is related to tr(INT). And appropriate value can be obtained with the following reference charts.

NOTE 

: 

1) Refer to chapter 2.8.10 Start Address Register F101h DDP Block Diagram

Busy State

Ready   Vcc

VOH

tf

tr

VOL

Vss

~50k ohm

INT

1)

Vcc or Vccq

Rp

INT pol = ‘High’ 

(Default) 

 

 

tr

,t

f 

Ibus

y [mA

]

Rp(ohm)

Ibusy

tr[us]

KFN4G16Q2A @ Vcc = 1.8V,  Ta = 25

°

C , C

L

 = 30pF

1K

10K

20K

30K

0.1373

tf[ns]

1.046

1.658

2.062

2.717

2.676

2.674

2.673

1.78

0.18

0.09

40K

50K

2.349

2.565

2.673

2.672

0.045

0.06

0.036

Open(100K)

3.145

0.018

ª

ª

ª

ª

ª

ª

Summary of Contents for MUXONENAND A-DIE KFN4G16Q2A

Page 1: ...CUMENT IS PROVIDED ON AS AS IS BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND 1 For updates or additional information about Samsung products contact your nearest Samsung office 2 Samsung products are not intended for use in life support critical care medical safety equipment or similar applications where Product failure could result in loss of life or personal or physical harm or any military or ...

Page 2: ...t Write Operation revised 1 Chapter 2 8 21 Description of OTP Lock status and 1st block OTP Lock status revised 2 Chapter 3 6 Load Operation Flow Chart Diagram revised 3 Chapter 3 8 Cache Read Flow Chart revised 4 Chapter 3 9 5 Synchronous Burst Block Read Operation Flow Chart revised 5 Chapter 3 12 Copy Back Program Operation Flow Chart revised 6 Chapter 3 12 1 Copy Back Program Operation with Ra...

Page 3: ... DEBx Revision No History Draft Date Remark 1 3 1 Corrected errata 2 Chapter 2 8 18 Command Register F220h R W revised 3 Chapter 3 4 3 NAND Array Write Protection states revised 4 Chapter 3 4 3 3 Locked tight NAND Array Write Protection State revised Dec 16 2008 Final ...

Page 4: ... found in Section 8 0 1 1 Flash Product Type Selector Samsung offers a variety of Flash solutions including NAND Flash MuxOneNAND and NOR Flash Samsung offers Flash products both component and a variety of card formats including RS MMC MMC CompactFlash and SmartMedia To determine which Samsung Flash product solution is best for your application refer the product selector chart Density Part No VCC ...

Page 5: ...m time low power and high density and combines it with the syn chronous read performance of NOR The NOR Flash host interface makes MuxOneNAND an ideal solution for applications like G3 Smart Phones Camera Phones and mobile applications that have large advanced multimedia applications and operating systems but lack a NAND controller When integrated into a Samsung Multi Chip Package with Samsung Mob...

Page 6: ...ar Burst 4 8 16 32 1K words with no wrap Continuous 1K words 64 Page Sequential Burst Synchronous Write Up to 83MHz clock frequency Linear Burst 4 8 16 32 1K words with wrap around Continuous 1K words Sequential Burst Asynchronous Random Read 76ns access time Asynchronous Random Write Latency 3 4 Default 5 6 and 7 1 40Mhz Latency 3 available 1 66Mhz Latency 4 5 6 and 7 available Over 66Mhz Latency...

Page 7: ...ith minimum 4 clock 66MHz 6 clock 83MHz latency Below 40MHz it is accessible with minimum 3 clock latency Appropriate wait cycles are determined by programmable read latency MuxOneNAND provides for multiple sector read operations by assigning the number of sectors to be read in the sector counter register The device includes one block sized OTP One Time Programmable area and user controlled 1st bl...

Page 8: ...ured and locked with secured user information On chip controller interfaces enable the device to operate in systems without NAND Host controllers 2 2 Definitions B capital letter Byte 8bits W capital letter Word 16bits b lower case letter Bit ECC Error Correction Code Calculated ECC ECC that has been calculated during a load or program access Written ECC ECC that has been stored as data in the NAN...

Page 9: ...s Facing Down 63ball FBGA MuxOneNAND Chip 63ball 10mm x 13mm x max 1 0mmt 0 8mm ball pitch FBGA NC NC NC NC INT NC NC NC NC NC NC NC NC WE RP ADQ1 VSS VSS ADQ2 ADQ3 ADQ7 ADQ14 OE ADQ6 VCC ADQ8 ADQ11 ADQ4 ADQ5 ADQ12 VCC ADQ0 NC ADQ15 ADQ10 ADQ9 CE ADQ13 NC NC NC AVD NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Core IO CLK NC NC NC RDY ...

Page 10: ...own 63ball FBGA MuxOneNAND Chip 63ball 10mm x 13mm x max 1 2mmt 0 8mm ball pitch FBGA NC NC NC NC INT NC NC NC NC NC NC NC NC WE RP ADQ1 VSS VSS ADQ2 ADQ3 ADQ7 ADQ14 OE ADQ6 VCC ADQ8 ADQ11 ADQ4 ADQ5 ADQ12 VCC ADQ0 NC ADQ15 ADQ10 ADQ9 CE ADQ13 NC NC NC AVD NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Core IO CLK NC NC NC RDY ...

Page 11: ...onjunction with AVD low latches address input WE I Write Enable WE controls writes to the bufferRAM and registers Data is latched on the WE pulse s rising edge AVD I Address Valid Detect Indicates valid address presence on address inputs During asynchronous read operation all addresses are latched on AVD s rising edge and during synchronous read operation all addresses are latched on CLK s ris ing...

Page 12: ...rea is divided into Blocks of 64 Pages Within a Block each Page is 2KB and is com prised of 4 Sectors Within a Page each Sector is 512B and is comprised of 256 Words Spare Area The spare area is used for invalid block information and ECC storage Spare area internal memory is associated with corresponding main area memory Within a Block each Page has four 16B Sectors of spare area Each spare area S...

Page 13: ...ganization Area Block Page Sector Main 128KB 2KB 512B Spare 4KB 64B 16B 2KB Page0 512B 16B 64B Page0 2KB Page63 64B Page63 Sector Main Area Spare Area Block Page Main Area Spare Area 2KB 64B Main Area Spare Area 128KB 4KB Page 0 Page 63 512B Sector0 512B Sector1 512B Sector2 512B Sector3 16BSector0 16BSector1 16B Sector2 16BSector3 ...

Page 14: ...imul taneous Read While load and Write While program operations after Boot Up During Boot Up the BootRam is used by the host to initialize the main memory and deliver boot code from NAND Flash core to host The external memory is divided into a main area and a spare area Each buffer is the equivalent size of a Sector The main area data is 512B The spare area data is 16B External Memory Array Inform...

Page 15: ...D4G KFN4G16Q2A DEBx External Memory Array Organization BootRAM 0 BootRAM 1 BootRAM DataRAM 1_0 DataRAM 1_1 DataRAM 1_2 DataRAM 1_3 DataRAM1 Main area data Spare area data DataRAM 0_0 DataRAM 0_1 DataRAM 0_2 DataRAM 0_3 DataRAM0 Sector 512 16 Byte 512B 16B ...

Page 16: ...02Bh 0000h 00FFh 128KB Block12 000Ch 0000h 00FFh 128KB Block44 002Ch 0000h 00FFh 128KB Block13 000Dh 0000h 00FFh 128KB Block45 002Dh 0000h 00FFh 128KB Block14 000Eh 0000h 00FFh 128KB Block46 002Eh 0000h 00FFh 128KB Block15 000Fh 0000h 00FFh 128KB Block47 002Fh 0000h 00FFh 128KB Block16 0010h 0000h 00FFh 128KB Block48 0030h 0000h 00FFh 128KB Block17 0011h 0000h 00FFh 128KB Block49 0031h 0000h 00FFh...

Page 17: ...4Dh 0000h 00FFh 128KB Block109 006Dh 0000h 00FFh 128KB Block78 004Eh 0000h 00FFh 128KB Block110 006Eh 0000h 00FFh 128KB Block79 004Fh 0000h 00FFh 128KB Block111 006Fh 0000h 00FFh 128KB Block80 0050h 0000h 00FFh 128KB Block112 0070h 0000h 00FFh 128KB Block81 0051h 0000h 00FFh 128KB Block113 0071h 0000h 00FFh 128KB Block82 0052h 0000h 00FFh 128KB Block114 0072h 0000h 00FFh 128KB Block83 0053h 0000h ...

Page 18: ...8Dh 0000h 00FFh 128KB Block173 00ADh 0000h 00FFh 128KB Block142 008Eh 0000h 00FFh 128KB Block174 00AEh 0000h 00FFh 128KB Block143 008Fh 0000h 00FFh 128KB Block175 00AFh 0000h 00FFh 128KB Block144 0090h 0000h 00FFh 128KB Block176 00B0h 0000h 00FFh 128KB Block145 0091h 0000h 00FFh 128KB Block177 00B1h 0000h 00FFh 128KB Block146 0092h 0000h 00FFh 128KB Block178 00B2h 0000h 00FFh 128KB Block147 0093h ...

Page 19: ...CDh 0000h 00FFh 128KB Block237 00EDh 0000h 00FFh 128KB Block206 00CEh 0000h 00FFh 128KB Block238 00EEh 0000h 00FFh 128KB Block207 00CFh 0000h 00FFh 128KB Block239 00EFh 0000h 00FFh 128KB Block208 00D0h 0000h 00FFh 128KB Block240 00F0h 0000h 00FFh 128KB Block209 00D1h 0000h 00FFh 128KB Block241 00F1h 0000h 00FFh 128KB Block210 00D2h 0000h 00FFh 128KB Block242 00F2h 0000h 00FFh 128KB Block211 00D3h ...

Page 20: ...0Dh 0000h 00FFh 128KB Block301 012Dh 0000h 00FFh 128KB Block270 010Eh 0000h 00FFh 128KB Block302 012Eh 0000h 00FFh 128KB Block271 010Fh 0000h 00FFh 128KB Block303 012Fh 0000h 00FFh 128KB Block272 0110h 0000h 00FFh 128KB Block304 0130h 0000h 00FFh 128KB Block273 0111h 0000h 00FFh 128KB Block305 0131h 0000h 00FFh 128KB Block274 0112h 0000h 00FFh 128KB Block306 0132h 0000h 00FFh 128KB Block275 0113h ...

Page 21: ...4Dh 0000h 00FFh 128KB Block365 016Dh 0000h 00FFh 128KB Block334 014Eh 0000h 00FFh 128KB Block366 016Eh 0000h 00FFh 128KB Block335 014Fh 0000h 00FFh 128KB Block367 016Fh 0000h 00FFh 128KB Block336 0150h 0000h 00FFh 128KB Block368 0170h 0000h 00FFh 128KB Block337 0151h 0000h 00FFh 128KB Block369 0171h 0000h 00FFh 128KB Block338 0152h 0000h 00FFh 128KB Block370 0172h 0000h 00FFh 128KB Block339 0153h ...

Page 22: ...8Dh 0000h 00FFh 128KB Block429 01ADh 0000h 00FFh 128KB Block398 018Eh 0000h 00FFh 128KB Block430 01AEh 0000h 00FFh 128KB Block399 018Fh 0000h 00FFh 128KB Block431 01AFh 0000h 00FFh 128KB Block400 0190h 0000h 00FFh 128KB Block432 01B0h 0000h 00FFh 128KB Block401 0191h 0000h 00FFh 128KB Block433 01B1h 0000h 00FFh 128KB Block402 0192h 0000h 00FFh 128KB Block434 01B2h 0000h 00FFh 128KB Block403 0193h ...

Page 23: ...CDh 0000h 00FFh 128KB Block493 01EDh 0000h 00FFh 128KB Block462 01CEh 0000h 00FFh 128KB Block494 01EEh 0000h 00FFh 128KB Block463 01CFh 0000h 00FFh 128KB Block495 01EFh 0000h 00FFh 128KB Block464 01D0h 0000h 00FFh 128KB Block496 01F0h 0000h 00FFh 128KB Block465 01D1h 0000h 00FFh 128KB Block497 01F1h 0000h 00FFh 128KB Block466 01D2h 0000h 00FFh 128KB Block498 01F2h 0000h 00FFh 128KB Block467 01D3h ...

Page 24: ...0Dh 0000h 00FFh 128KB Block557 022Dh 0000h 00FFh 128KB Block526 020Eh 0000h 00FFh 128KB Block558 022Eh 0000h 00FFh 128KB Block527 020Fh 0000h 00FFh 128KB Block559 022Fh 0000h 00FFh 128KB Block528 0210h 0000h 00FFh 128KB Block560 0230h 0000h 00FFh 128KB Block529 0211h 0000h 00FFh 128KB Block561 0231h 0000h 00FFh 128KB Block530 0212h 0000h 00FFh 128KB Block562 0232h 0000h 00FFh 128KB Block531 0213h ...

Page 25: ...4Dh 0000h 00FFh 128KB Block621 026Dh 0000h 00FFh 128KB Block590 024Eh 0000h 00FFh 128KB Block622 026Eh 0000h 00FFh 128KB Block591 024Fh 0000h 00FFh 128KB Block623 026Fh 0000h 00FFh 128KB Block592 0250h 0000h 00FFh 128KB Block624 0270h 0000h 00FFh 128KB Block593 0251h 0000h 00FFh 128KB Block625 0271h 0000h 00FFh 128KB Block594 0252h 0000h 00FFh 128KB Block626 0272h 0000h 00FFh 128KB Block595 0253h ...

Page 26: ...8Dh 0000h 00FFh 128KB Block685 02ADh 0000h 00FFh 128KB Block654 028Eh 0000h 00FFh 128KB Block686 02AEh 0000h 00FFh 128KB Block655 028Fh 0000h 00FFh 128KB Block687 02AFh 0000h 00FFh 128KB Block656 0290h 0000h 00FFh 128KB Block688 02B0h 0000h 00FFh 128KB Block657 0291h 0000h 00FFh 128KB Block689 02B1h 0000h 00FFh 128KB Block658 0292h 0000h 00FFh 128KB Block690 02B2h 0000h 00FFh 128KB Block659 0293h ...

Page 27: ...CDh 0000h 00FFh 128KB Block749 02EDh 0000h 00FFh 128KB Block718 02CEh 0000h 00FFh 128KB Block750 02EEh 0000h 00FFh 128KB Block719 02CFh 0000h 00FFh 128KB Block751 02EFh 0000h 00FFh 128KB Block720 02D0h 0000h 00FFh 128KB Block752 02F0h 0000h 00FFh 128KB Block721 02D1h 0000h 00FFh 128KB Block753 02F1h 0000h 00FFh 128KB Block722 02D2h 0000h 00FFh 128KB Block754 02F2h 0000h 00FFh 128KB Block723 02D3h ...

Page 28: ...0Dh 0000h 00FFh 128KB Block813 032Dh 0000h 00FFh 128KB Block782 030Eh 0000h 00FFh 128KB Block814 032Eh 0000h 00FFh 128KB Block783 030Fh 0000h 00FFh 128KB Block815 032Fh 0000h 00FFh 128KB Block784 0310h 0000h 00FFh 128KB Block816 0330h 0000h 00FFh 128KB Block785 0311h 0000h 00FFh 128KB Block817 0331h 0000h 00FFh 128KB Block786 0312h 0000h 00FFh 128KB Block818 0332h 0000h 00FFh 128KB Block787 0313h ...

Page 29: ...4Dh 0000h 00FFh 128KB Block877 036Dh 0000h 00FFh 128KB Block846 034Eh 0000h 00FFh 128KB Block878 036Eh 0000h 00FFh 128KB Block847 034Fh 0000h 00FFh 128KB Block879 036Fh 0000h 00FFh 128KB Block848 0350h 0000h 00FFh 128KB Block880 0370h 0000h 00FFh 128KB Block849 0351h 0000h 00FFh 128KB Block881 0371h 0000h 00FFh 128KB Block850 0352h 0000h 00FFh 128KB Block882 0372h 0000h 00FFh 128KB Block851 0353h ...

Page 30: ...8Dh 0000h 00FFh 128KB Block941 03ADh 0000h 00FFh 128KB Block910 038Eh 0000h 00FFh 128KB Block942 03AEh 0000h 00FFh 128KB Block911 038Fh 0000h 00FFh 128KB Block943 03AFh 0000h 00FFh 128KB Block912 0390h 0000h 00FFh 128KB Block944 03B0h 0000h 00FFh 128KB Block913 0391h 0000h 00FFh 128KB Block945 03B1h 0000h 00FFh 128KB Block914 0392h 0000h 00FFh 128KB Block946 03B2h 0000h 00FFh 128KB Block915 0393h ...

Page 31: ...0h 00FFh 128KB Block1005 03EDh 0000h 00FFh 128KB Block974 03CEh 0000h 00FFh 128KB Block1006 03EEh 0000h 00FFh 128KB Block975 03CFh 0000h 00FFh 128KB Block1007 03EFh 0000h 00FFh 128KB Block976 03D0h 0000h 00FFh 128KB Block1008 03F0h 0000h 00FFh 128KB Block977 03D1h 0000h 00FFh 128KB Block1009 03F1h 0000h 00FFh 128KB Block978 03D2h 0000h 00FFh 128KB Block1010 03F2h 0000h 00FFh 128KB Block979 03D3h 0...

Page 32: ...000h 00FFh 128KB Block1069 042Dh 0000h 00FFh 128KB Block1038 040Eh 0000h 00FFh 128KB Block1070 042Eh 0000h 00FFh 128KB Block1039 040Fh 0000h 00FFh 128KB Block1071 042Fh 0000h 00FFh 128KB Block1040 0410h 0000h 00FFh 128KB Block1072 0430h 0000h 00FFh 128KB Block1041 0411h 0000h 00FFh 128KB Block1073 0431h 0000h 00FFh 128KB Block1042 0412h 0000h 00FFh 128KB Block1074 0432h 0000h 00FFh 128KB Block1043...

Page 33: ...000h 00FFh 128KB Block1133 046Dh 0000h 00FFh 128KB Block1102 044Eh 0000h 00FFh 128KB Block1134 046Eh 0000h 00FFh 128KB Block1103 044Fh 0000h 00FFh 128KB Block1135 046Fh 0000h 00FFh 128KB Block1104 0450h 0000h 00FFh 128KB Block1136 0470h 0000h 00FFh 128KB Block1105 0451h 0000h 00FFh 128KB Block1137 0471h 0000h 00FFh 128KB Block1106 0452h 0000h 00FFh 128KB Block1138 0472h 0000h 00FFh 128KB Block1107...

Page 34: ...000h 00FFh 128KB Block1197 04ADh 0000h 00FFh 128KB Block1166 048Eh 0000h 00FFh 128KB Block1198 04AEh 0000h 00FFh 128KB Block1167 048Fh 0000h 00FFh 128KB Block1199 04AFh 0000h 00FFh 128KB Block1168 0490h 0000h 00FFh 128KB Block1200 04B0h 0000h 00FFh 128KB Block1169 0491h 0000h 00FFh 128KB Block1201 04B1h 0000h 00FFh 128KB Block1170 0492h 0000h 00FFh 128KB Block1202 04B2h 0000h 00FFh 128KB Block1171...

Page 35: ...000h 00FFh 128KB Block1261 04EDh 0000h 00FFh 128KB Block1230 04CEh 0000h 00FFh 128KB Block1262 04EEh 0000h 00FFh 128KB Block1231 04CFh 0000h 00FFh 128KB Block1263 04EFh 0000h 00FFh 128KB Block1232 04D0h 0000h 00FFh 128KB Block1264 04F0h 0000h 00FFh 128KB Block1233 04D1h 0000h 00FFh 128KB Block1265 04F1h 0000h 00FFh 128KB Block1234 04D2h 0000h 00FFh 128KB Block1266 04F2h 0000h 00FFh 128KB Block1235...

Page 36: ...000h 00FFh 128KB Block1325 052Dh 0000h 00FFh 128KB Block1294 050Eh 0000h 00FFh 128KB Block1326 052Eh 0000h 00FFh 128KB Block1295 050Fh 0000h 00FFh 128KB Block1327 052Fh 0000h 00FFh 128KB Block1296 0510h 0000h 00FFh 128KB Block1328 0530h 0000h 00FFh 128KB Block1297 0511h 0000h 00FFh 128KB Block1329 0531h 0000h 00FFh 128KB Block1298 0512h 0000h 00FFh 128KB Block1330 0532h 0000h 00FFh 128KB Block1299...

Page 37: ...000h 00FFh 128KB Block1389 056Dh 0000h 00FFh 128KB Block1358 054Eh 0000h 00FFh 128KB Block1390 056Eh 0000h 00FFh 128KB Block1359 054Fh 0000h 00FFh 128KB Block1391 056Fh 0000h 00FFh 128KB Block1360 0550h 0000h 00FFh 128KB Block1392 0570h 0000h 00FFh 128KB Block1361 0551h 0000h 00FFh 128KB Block1393 0571h 0000h 00FFh 128KB Block1362 0552h 0000h 00FFh 128KB Block1394 0572h 0000h 00FFh 128KB Block1363...

Page 38: ...000h 00FFh 128KB Block1453 05ADh 0000h 00FFh 128KB Block1422 058Eh 0000h 00FFh 128KB Block1454 05AEh 0000h 00FFh 128KB Block1423 058Fh 0000h 00FFh 128KB Block1455 05AFh 0000h 00FFh 128KB Block1424 0590h 0000h 00FFh 128KB Block1456 05B0h 0000h 00FFh 128KB Block1425 0591h 0000h 00FFh 128KB Block1457 05B1h 0000h 00FFh 128KB Block1426 0592h 0000h 00FFh 128KB Block1458 05B2h 0000h 00FFh 128KB Block1427...

Page 39: ...000h 00FFh 128KB Block1517 05EDh 0000h 00FFh 128KB Block1486 05CEh 0000h 00FFh 128KB Block1518 05EEh 0000h 00FFh 128KB Block1487 05CFh 0000h 00FFh 128KB Block1519 05EFh 0000h 00FFh 128KB Block1488 05D0h 0000h 00FFh 128KB Block1520 05F0h 0000h 00FFh 128KB Block1489 05D1h 0000h 00FFh 128KB Block1521 05F1h 0000h 00FFh 128KB Block1490 05D2h 0000h 00FFh 128KB Block1522 05F2h 0000h 00FFh 128KB Block1491...

Page 40: ...000h 00FFh 128KB Block1581 062Dh 0000h 00FFh 128KB Block1550 060Eh 0000h 00FFh 128KB Block1582 062Eh 0000h 00FFh 128KB Block1551 060Fh 0000h 00FFh 128KB Block1583 062Fh 0000h 00FFh 128KB Block1552 0610h 0000h 00FFh 128KB Block1584 0630h 0000h 00FFh 128KB Block1553 0611h 0000h 00FFh 128KB Block1585 0631h 0000h 00FFh 128KB Block1554 0612h 0000h 00FFh 128KB Block1586 0632h 0000h 00FFh 128KB Block1555...

Page 41: ...000h 00FFh 128KB Block1645 066Dh 0000h 00FFh 128KB Block1614 064Eh 0000h 00FFh 128KB Block1646 066Eh 0000h 00FFh 128KB Block1615 064Fh 0000h 00FFh 128KB Block1647 066Fh 0000h 00FFh 128KB Block1616 0650h 0000h 00FFh 128KB Block1648 0670h 0000h 00FFh 128KB Block1617 0651h 0000h 00FFh 128KB Block1649 0671h 0000h 00FFh 128KB Block1618 0652h 0000h 00FFh 128KB Block1650 0672h 0000h 00FFh 128KB Block1619...

Page 42: ...000h 00FFh 128KB Block1709 06ADh 0000h 00FFh 128KB Block1678 068Eh 0000h 00FFh 128KB Block1710 06AEh 0000h 00FFh 128KB Block1679 068Fh 0000h 00FFh 128KB Block1711 06AFh 0000h 00FFh 128KB Block1680 0690h 0000h 00FFh 128KB Block1712 06B0h 0000h 00FFh 128KB Block1681 0691h 0000h 00FFh 128KB Block1713 06B1h 0000h 00FFh 128KB Block1682 0692h 0000h 00FFh 128KB Block1714 06B2h 0000h 00FFh 128KB Block1683...

Page 43: ...000h 00FFh 128KB Block1773 06EDh 0000h 00FFh 128KB Block1742 06CEh 0000h 00FFh 128KB Block1774 06EEh 0000h 00FFh 128KB Block1743 06CFh 0000h 00FFh 128KB Block1775 06EFh 0000h 00FFh 128KB Block1744 06D0h 0000h 00FFh 128KB Block1776 06F0h 0000h 00FFh 128KB Block1745 06D1h 0000h 00FFh 128KB Block1777 06F1h 0000h 00FFh 128KB Block1746 06D2h 0000h 00FFh 128KB Block1778 06F2h 0000h 00FFh 128KB Block1747...

Page 44: ...000h 00FFh 128KB Block1837 072Dh 0000h 00FFh 128KB Block1806 070Eh 0000h 00FFh 128KB Block1838 072Eh 0000h 00FFh 128KB Block1807 070Fh 0000h 00FFh 128KB Block1839 072Fh 0000h 00FFh 128KB Block1808 0710h 0000h 00FFh 128KB Block1840 0730h 0000h 00FFh 128KB Block1809 0711h 0000h 00FFh 128KB Block1841 0731h 0000h 00FFh 128KB Block1810 0712h 0000h 00FFh 128KB Block1842 0732h 0000h 00FFh 128KB Block1811...

Page 45: ...000h 00FFh 128KB Block1901 076Dh 0000h 00FFh 128KB Block1870 074Eh 0000h 00FFh 128KB Block1902 076Eh 0000h 00FFh 128KB Block1871 074Fh 0000h 00FFh 128KB Block1903 076Fh 0000h 00FFh 128KB Block1872 0750h 0000h 00FFh 128KB Block1904 0770h 0000h 00FFh 128KB Block1873 0751h 0000h 00FFh 128KB Block1905 0771h 0000h 00FFh 128KB Block1874 0752h 0000h 00FFh 128KB Block1906 0772h 0000h 00FFh 128KB Block1875...

Page 46: ...000h 00FFh 128KB Block1965 07ADh 0000h 00FFh 128KB Block1934 078Eh 0000h 00FFh 128KB Block1966 07AEh 0000h 00FFh 128KB Block1935 078Fh 0000h 00FFh 128KB Block1967 07AFh 0000h 00FFh 128KB Block1936 0790h 0000h 00FFh 128KB Block1968 07B0h 0000h 00FFh 128KB Block1937 0791h 0000h 00FFh 128KB Block1969 07B1h 0000h 00FFh 128KB Block1938 0792h 0000h 00FFh 128KB Block1970 07B2h 0000h 00FFh 128KB Block1939...

Page 47: ...0000h 00FFh 128KB Block2029 07EDh 0000h 00FFh 128KB Block1998 07CEh 0000h 00FFh 128KB Block2030 07EEh 0000h 00FFh 128KB Block1999 07CFh 0000h 00FFh 128KB Block2031 07EFh 0000h 00FFh 128KB Block2000 07D0h 0000h 00FFh 128KB Block2032 07F0h 0000h 00FFh 128KB Block2001 07D1h 0000h 00FFh 128KB Block2033 07F1h 0000h 00FFh 128KB Block2002 07D2h 0000h 00FFh 128KB Block2034 07F2h 0000h 00FFh 128KB Block200...

Page 48: ...r Number data MSB 3 LSB MSB 3 Reserved for future use 4 LSB MSB 5 LSB Dedicated to internal ECC logic Read Only Note 5 ECCm 1st for main area data MSB Dedicated to internal ECC logic Read Only Note 5 ECCm 2nd for main area data 6 LSB Dedicated to internal ECC logic Read Only Note 5 ECCm 3rd for main area data MSB Dedicated to internal ECC logic Read Only Note 5 ECCs 1st for 2nd word of spare area ...

Page 49: ...RAM Main page1 sector2 0900h 09FFh 01200h 013FEh 512B DataM 1_3 DataRAM Main page1 sector3 0A00h 7FFFh 01400h 0FFFEh 59K 59K Reserved Reserved Spare area 8KB 8000h 8007h 10000h 1000Eh 16B 32B R BootS 0 BootRAM Spare sector0 8008h 800Fh 10010h 1001Eh 16B BootS 1 BootRAM Spare sector1 8010h 8017h 10020h 1002Eh 16B 128B R W DataS 0_0 DataRAM Spare page0 sector0 8018h 801Fh 10030h 1003Eh 16B DataS 0_1...

Page 50: ... 0 0200h 02FFh 512B DataM 0_0 sector 0 of page 0 0300h 03FFh 512B DataM 0_1 sector 1 of page 0 0400h 04FFh 512B DataM 0_2 sector 2 of page 0 0500h 05FFh 512B DataM 0_3 sector 3 of page 0 0600h 06FFh 512B DataM 1_0 sector 0 of page 1 0700h 07FFh 512B DataM 1_1 sector 1 of page 1 0800h 08FFh 512B DataM 1_2 sector 2 of page 1 0900h 09FFh 512B DataM 1_3 sector 3 of page 1 8000h 8007h 16B BootS 0 secto...

Page 51: ...data 1st 800Dh 1001Ah ECC Code for Spare area data 1st ECC Code for Main area data 3rd 800Eh 1001Ch FFh Reserved for the future use ECC Code for Spare area data 2nd 800Fh 1001Eh Free Usage DataS 0_0 8010h 10020h BI 8011h 10022h Managed by Internal ECC logic 8012h 10024h Reserved for the future use Managed by Internal ECC logic 8013h 10026h Reserved for the current and future use 8014h 10028h ECC C...

Page 52: ...2h 10064h Reserved for the future use Managed by Internal ECC logic 8033h 10066h Reserved for the current and future use 8034h 10068h ECC Code for Main area data 2nd ECC Code for Main area data 1st 8035h 1006Ah ECC Code for Spare area data 1st ECC Code for Main area data 3rd 8036h 1006Ch Reserved for the future use ECC Code for Spare area data 2nd 8037h 1006Eh Free Usage DataS 1_1 8038h 10070h BI ...

Page 53: ...ng load operation When loading programming spare area spare area BufferRAM address BSA and BufferRAM sector count BSC is chosen via Start buffer register as it is Buf Word Address Byte Address F E D C B A 9 8 7 6 5 4 3 2 1 0 DataS 1_3 8048h 10090h BI 8049h 10092h Managed by Internal ECC logic 804Ah 10094h Reserved for the future use Managed by Internal ECC logic 804Bh 10096h Reserved for the curre...

Page 54: ...nation Page Sector address for Copy back program F104h 1E208h Start address 5 R W Number of Page in Synchronous Burst Block Read F105h 1E20Ah Start address 6 N A F106h 1E20Ch Start address 7 N A F107h 1E20Eh Start address 8 R W NAND Flash Page Sector address F108h F1FFh 1E210h 1E3FEh Reserved Reserved for user F200h 1E400h Start Buffer R W Buffer Number for the page data transfer to from the mem o...

Page 55: ... Result of spare area data R ECC error position of Spare area data error for first selected Sector FF03h 1FE06h ECC Result of main area data R ECC error position of Main area data error for second selected Sector FF04h 1FE08h ECC Result of spare area data R ECC error position of Spare area data error for second selected Sector FF05h 1FE0Ah ECC Result of main area data R ECC error position of Main ...

Page 56: ...n Device ID Default 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DeviceID Device Identification Description DeviceID 1 0 Vcc 00 1 8V 01 10 11 reserved DeviceID 2 Muxed Demuxed 0 Muxed 1 Demuxed DeviceID 3 Single DDP 0 Single 1 DDP DeviceID 7 4 Density 0000 128Mb 0001 256Mb 0010 512Mb 0011 1Gb 0100 2Gb 0101 4Gb DeviceID 8 Bottom Boot 0 Bottom Boot Device DeviceID 15 0 KFM2G16Q2A 0040h KFN4G16Q2A 0058h ...

Page 57: ... is reserved for internal use 2 8 5 Data Buffer Size Register F003h R F003h default 0800h Data Buffer Size Information 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DataBufSize Register Information Description DataBufSize Total data buffer size in Words equal to 2 buffers of 1024 Words each 2 x 1024 211 in the memory interface ...

Page 58: ...ibes the internal NAND array technology F006h default 0000h Technology Information 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BootBufSize Register Information Description BootBufSize Total boot buffer size in Words equal to 1 buffer of 512 Words 1 x 512 29 in the memory interface 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DataBufAmount BootBufAmount Register Information Description DataBufAmount The number ...

Page 59: ...er of chip1 chip2 follows the DBS setting In using DDP chip BootRAM of Chip 1 will always be selected regardless of DBS Reading and Writing on the DataRAM of DDP chip is different Only the DataRAM selected by DBS will be written and read out 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DFS Reserved 0000 FBA1 Device Number of Block FBA 2Gb 2048 FBA 10 0 4Gb DDP 4096 DFS 15 FBA 10 0 Register Information De...

Page 60: ...ing Also this register describes the first page and sector address to be loaded in Cache Read Operation F103h default 0000h NOTE 1 In case of Cache Read Operation FCSA has to be set to 00 Start Address4 Information 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 00000 FCBA Device Number of Block FBA 2Gb 2048 FCBA 10 0 Register Information Description FCBA NAND Flash Copy Back Block Address Block Ad...

Page 61: ...s in a block for a page load copy back program or program operation and the NAND Flash start sector address in a page for a load copy back program or program operation F107h default 0000h NOTE 1 In case of 2X Cache Program the host programs data on same FPA of different Planes 2 In case of Synchronous Burst Block Read Cache Read Operation 2X Program and 2X Cache Program FSA has to be set to 00 Sta...

Page 62: ... Cache Read BSA has to be set to 1000 or 1100 And BSC has to be set to 00 In case of Synchronous Burst Block Read BSA has to be set to 1000 And BSC has to be set to 00 In case of 2X Program or 2X Cache Program BSA has to be set to 1000 And BSC has to be set to 00 Start Address8 Information 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 0000 BSA Reserved 000000 BSC Item Description BSA 3 Selection ...

Page 63: ... and must be ended by 007D for the last page program of cache program Refer to 6 13 and 6 14 3 If any blocks are changed to locked tight state the all block unlock command will fail In order to use all block unlock command again a cold reset is needed 4 Reset MuxOneNAND Hot reset command makes the registers and NAND Flash core into default state 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Command CMD Op...

Page 64: ... operation will make INT pin turn low 1 2 Write command into Command Register This will make the device to perform the designated operation 3 INT pin will turn back to high once the operation is completed 1 NOTE 1 INT pin polarity is based on IOBE 1 and INT pol 1 default setting Method 2 Write command into Command Register at INT ready state Auto INT Mode 1 Write command into Command Register This...

Page 65: ...while HF is 0 Burst Read Write Latency BRWL Information 14 12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W R R W R W R RM BRWL BL ECC RDY pol INT pol IOBE RDY Conf Reserv ed HF WM BWPS RM Read Mode 0 Asynchronous read default 1 Synchronous read Item Definition Description RM Read Mode Selects between asynchronous read mode and synchronous read mode BRWL Latency Cycles Read...

Page 66: ...or Correction Code ECC Information 8 RDY Polarity RDYpol Information 7 INT Polarity INTpol Information 6 BL Burst Length Main Burst Length Spare 000 Continuous default 001 4 words 010 8 words 011 16 words 100 32 words N A 101 1K words Block Read Only N A 110 111 Reserved Item Definition Description BL Burst Length Specifies the size of the burst length during a synchronous linear burst read and wr...

Page 67: ...ation1 Register I O Buffer Enable Information 5 RDY Configuration RDY conf RDY Configuration Information 4 HF Enable HF HF Information 2 Item Definition Description IOBE I O Buffer Enable for INT and RDY signals 0 disable default 1 enable Item Definition Description RDY conf RDY configuration 0 active with valid data default 1 active one clock before valid data HF Description 0 HF Disable default ...

Page 68: ... Status BWPS Boot Buffer Write Protect Status Information 0 WM Write Mode 0 Asynchronous Write default 1 Synchronous Write Item Definition Description WM Write Mode Selects between asynchronous Write Mode and synchronous Write Mode RM WM Mode Description 0 0 Asynch Read Asynch Write Default 1 0 Sync Read Asynch Write 1 1 Sync Read Synch Write Other Case Reserved 1 Item Definition Description BWPS ...

Page 69: ...5 Lock This bit shows whether the host is loading data from the NAND Flash array into the locked BootRAM or whether the host is performing a pro gram erase of a locked block of the NAND Flash array Lock Information 14 Load This bit shows the Load Operation status Load Information 13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OnGo Lock Load Prog Erase Error Sus Reserved RSTB OTPL OTPBL Plane1 Previous P...

Page 70: ...t will stay as Fail status until the end of 2X Cache Program In case of 2X Program Error bit will indicate the 2X Program fail regardless of Plane1 or Plane2 Error Information 10 Erase Suspend Sus This bit shows the Erase Suspend status Sus Information 9 Item Definition Description Prog Program Operation status 0 ready default 1 busy or error see controller status output modes Item Definition Desc...

Page 71: ...ing of data stored in the 1st block The OTPBL status bit is automatically updated at power on and it must be referred only on Chip1 within DDP OTP Lock Information 5 Plane1 Previous This bit shows the previous program status of Plane1 at 2X Cache Program This value is invalid only at the first Read Controller Status Reg ister step of 2X Cache Program and 2X Interleave Cache Program operation Refer...

Page 72: ...ache Program operation Refer to 6 14 and 6 15 Plane2 Previous Information 2 Plane2 Current This bit shows the current program status of Plane2 at Final 2X Cache Program 2X Program and 2X Interleave Cache Program During 2X Cache Program prior to 2X Program command which will be Final 2X Cache Program this bit will be invalid fixed to 0 Plane2 Current Information 1 Time Out TO This bit determines if...

Page 73: ... 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 Program OK 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 Erase OK 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 Erase Verify Read OK3 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 Load Fail1 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 0 Program Fail 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 Erase Fail 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 Cache Read Fail 1 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 0 Erase Verify Read Fail3 0 0 0 0 1 1 0 ...

Page 74: ...de Controller Status Register 15 0 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 OnGo Lock Load Prog Erase Error Sus RSTB OTPL note1 OTPBL note2 Plane1 Previous Plane1 Current Plane2 Previous Plane2 Current TO Program Fail on 2X Program Plane1 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 Program Fail on 2X Program Plane2 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 Program Fail on 2X Program Plane1 Plane2 0 0 0 1 0 1 0 0 0 1 0 1...

Page 75: ...11 10 9 8 7 6 5 4 3 2 1 0 INT Reserved 0000000 RI WI EI RSTI Reserved 0000 Status Conditions Default State Valid State Interrupt Function Cold Warm hot 1 1 0 off sets itself to 1 One or more of RI WI RSTI and EI is set to 1 or 0065h 0023h 0071h 002Ah 0027h and 002Ch commands are completed 0 1 Pending clears to 0 0 is written to this bit Cold Warm Hot reset is being performed or command is written ...

Page 76: ... reset is being performed or com mand is written to Command Register in INT auto mode 1 0 off Status Conditions Default State Valid State Interrupt Function Cold Warm hot 0 0 0 off sets itself to 1 At the completion of an Erase Operation 0094h 0095h 0030h 0 1 Pending clears to 0 0 is written to this bit Cold Warm Hot reset is being performed or com mand is written to Command Register in INT auto m...

Page 77: ... the NAND Flash memory array To read the write protection status FBA DFS and DBS also in case of DDP has to be set before reading the register F24Eh default 0002h Write Protection Status Information 2 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 000000 SBA Device Number of Block SBA 2Gb 2048 10 0 Item Definition Description SBA Start Block Address Precedes Lock Block Unlock Block or Lock Tight...

Page 78: ...RAM Status of errors in the 2nd selected sector of the main BufferRAM as a result of an ECC check during a load operation Also updated during a Bootload operation ERm2 3rd selected sector of the main BufferRAM Status of errors in the 3rd selected sector of the main BufferRAM as a result of an ECC check during a load operation Also updated during a Bootload operation ERm3 4th selected sector of the...

Page 79: ...of 2nd Selected Sector Main Area Data Register FF03h R This Read register shows the Error Correction result for the 2nd selected sector of the main area data ECCposWord1 is the error position address in the Main Area data of 256 words ECCposIO1 is the error position address which selects 1 of 16 DQs ECCposWord1 and ECCposIO1 are also updated at boot loading FF03h default 0000h 2 8 30 ECC Result of...

Page 80: ...of 4th Selected Sector Main Area Data Register FF07h R This Read register shows the Error Correction result for the 4th selected sector of the main area data ECCposWord3 is the error position address in the Main Area data of 256 words ECCposIO3 is the error position address which selects 1 of 16 DQs ECCposWord3 and ECCposIO3 are also updated at boot loading FF07h default 0000h 2 8 34 ECC Result of...

Page 81: ...16Q2A DEBx ECC Log Sector ECClogSector0 ECClogSector3 indicates the error position in the 2nd word and LSB of 3rd word in the spare area Refer to note 2 in chapter 2 7 2 ECClogSector Information 5 4 ECClogSector Error Position 00 2nd word 01 3rd word 10 11 Reserved ...

Page 82: ...including address and data to the boot partition or writing an improper command will terminate the previous com mand sequence and make the device enter the ready status The defined valid command sequences are stated in Command Sequences Table Command based operations are mainly used when MuxOneNAND is used as Booting device and all command based operations only sup ports asynchronous reads and wri...

Page 83: ...d will sequentially load data in next page to DataRAM0 This page address increment is restricted within a block The default value of FBA and FPA is 0 Therefore initial issue of this command after power on will load the first page of memory which is usu ally boot code 3 1 3 Read Identification Data Command The Read Identification Data command consists of two cycles It gives out the devices identifi...

Page 84: ...ous Read L L H Add In Data Out H L Start Initial Burst Read L H H Add In H Burst Read L L H Burst Data Out H Terminate Burst Read Cycle H X H High Z H X X Terminate Burst Read Cycle via RP X X X High Z L X X Terminate Current Burst Read Cycle and Start New Burst Read Cycle L H H Add In H Start Initial Burst Write L H L Add In H Burst Write L H X Data In H H Terminate Burst Write Cycle H H X High Z...

Page 85: ...r R W DFS FBA 0000h 0000h 0000h 0000h N A F101h Start Address2 Register R W DBS 0000h 0000h 0000h 0000h N A F102h Start Address3 Register R W FCBA 0000h 0000h 0000h 0000h N A F103h Start Address4 Register R W FCPA FCSA 0000h 0000h 0000h 0000h N A F104h Start Address5 Register R W FPC 0000h 0000h 0000h 0000h N A F107h Start Address8 Register R W FPA FSA 0000h 0000h 0000h 0000h N A F200h Start Buffe...

Page 86: ...status The BufferRAM data is kept unchanged after Warm Hot reset operations The device guarantees the logic reset operation in case RP pulse is longer than tRP min 200ns The device may reset if tRP tRP min 200ns but this is not guaranteed Warm reset will abort the current NAND Flash core operation During a warm reset the content of memory cells being altered is no longer valid as the data will be ...

Page 87: ...ash array goes to a locked state after a Cold or Warm Reset Software Write Protection Operation The software write protection operation is implemented by writing a Lock command 002Ah or a Lock tight command 002Ch to command register F220h Lock 002Ah and Lock tight 002Ch commands write protects the block defined in the Start Block Address Register F24Ch 3 4 3 NAND Array Write Protection States Ther...

Page 88: ...anged to locked tight state the all block unlock command will fail In order to use all block unlock command again a cold reset is needed 3 4 3 2 Locked NAND Array Write Protection State A Locked block cannot be programmed or erased All blocks default to a locked state following a Cold or Warm Reset Unlocked blocks can be changed to locked using the Lock block command The status of a locked block c...

Page 89: ... reset is needed A block must first be set to a locked state before it can be changed to locked tight using the Lock tight command 3 4 4 NAND Flash Array Write Protection State Diagram NOTE If the 1st Block is set to be OTP Block 0 will always be Lock Status Lock Tight Command Sequence Start block address Lock tight block command 002Ch Locked tight Power On Start block address Unlock block Command...

Page 90: ...rt Lock Unlock Lock Tight Write lock unlock lock tight Add F220h DQ 002Ah 0023h 002Ch Wait for INT register low to high transition Add F241h DQ 15 INT Write 0 to interrupt register1 Add F241h DQ 0000h Command completed Write DFS of Flash Add F100h DQ DFS Write SBA of Flash Add F24Ch DQ SBA Select DataRAM for DDP Add F101h DQ DBS Add F240h DQ 10 0 pass Read Controller Status Register Add F24Eh DQ 2...

Page 91: ...e ignored when using INT auto mode Refer to chapter 2 8 18 1 Unlock All Block Write All Block Unlock Add F220h DQ 0027h Wait for INT register low to high transition Add F241h DQ 15 INT Command completed Write 0 to interrupt register1 Add F241h DQ 0000h Write SBA of Flash Add F24Ch DQ SBA 000h DFS DBS is for DDP Add F240h DQ 10 0 pass Read Controller Status Register Add F24Eh DQ 2 0 US LS LTS Read ...

Page 92: ...n be an asynchronous read mode or synchronous read mode The status information related to load operation can be checked by the host if required The device has a dual data buffer memory architecture DataRAM0 DataRAM1 each 2KB in size Each DataRAM buffer has 4 Sectors The device is capable of independent and simultaneous data read operation from one data buffer and data load operation to the other d...

Page 93: ...d data at the outputs The Output Enable access time tOE is the delay from the falling edge of OE to valid data at the output 3 7 2 Synchronous Read Mode Operation RM 1 WM X See Timing Diagrams 6 1 and 6 2 In a Synchronous Read Mode data is output with respect to a clock input The device is capable of a continuous linear burst operation and a fixed length linear burst operation of a preset length B...

Page 94: ...Hot Reset or a WE low pulse will terminate the burst read operation Synchronous Read Boundary 3 7 2 2 4 8 16 32 Word Linear Burst Read Operation See Timing Diagram 6 1 An alternate Burst Read Mode enables a fixed number of words to be read from consecutive address The device supports a burst read from consecutive addresses of 4 8 16 and 32 words with a linear wrap around When the last word in the ...

Page 95: ...MHz BRWL should be 6 or 7 while HF 1 Also for frequency under 40MHz BRWL can be reduced to 3 and HF 0 3 7 3 Handshaking Operation The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready to be read To set the number of initial cycles for optimal burst mode the host should use the programmable burst rea...

Page 96: ... for first page is Copy back registers FCBA FCPA and FCSA and the registers used for addressing second page and follow ing cache read are normal address registers FBA FPA and FSA At Cache Read Operation FCSA and FSA must be set to 00 BSA setting is only required once at First Cache Read cycle From the following cycles BSA will be automatically switched to select DataRAM0 and DataRAM1 alternately B...

Page 97: ...SA2 of Flash3 Add F107h DQ FPA FSA END Add F220h DQ 000Ch Host reads data from DataRAM6 Wait for INT high State Add F241h DQ 15 INT Read Controller Status Add F240h DQ 10 Error Register DQ 10 0 Yes No Host reads data from DataRAM Write Finish Cache Read Command Final Read Write DFS FBA of Flash Add F100h DQ DFS FBA Write DFS FBA of Flash3 Add F100h DQ DFS FBA Read Controller Status DQ 15 Ongo DQ 1...

Page 98: ...load FBA and FPA Command Setting It consists of writing 0 to Interrupt register and writing command to Command register In INT auto mode writing 0 to Interrupt register may be ignored Status Read It consists of INT high state checking and Controller Status Register checking step Host read 1st nth data from DataRAM During this step Host can read data from DataRAM by any read mode which supported by...

Page 99: ... reads 1 page data from DataRAM host must confirm INT pin or bit return low to high and then enable CE to read 1 page of data And when host read operation for this 1 page is done INT will automatically turn low Note that INT auto mode is a mandatory option for Synchronous Burst Block Read and WE must always be set high throughout this operation Therefore the steps are as follows 1 Host will deasse...

Page 100: ...z to 66MHz latency cycle should be over 4 And at 83MHz frequency BRWL should be set to 6 BRWL can be set up to 7 latency cycles The BRWL registers can be read during a burst read mode by using the AVD signal with an address 3 9 2 Continuous Linear Burst Read Operation During Synchronous Burst Block Read Mode First Clock Cycle The initial word is output at tIAA after the rising edge of the first CL...

Page 101: ...16Q2A DEBx 101 FLASH MEMORY MuxOneNAND4G KFN4G16Q2A DEBx Synchronous Burst Block Read Boundary Read Sequence for Single Plane Device note that only main area data is read Main Area Spare Area Page 0 Page 63 Not supported ...

Page 102: ...mable burst read latency just same manner as normal synchronous burst read mode Upon power up the number of initial clock cycles from Valid Address AVD to initial data defaults to four clocks The number of clock cycles n which are inserted after the clock which is latching the address The host can read the first data with the n 1 th rising edge The number of total initial access cycles is programm...

Page 103: ...ble the CE of OneNAND in order to operate another device Even if host does not operate another device CE should be disabled during INT low Write DFS FBA of Flash Add F100h DQ DFS FBA Start Write FPA FSA of Flash Add F107h DQ FPA FSA1 Write FPC of Flash Add F104h DQ FPC Write Synchronous Burst Add F220h DQ 000Ah Block Read Command Wait for INT register or PIN3 low to high transition Add F241h DQ 15...

Page 104: ...d MuxOneNAND device The RDY output will be asserted as soon as a burst is initiated and will be de asserted to indicate when data is to be transferred into or out of the memory The processor can access other devices without incurring the timing penalty of the initial latency for a new burst by suspend ing burst mode Bursts are suspended by stopping clk clk can be stopped high or low To continue th...

Page 105: ...e operation from the Host to one of data buffers and a program operation from the other data buffer to the NAND Flash Array memory Refer to Section 3 15 2 Write While Program Operation for more information Addressing for program operation Within a block the pages must be programmed consecutively from the LSB least significant bit page of the block to MSB most significant bit pages of the block Ran...

Page 106: ... of Controller Status Register F240h Data input from the Host to the DataRAM can be done at any time during the Internal Program Routine after Start but before the Write Pro gram Command is written DBS DFS is for DDP If program operation results in an error map out the block including the page in error and copy the target data to another block Write Program Command Add F220h DQ 0080h or 001Ah Wait...

Page 107: ...Dh issue 3 4KB data will be trasfered to each page buffer in two plane NAND Flash Array at the same time 4 The data will be placed on same page of respective blocks If the host wants to program data under 4 sector size unwanted area to be programmed must be written to all 1 s BSC must be set to 00 which is 4sectors Although host only set FBA i e even block in Plane1 and BSA i e DataRAM0 for the fi...

Page 108: ...h DQ FPA FSA4 Select DataRAM for DDP1 Add F101h DQ DBS Write Data into DataRAM2 ADD DP DQ Data in Write 2X Program Command Completed Wait for INT register low to high transition Add F241h DQ 15 INT NO YES DBS DFS is for DDP If program operation results in an error map out the block including the page in error and copy the target data to another block Write 0 to interrupt register5 Add F241h DQ 000...

Page 109: ...host wants to program data under 4 sector size unwanted area to be programmed must be written to all 1 s BSC must be set to 00 which is 4sectors When INT bit goes to 1 after second data transfer from DataRAMs to Pafe Buffers are complete user may check the Status Register to check the 2X program status During 2X Cache Program Error bit shows the status of previous program operation For the final 4...

Page 110: ...000h Write 2X Cache PGM CMD Add F220h DQ 007Fh Wait for INT register Add F241h DQ 8040h low to high transition DQ 10 0 YES Write DFS FBA of Flash Add F100h DQ DFS FBA2 Write FPA FSA of Flash Add F107h DQ FPA FSA3 Write BSA BSC of Flash3 Add F200h DQ BSA BSC Write 0 to interrupt register4 Add F241h DQ 0000h Write 2X PGM CMD Add F220h DQ 007Dh Wait for INT register Add F241h DQ INT low to high trans...

Page 111: ...it will go to 0 1 again NOTE 1 This is for INT auto mode for INT manual mode case user should write 0 to INT bit before issuing any command When INT bit goes to 1 after second data transfer from DataRAMs to Page Buffers are completed user may check the Status Register to check the 2X program status During 2X Cache Program Plane1 2 previous bit shows the status of previous program operation For the...

Page 112: ...DP1 Add F101h DQ DBS DQ 4 DQ 2 0 Last 2 Plane PGM for a chip Write DFS FBA of Flash Add F100h DQ DFS FBA2 Write FPA FSA of Flash Add F107h DQ FPA FSA3 Write BSA BSC of Flash3 Add F200h DQ BSA BSC Write Data into DataRAM0 1 Add DataRAM DQ Data 4KB Write 2X PGM CMD6 Add F220h DQ 007Dh Write DFS FBA of Flash Add F100h DQ DFS FBA2 Write FPA FSA of Flash Add F107h DQ FPA FSA3 Write BSA BSC of Flash3 Ad...

Page 113: ...uting a copy program using the address of the destination page Copy Back Program Operation Flow Chart NOTE 1 Selected DataRAM by BSA BSC is used for Copy back operation so previous data is overwritten 2 FBA FPA and FSA should be input prior to FCBA FCPA and FCSA 3 Write 0 to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 Start Write DFS FBA of Flash Add F...

Page 114: ...A identifies how many sectors and the location of the sectors in DataRAM that are used The destination address in the NAND Array is written using the Flash Copy Back Block Address FCBA Flash Copy Back Page Address FCPA and Flash Copy Back Sector Address FCSA The Copy Back Program command is issued to start programming Upon completion of copy back programming to the destination page address the Hos...

Page 115: ... to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 Start Write DFS FBA of Flash Add F100h DQ DFS FBA Write FPA FSA of Flash Add F107h DQ FPA FSA Write BSA BSC of DataRAM Add F200h DQ BSA BSC Select DataRAM for DDP Add F101h DQ DBS Write Load Command Add F220h DQ 0000h or 0013h Wait for INT register low to high transition Add F241h DQ 15 INT Read Controlle...

Page 116: ...o interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 Start Write DFS FBA of Flash Add F100h DQ DFS FBA Write Erase Command Add F220h DQ 0094h Wait for INT register Add F241h DQ 15 INT low to high transition If erase operation results in an error map out the failing block and replace it with another block Write 0 to interrupt register1 Add F241h DQ 0000h DFS i...

Page 117: ...hat the first block address to be latched is written to the time that the actual erase operation finishes During block address latch sequence issuing of other commands except Block Erase and Multi Block Erase at INT High will abort the current operation So to speak It will cancel the previously latched addresses of Multi Block Erase Operation On the other hand Other command issue at INT low will b...

Page 118: ...000h Command Erase Write DFS FBA of Flash Add F100h DQ DFS FBA Write Block Erase Add F220h DQ 0094h Wait for INT register Add F241h DQ 15 INT low to high transition Write 0 to interrupt register2 Add F241h DQ 0000h Command Multi Block Erase Verify Read Write DFS FBA of Flash Add F100h DQ DFS FBA Write Multi Block Erase Add F220h DQ 0071h Wait for INT register Add F241h DQ 15 INT low to high transi...

Page 119: ... operation stop a NAND Flash Core Reset command should be issued For the duration of the Erase Suspend period the following commands are not accepted Block Erase Multi Block Erase Erase Suspend Erase Suspend and Erase Resume Operation Flow Chart NOTE 1 Erase Suspend command input is prohibited during Multi Block Erase address latch period 2 If OTP access mode exit happens with Reset operation duri...

Page 120: ...eration is performed Exiting the OTP Block during an Erase Operation If the Reset triggered exit from the OTP Access Mode happens during an Erase Suspend Operation the erase routine could fail Therefore to exit from the OTP Access Mode without suspending the erase operation stop a NAND Flash Core Reset command should be issued The OTP Block Page Assignments OTP area is one block size 128KB 4KB 64 ...

Page 121: ...ck OTP Area Structure Page 2KB 64B Sector main area 512B Sector spare area 16B One Block 128KB 4KB 64pages Manufacturer Area page 50 to page 63 14pages User Area page 0 to page 49 50pages Page 2KB 64B Sector main area 512B Sector spare area 16B One Block 128KB 4KB 64pages User Area page 0 to page 63 64pages ...

Page 122: ...per formed OTP Block Read Operation Flow Chart NOTE 1 FBA NAND Flash Block Address could be omitted or any address in a single die package FBA must be an address of a chip containing OTP block that is supposed to be accessed in DDP 2 Write 0 to interrupt register step may be ignored when using INT auto mode Refer to chapter 2 8 18 1 Start Wait for INT register Add F241h DQ 15 INT Write 0 to interr...

Page 123: ...med using the same sequence as normal program operation after being accessed by the command see section 3 8 for more information Programming the OTP Area Issue the OTP Access Command Write data into the DataRAM data can be input at anytime between the Start and Write Program commands Issue a Flash Block Address FBA which is unlocked area address of NAND Flash Array address map Issue a Write Progra...

Page 124: ... BSC Write Data into DataRAM2 Add DP DQ Data in OTP Programming completed Write Program command DQ 0080h or 001Ah Completed Wait for INT register low to high transition Add F241h DQ 15 INT NO Add F220h Wait for INT register Add F241h DQ 15 INT Write 0 to interrupt register4 Add F241h DQ 0000h low to high transition Do Cold Warm Hot OTP Exit Automatically checked Wait for INT register low to high t...

Page 125: ...P block At device power up this word location is checked and if XXFCh is found the OTPL bit of the Controller Status Register is set to 1 indicating the OTP is locked When the Program Operation finds that the status of the OTP is locked the device updates the Error Bit of the Controller Status Register as 1 fail OTP Lock Operation Steps Issue the OTP Access Command Fill data to be programmed into ...

Page 126: ...Write BSA BSC of DataRAM Add F200h DQ 0801h 0C01h Write Data into DataRAM2 Add 8th Word Write Program command DQ 0080h or 001Ah Wait for INT register low to high transition Add F241h DQ 15 INT Add F220h Write 0 to interrupt register4 Add F241h DQ 0000h Automatically updated DQ XXFCh in sector0 spare page0 OTP lock completed Write DFS FBA of Flash Add F100h DQ DFS FBA3 Write OTP Access Command Add ...

Page 127: ...the status of the 1st Block is locked the device updates the Error Bit of the Controller Status Register as 1 fail 1st Block OTP Lock Operation Steps Issue the OTP Access Command Fill data to be programmed into DataRAM data can be input at anytime between the Start and Write Program commands Write XXF3h data into the 8th word of sector0 in page0 spare area of the DataRAM Issue a Flash Block Addres...

Page 128: ...te BSA BSC of DataRAM Add F200h DQ 0801h 0C01h Write Data into DataRAM2 Add 8th Word Write Program command DQ 0080h or 001Ah Wait for INT register low to high transition Add F241h DQ 15 INT Add F220h Write 0 to interrupt register4 Add F241h DQ 0000h Automatically updated DQ XXF3h in sector0 spare page0 1st Block OTP lock completed Write DFS FBA of Flash Add F100h DQ DFS FBA3 Write OTP Access Comma...

Page 129: ... the Program Operation finds that the status of the OTP and 1st Block is locked the device updates the Error Bit of the Controller Status Register as 1 fail OTP and 1st Block OTP simultaneous Lock Operation Steps Issue the OTP Access Command Fill data to be programmed into DataRAM data can be input at anytime between the Start and Write Program commands Write XXF0h data into the 8th word of sector...

Page 130: ... BSC of DataRAM Add F200h DQ 0801h 0C01h Write Data into DataRAM2 Add 8th Word Write Program command DQ 0080h or 001Ah Wait for INT register low to high transition Add F241h DQ 15 INT Add F220h Write 0 to interrupt register4 Add F241h DQ 0000h Automatically updated DQ XXF0h in sector0 spare page0 OTP and 1st Block OTP lock completed Write DFS FBA of Flash Add F100h DQ DFS FBA3 Write OTP Access Com...

Page 131: ...it will fail the internal load operation Address registers should not be updated until internal operation is completed 3 15 2 Write While Program Operation This operation accelerates the programming performance of the device by enabling data to be written by the host into one DataRAM buffer while the NAND Flash Array memory is being programmed with data from the other DataRAM buffer The dual data ...

Page 132: ...aded DBn_add DataRAM Address to be loaded CMD_reg Command Register Address LD_CMD Load Command Data Load_DBn Load Data from NAND Flash Array to DataRAMn CS_reg Controller Status Register Address Data Read_DBn Read Data from DBn 1 AVD Add_ reg Flash _add Add_ reg DB1 _add CMD_ reg CS_ reg Data Load _DB0 Data Load _DB1 Data Read _DB0 LD_ CMD Read Status Add_ reg Flash _add Add_ reg DB0 _add CMD_ reg...

Page 133: ... Flash Address to be programmed Int_reg Interrupt Register Address CMD_reg Command Register Address PD_CMD Program Command Data PGM_PageA Program Data from DataRAM to PageA CS_reg Controller Status Register Address 1 AVD Data Write _DB0 Data PGM _PageA Add_ reg Flash _add Add_ reg DB0 _add Int_ reg 0000h CMD_ reg PD_ CMD Data Write _DB1 Add_ reg Flash _add CS_ reg Read Status Add_ reg DB1 _add Int...

Page 134: ...than twice utilizing asynchronous Figure 6 22 6 23 the host will read toggled value of DQ6 and the rest of DQ s are not guaranteed to be fixed value DQ6 toggle is only for reading status of BufferRAM which is being loaded by internal operation that is BufferRAM designated by BSA Host may read previous data from BufferRAM not pointed by BSA during internal load operation DQ6 toggle bit is read at t...

Page 135: ...atically corrects ECC error When the device reads the NAND Flash Array memory main and spare area data with an ECC operation the device doesn t place the newly generated ECC for main and spare area into the buffer Instead it places the ECC which was generated and written during the program oper ation into the buffer An ECC operation is also done during the Boot Loading operation 3 17 1 ECC Bypass ...

Page 136: ...ays fully guaranteed to be a valid block Due to invalid marking during load operation for identifying invalid block a load error may occur 3 18 1 Invalid Block Identification Table Operation A system must be able to recognize invalid block s based on the original invalid block information and create an invalid block table Invalid blocks are identified by erasing all address locations in the NAND F...

Page 137: ...ge program does not affect the data of the other pages in the same block a block replacement can be executed with a page sized buffer by find ing an erased empty block and reprogramming the current target data and copying the rest of the replaced block Block Failure Modes and Countermeasures Failure Mode Detection and Countermeasure sequence Erase Failure Status Read after Erase Block Replacement ...

Page 138: ... via data buffer0 Then copy the nth page data of block A in the data buffer1 to the nth page of block B or any free block Do not further erase or program block A but instead complete the operation by creating an Invalid Block Table or other appropriate scheme Block Replacement Operation Sequence Data Buffer1 of the device 1st Block A Block B n 1 th nth page 1st n 1 th nth page an error occurs 1 2 ...

Page 139: ...eet Exposure to absolute maximum rating conditions for extended periods may affect reliability 4 2 Operating Conditions Voltage reference to GND NOTE 1 Vcc Core or Vcc should reach the operating voltage level prior to or at the same time as Vcc IO or Vccq Parameter Symbol Rating Unit Voltage on any pin relative to VSS Vcc Vcc 0 5 to 2 45 V All Pins VIN 0 5 to 2 45 Temperature Under Bias Extended T...

Page 140: ... 25 35 mA 1MHz 3 4 mA 66MHz DDP 30 38 mA 83MHz DDP 35 45 mA 1MHz DDP 3 4 mA Active Burst Write Current Note 2 ICC2W CE VIL OE VIH WE VIL 66MHz 20 30 mA 83MHz 25 35 mA 1MHz 3 4 mA 66MHz DDP 30 38 mA 83MHz DDP 35 45 mA 1MHz DDP 3 4 mA Active Asynchronous Write Current Note 2 ICC3 CE VIL OE VIH Single 8 15 mA DDP 17 25 mA Active Load Current Note 3 ICC4 CE VIL OE VIH WE VIH 30 40 mA Active Program Cu...

Page 141: ...e 1st block which is placed on 00h block address is guaranteed to be a valid block up to 1K program erase cycles with 1bit 512Byte ECC Parameter Value 66MHz Value 83MHz Input Pulse Levels 0V to VCC 0V to VCC Input Rise and Fall Times CLK 3ns 2ns other inputs 5ns 2ns Input and Output Timing Levels VCC 2 VCC 2 Output Load CL 30pF CL 30pF Item Symbol Test Condition Single DDP Unit Min Max Min Max Inp...

Page 142: ...Unit Min Max Min Max Clock CLK 1 66 1 83 MHz Clock Cycle tCLK 15 12 ns Initial Access Time tIAA 70 70 ns Burst Access Time Valid Clock to Output Delay tBA 11 9 ns AVD Setup Time to CLK tAVDS 5 4 ns AVD Hold Time from CLK tAVDH 2 2 ns AVD High to OE Low tAVDO 0 0 ns Address Setup Time to CLK tACS 5 4 ns Address Hold Time from CLK tACH 6 6 ns Data Hold Time from Next Clock Cycle tBDH 3 2 ns Output E...

Page 143: ...ranteed Parameter Symbol KFM2G16Q2A KFN4G16Q2A Unit Min Max Access Time from CE Low tCE 76 ns Asynchronous Access Time from AVD Low tAA 76 ns Asynchronous Access Time from address valid tACC 76 ns Read Cycle Time tRC 76 ns AVD Low Time tAVDP 12 ns Address Setup to rising edge of AVD tAAVDS 5 ns Address Hold from rising edge of AVD tAAVDH 6 ns Output Enable to Output Valid tOE 20 ns CE Setup to AVD...

Page 144: ... ns CE Low to RDY Valid tCER 15 ns CE Disable to Output RDY High Z tCEZ 20 ns Parameter Symbol 66MHz 83MHz Unit Min Max Min Max Clock CLK1 1 66 1 83 MHz Clock Cycle tCLK 15 12 ns AVD Setup to CLK tAVDS 5 4 ns AVD Hold Time from CLK tAVDH 2 2 ns Address Setup Time to CLK tACS 5 4 ns Address Hold Time from CLK tACH 6 6 ns Data Setup Time to CLK tWDS 5 4 ns Data Hold Time from CLK tWDH 2 2 ns WE Setu...

Page 145: ...grams 6 3 6 4 Parameter Symbol Min Typ Max Unit Spare Load time Note 1 Note2 tRD1 23 35 µs Sector Load time Note 1 Page Load time Note 1 tRD2 30 45 µs Spare Program time Note 1 Note3 tPGM1 205 720 µs Sector Program time Note 1 Page Pogram time Note 1 tPGM2 220 750 µs OTP Access Time Note 1 tOTP 500 700 ns Lock Unlock Lock tight Note 1 tLOCK 500 700 ns All Block Unlock Time tABU 2 3 µs Erase Suspen...

Page 146: ... with Wrap Around See AC Characteristics Table 5 4 tCES tAVDS tAVDH tACS tACH tIAA tRDYO tBA tBDH tCLK Hi Z CE CLK AVD OE RDY tRDYS tRDYA tOE A DQ0 A DQ15 tCER tAVDO tCEZ tOEZ D6 D7 D0 D1 D2 D3 D7 D0 tCLKH tCLKL Hi Z tCER 1 0 1 2 3 4 BRWL 4 tCES tAVDS tAVDH tACS tACH tIAA tBA tBDH tCLK Hi Z CE CLK AVD OE RDY tRDYS tRDYA tOE A DQ0 A DQ15 tCEZ tOEZ Da 1 Da 2 Da 3 Da 4 Da 5 Da n Da n 1 tAVDO Hi Z tRD...

Page 147: ... CS AVD V IL t DH t RD2 CA SBBRCD FPC AA ADQ15 Hi Z D0 D1 D2 RDY NOTE Asynchronous write was used in this timing diagram Synchronous write is also possible 1 AA Address of address register CA Address of command register SBBRCD Synchronous Burst Block Read Command FBA Flash Block Address FPA Flash Page Address BSA BufferRAM Sector Address FPC Number of Flash Page to be read 3pages 64pages Synchrono...

Page 148: ...lock Read Command ADQ0 CE CLK RDY High Z High Z INT Indicator for DataRAM s Status Ready High Busy Low RDY Indicator for Latency of Sync Burst Block Read Burst Length 4 8 16 32 1K Word and Continuous Synchronous Burst Block Read are available A1 A4 For the fixed number of words linear burst block read A1 A4 are start address of the each DataRAM For detailed timing diagram refer to Chapter 6 3 WE m...

Page 149: ...icator for Latency of Sync Burst Block Read Burst Length 4 8 16 32 1K Word Synchronous Burst Block Read are available A1 1 A1 N Address where each burst data initiates and this may differ for different settings of BSA and BL N can be calculated by 1024w BL Therefore for above case BSA 0200h and BL 8word So that N 128 A1 1 0200h A1 2 0208h A1 128 05F8h WE must be set high throughout the operation A...

Page 150: ...2 6 23 for tASO 6 6 Asynchronous Read VA Transition After AVD Low See AC Characteristics Table 5 5 NOTE VA Valid Read Address RD Read Data See timing diagram 6 22 6 23 for tASO tOE VA Valid RD tCE tOEZ tAAVDH tAVDP tAAVDS CE OE WE A DQ0 AVD A DQ15 Hi Z Hi Z RDY tAA tRC tWEA tCA tCEZ tCER tAVDO Hi Z tOE VA Valid RD tOEZ tACC tAAVDH tAVDP tAAVDS CE OE WE A DQ0 AVD A DQ15 tWEA tCEZ tCA tCER tAVDO Hi ...

Page 151: ...xOneNAND4G KFN4G16Q2A DEBx 6 7 Asynchronous Write See AC Characteristics Table 5 7 NOTE VA Valid Read Address WD Write Data CE WE OE RP tCS tDS RDY tWPL tWPH tWC tCER Hi Z Hi Z CLK VIL tCH Valid WD VA Valid WD AVD tAAVDS tAVDP tAAVDH tWEA tDH tCEZ VA ...

Page 152: ...tCES tAVDS tAVDH tACS tACH tRDYO tWDH tWDS tCLK Hi Z CE CLK AVD OE RDY tRDYS tRDYA A DQ0 A DQ15 tCER tCEZ D0 D1 D2 D3 D4 D5 D7 tCLKH tCLKL Hi Z tCER WE tWES tWEH tCEH 1 0 1 2 3 4 BRWL 4 tCES tAVDS tAVDH tACS tACH tRDYO tWDH tWDS tCLK Hi Z CE CLK AVD OE RDY tRDYS tRDYA BRWL 4 A DQ0 A DQ15 tCE D1 D2 D7 tCLKH tCLKL Hi Z tCER WE D0 D1 D7 tCEHP tWES tCES tCE tCER tAVDS tAVDH tACS tACH tRDYO tRDYS tRDYA...

Page 153: ...KFN4G16Q2A DEBx 6 10 Start Initial Burst Write Operation See AC Characteristics Table 5 8 tCES tAVDS tAVDH tACS tACH tRDYO tWDH tWDS tCLK Hi Z CE CLK AVD OE RDY tRDYS tRDYA A DQ0 tCER D0 tCLKH tCLKL tCER WE tWES tWEH tCEH 1 0 1 2 3 4 BRWL 4 tCEZ tCEHP D0 BRWL 4 ...

Page 154: ...to be loaded BA Address of BufferRAM to load the data SA Address of status register 2 In progress and complete refer to status register 3 Status reads in this figure is asynchronous read but status read in synchronous mode is also supported tCER Load Command Sequence last two cycles WE CE CLK tAVDP tDS tDH tCH tWPL tWPH tWC SA BA Completed Da n LCD CA LMA AA ADQ0 15 OE Read Data VIL tWEA tAAVDS tA...

Page 155: ...atus register AA Address of Start Address1 Register for Flash Block Address PMB DFS FBA Flash Block address of memory to be programmed next time 2 In progress and complete refer to status register 3 Status reads in this figure is asynchronous read but status read in synchronous mode is also supported Program Command Sequence last two cycles WE CE CLK tDS tDH tCH tWPL tCS tWPH tWC SA SA In Progress...

Page 156: ...roller Status Register 15 F240h 4KB data input Asynch Write Synch Write available Command input and INT pin behavior is based on INT auto mode In INT manual mode writing 0 to interrupt register is required before command issue 1st data input Address Setting ADQ0 ADQ15 A1 INT 4KB data into 2 DataRAMs 2X program Command Ongoing Status Controller Status Register Check Plane1 Plane2 current Pass 0 Fai...

Page 157: ... pin behavior is based on INT auto mode In INT manual mode writing 0 to interrupt register is required before command issue ADQ15 A1 A2 High Z INT 4KB data into 2 DataRAMs 4KB data into 2 DataRAMs 2X Cache program Command 2X program Command 3nd data input A3 4KB data into 2 DataRAMs Ongoing Status Controller Status Register Check Plane1 Plane2 current Invalid Plane1 Plane2 previous Pass 0 Fail 1 C...

Page 158: ...data into 2 DataRAMs Ongoing Status Controller Status Register Check Plane1 Plane2 current Invalid Plane1 Plane2 previous Pass 0 Fail 1 Controller Status Register Check Plane1 Plane2 current Pass 0 Fail 1 Plane1 Plane2 previous Pass 0 Fail 1 1st data input 2nd data input Address Setting 2X cache program Command ADQ0 ADQ15 A1 A2 4KB data into 2 DataRAMs 4KB data into 2 DataRAMs 2X Cache program Com...

Page 159: ...ress of Start Address1 Register for Flash Block Address PMB DFS FBA Flash Block address of memory to be programmed next time 2 For In progress and complete status refer to status register 3 Status reads in this figure is asynchronous read but status read in synchronous mode is also supported Erase Command Sequence WE CE CLK tAVDP tAAVDS tAAVDH tDS tDH tCH tWPL tWPH tWC ECD CA EMA AA A DQ0 A DQ15 O...

Page 160: ...rom sector0 and sector1 page0 block0 of NAND Flash array to BootRAM Host can read Bootcode in BootRAM 1K bytes after Bootcode copy completion 3 INT register goes Low to High on the condition of Bootcode copy done and RP rising edge If RP goes Low to High before Bootcode copy done INT register goes to Low to High as soon as Bootcode copy done System Power Sleep Bootcode copy Idle Bootcode copy done...

Page 161: ...us where reset is ongoing 3 The status allows only BootRAM BL1 read operation for Boot Sequence refer to 7 2 2 Boot Sequence 4 To read BL2 of Boot Sequence Host should wait INT until becomes ready and then Host can issue load command refer to 7 2 2 Boot Sequence 7 1 Methods of Determining Interrupt status CE OE RP tRP tReady1 RDY INT High Z High Z tReady2 Idle1 Operation Status Reset Ongoing2 Boot...

Page 162: ...ters and makes output signals go to default status and bufferRAM data are kept unchanged after Warm Hot reset operations 2 Reset command Command based reset or Register based reset 3 BP Boot Partition BootRAM area 0000h 01FFh 8000h 800Fh 4 00F0h for BP and 00F3h for F220h AVD BP Note 3 ADQi 00F0h CE or F220h or 00F3h INT WE OE tReady2 bit RDY Operation or Idle MuxOneNAND reset Idle MuxOneNAND Oper...

Page 163: ...r protection from any involuntary program erase during power transitions RP pin provides hardware protection and is recommended to be kept at VIL before Vcc drops to 1 5V AVD ADQi 00F0h CE F220h RDY Operation or Idle NAND Flash Core reset Idle MuxOneNAND Operation High Z INT WE OE tReady2 bit VCC RP MuxOneNAND Logic Reset NAND Array Write Protected INT MuxOneNAND Operation typ 1 5V 0V ...

Page 164: ...3 Toggle Bit Timing in Asynchronous Read VA Transition After AVD Low See AC Characteristics Table 5 5 NOTE 1 VA Valid Read Address RD Read Data 2 Before IOBE is set to 1 RDY and INT pin are High Z state 3 Refer to chapter 5 5 for tASO description and value tOE Status RD1 tCE tOEZ tAVDP CE OE WE A DQ0 AVD A DQ15 Hi Z RDY2 tAA tRC tCA tCEZ tCER tAVDO Hi Z VA Status RD Hi Z tASO tAAVDH tAAVDS VA1 tOE...

Page 165: ... AC Characteristics Tables 5 10 NOTE INT pin polarity is based on IOBE 1 and INT pol 1 default setting Write command into Command Register INT will automatically turn to Busy State INT will automatically turn back to ready state when designated operation is completed INT pin INT bit tWB WE ADQ CMD ...

Page 166: ...r load operation In its normal state the INT pin is high if the INT polarity bit is default In case of normal INT mode before a command is written to the com mand register the INT bit must be written to 0 for the INT pin transitions to a low state indicating start of the operation In case of INT auto mode INT bit is written to 0 automatically right after command issued Upon completion of the comma...

Page 167: ...ied directly to a Host GPIO RDY could be connected as one of following guides Asynchronous Mode Using the INT Pin When configured to operate in an asynchronous mode CE AVD and OE of the MuxOneNAND are tied to corresponding pins of the Host CLK is tied to the Host Vss Ground RDY is tied to a no connect OE of the MuxOneNAND and Host are tied together and INT is tied to a GPIO INT COMMAND Host MuxOne...

Page 168: ...chronous Mode Using Interrupt Status Register Bit Polling When operating synchronously CE AVD CLK RDY OE and DQ pins on the host and MuxOneNAND are tied together RDY could be connected as one of following guides Asynchronous Mode Using Interrupt Status Register Bit Polling When configured to operate in an asynchronous mode CE AVD OE and DQ of the MuxOneNAND are tied to corresponding pins of the Ho...

Page 169: ...se at DDP option the pull up resis tor value is related to tr INT And appropriate value can be obtained with the following reference charts NOTE 1 Refer to chapter 2 8 10 Start Address Register F101h DDP Block Diagram Busy State Ready Vcc VOH tf tr VOL Vss 50k ohm INT1 Vcc or Vccq Rp INT pol High Default tr tf Ibusy mA Rp ohm Ibusy tr us KFN4G16Q2A Vcc 1 8V Ta 25 C CL 30pF 1K 10K 20K 30K 0 1373 tf...

Page 170: ... DDP Block Diagram 50k ohm INT1 Vcc or Vccq Rp INT pol Low Busy State Ready VOH tf tr VOL Vss Vcc tr tf Ibusy mA Rp ohm Ibusy tf us KFN4G16Q2A Vcc 1 8V Ta 25 C CL 30pF 1K 10K 20K 30K 0 1059 tr ns 0 8088 1 284 1 598 2 976 2 919 2 916 2 915 1 76 0 18 0 09 40K 50K 1 822 1 989 2 914 2 914 0 045 0 06 0 036 Open 100K 2 442 0 018 ª ª ª ª ª ª ...

Page 171: ...fetch time A typical boot scheme usually used to boot the system with MuxOneNAND is explained at Partition of NAND Flash Array and MuxOneNAND Boot Sequence In this boot scheme boot code is comprised of BL1 where BL stands for Boot Loader BL2 and BL3 Moreover the size of the boot code is larger than 3KB the 3rd case above BL1 is called primary boot loader in other words Here is the table of detaile...

Page 172: ...ck 1 Block 0 Partition 5 Sector 0 Sector 1 Sector 2 Sector 3 Page 63 Page 62 Page 2 Page 1 Page 0 BL2 Partition 4 Partition 3 Reservoir File System Os Image BL3 BL2 BL1 Partition 6 Block 162 Block 2 Block 1 Block 0 Partition 5 Sector 0 Sector 1 Sector 2 Sector 3 Page 63 Page 62 Page 2 Page 1 Page 0 Partition 4 Partition 3 BL1 Block 2047 Reservoir File System Os Image BL2 BL1 Os Image BL 2 NAND Fla...

Page 173: ...0 80x9 7 20 A 0 80x11 8 80 63 0 45 0 05 G 4 40 0 80 B 0 20 M A B Datum A Datum B 2 5 4 3 1 6 3 60 A1 INDEX H 10 00 0 10 13 00 0 10 A1 13 00 0 10 0 80 10 00 0 10 13 00 0 10 0 10 MAX 0 45 0 05 0 32 0 05 1 1 0 10 BOTTOM VIEW TOP VIEW A C E B D F 0 80x9 7 20 A 0 80x11 8 80 63 0 45 0 05 G 4 40 0 80 B 0 20 M A B Datum A Datum B 2 5 4 3 1 6 3 60 A1 INDEX H 10 00 0 10 13 00 0 10 A1 13 00 0 10 0 80 10 00 0...

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