MuxOneNAND2G(KFM2G16Q2A-DEBx)
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FLASH MEMORY
MuxOneNAND4G(KFN4G16Q2A-DEBx)
6.11 Load Operation Timing
See AC Characteristics Tables 5.5, 5.7 and 5.9.
NOTE :
1) AA = Address of address register
CA = Address of command register
LCD = Load Command
LMA = Address of memory to be loaded
BA = Address of BufferRAM to load the data
SA = Address of status register
2) “In progress” and “complete” refer to status register
3) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
t
CER
Load Command Sequence (last two cycles)
WE
CE
CLK
t
AVDP
t
DS
t
DH
t
CH
t
WPL
t
WPH
t
WC
SA
BA
Completed
Da+n
LCD
CA
LMA
AA
ADQ0~15
OE
Read Data
V
IL
≈
≈
≈
≈
≈
≈
t
WEA
t
AAVDS
t
AAVDH
t
RD1 or tRD2
INT
t
CS
AVD
RDY
Hi-Z
t
CER
t
CEZ
bit
t
CEZ