Samsung
Confidential
MUX
Option For External GFX
CLK1_WIPCIE*
DMI
Page 8
CLOCK DISTRIBUTION
SAMSUNG ELECTRONICS CO’S PROPERTY.
DPLLA
MPLL
DRAW
HD Audio
MDC
EXPRESS
32.768 KHz
CHP3_SATACLKREQ*
EXP3_CLKREQ*
Crestline
PCI Express Gfx
LAST EDIT
CLK1_SATA/SATA*
4
4
14.318 MHz
ELECTRONICS
667/533/400 MHz
CLK1_MCLK3/3*
B
B
14 MHz
OSC
D
CPU
GMCH
PAGE
33 MHz
CLK3_PCLKMICOM
3
100 MHz
Rev. 0.8
1
SLG8SP513
100 MHz
SAMSUNG PROPRIETARY
SSC
CPU_STP*
ITP_EN
SSC
33 MHz
RTC Clock
24.576 MHz
MUX
SPI3_CLK
DATE
DEV. STEP
HPLL
FS(2:0)
33 MHz
CLK3_PCLKCB
SS(96/100) SEL
PCI_STP*
PEX3_CLKREQ* (TBD)
ROBSON
P0.8V
MODULE CODE
CLK0_HOST_CPU/CPU*
200 MHz
REV
PEX3_CLKREQ* (TBD)
100 MHz
CLK3_USB48
CLK1_NF*
100 MHz
CLK3_PCLKSIO
33 MHz
100 MHz
MINI PCIE
A
A
TPM 1.2
PORT 80
96 MHz
CLK1_PCIEICH/ICH*
48 MHz
KBC
TITLE
PART NO.
14.318 MHz
CLK3_SIO14
10 MHz
2801-003730
CLK3_PCLKICH
33 MHz
1
33 MHz
D
CLK1_DCKLAN*
MDC3_BCLK
3
2801-003892
Buffer
MUX
LAN3_PHYCLK
BSEL
CLK1_DREFSSC/SSC*
100 MHz
Main PLL
MCH3_CLKREQ*
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
100 MHz
CLK1_MINIPCIE/PCIE*
USBPLL
SATAPLL
SPI
CLK0_HOST_GMCH/GMCH*
2
2
CLK1_MCH3GPLL/3GPLL*
PCIE PLL
333/266/200 MHz
333/266/200 MHz
DPLLB
ICH8-M
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
32.768 KHz
CLK3_GFX_27M/SSC
CLK1_MCLK0/0*
CLK1_MCLK1/1*
100 MHz
333/266/200 MHz
100 MHz
LAN (3rd Vender)
333/266/200 MHz
OSC
DCK LAN
SODIMM #0
CLK1_MCLK4/4*
CHECK
APPROVAL
HD 24 MHz
AUD3_BCLK
33 MHz
CLK3_PCLKPORT80
CARDBUS
HDSPA
100 MHz
CLK3_PCLKMIN
100 MHz
CLK3_ICH14
CK-505M (w/ CLKREQ* & SSDC)
LCI LAN
(Intel)
CLK1_DREFCLK/CLK*
CARD
100 MHz
100 MHz
CLK3_TPMLPC
CLK1_PEG/PEG*
MINI PCI
25 MHz
1394 Clock
OF
SAMSUNG
2801-003856
2801-003898
17.86 MHz
PEX3_CLKREQ* (TBD)
SODIMM #1
C
C
32.768 KHz
48MHz PLL
PLL3
200 MHz
CLK_3.3V_M
CLK3_PWRGD*
SUN XIAO
WUSHIJIANG
KEVIN LEE
6/26/2007
PV2
1.0
October 23, 2007 10:38:02 AM
BA41-XXXXX
7
58
Gevena
CLOCK DIAGRAM
PCIEPLL
CARD
SIO
100 MHz
FSB
PEG
33 MHz
