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INTERRUPTS

KS57C2308/P2308/C2316/P2316

7-6

Multi-Level Interrupt Handling

With multi-level interrupt handling, a lower-priority interrupt request can be executed by manipulating the
interrupt status flags, IS0 and IS1 while a high-priority interrupt is being serviced (see Table 7-2).

When an interrupt is requested during normal program execution, interrupt status flags IS0 and IS1 are set to "1"
and "0", respectively. This setting allows only highest-priority interrupts to be serviced. When a high-priority
request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority
level can be serviced. In this way, the high- and low-priority requests can be serviced in parallel (see Figure 7-4).

Table 7-2. IS1 and IS0 Bit Manipulation for Multi-Level Interrupt Handling

Process Status

Before INT

Effect of Isx Bit Setting

After INT ACK

IS1

IS0

IS1

IS0

0

0

0

All interrupt requests are serviced.

0

1

1

0

1

Only high-priority interrupts as determined by the
current settings in the IPR register are serviced.

1

0

2

1

0

No additional interrupt requests will be serviced.

–

–

–

1

1

Value undefined

–

–

INT Disable

SET IPR

INT Enable

Low or High

Level

Interrupt

Generated

Normal Program

Processing

(Status 0)

Low or High

Level Interrupt

Generated

Single

Interrupt

2-Level

Interrupt

Status 1

INT Enable

Modify Status

High-Level

Interrupt

Generated

3-Level

Interrupt

Status 0

Status 2

INT Disable

Status  0

Status 1

Figure 7-4. Multi-Level Interrupt Handling

Summary of Contents for C2316

Page 1: ...cations that require LCD functions Up to 40 pins of the 80 pin QFP package can be dedicated to I O Six vectored interrupts provide fast response to internal and external events In addition the KS57C2308 C2316 s advanced CMOS technology provides for low power consumption and a wide operating voltage range OTP The KS57C2308 C2316 microcontroller is also available in OTP One Time Programmable version...

Page 2: ...LCD 8 Bit Serial I O Interface 8 bit transmit receive mode 8 bit receive only mode LSB first or MSB first transmission selectable Internal or external clock source Bit Sequential Carrier Support 16 bit serial data transfer in arbitrary format Interrupts Three internal vectored interrupts Three external vectored interrupts Two quasi interrupts Memory Mapped I O Structure Data memory bank 15 Two Pow...

Page 3: ...BIAS VLC0 VLC2 LCDCK P3 0 LCDSY P3 1 COM0 COM3 SEG0 SEG23 P8 0 P8 7 SEG24 SEG31 P2 3 BUZ XOUT XTOUT P6 0 P6 3 KS0 KS3 I O Port 6 P7 0 P7 3 KS4 KS7 I O Port 7 P4 0 P4 3 I O Port 3 P5 0 P5 3 I O Port 4 8 Bit Timer Counter 0 P1 3 TCL0 P2 0 TCLO0 P8 0 P8 7 SEG24 SEG31 I O Port 8 P1 0 INT0 P1 1 INT1 P1 2 INT2 P1 3 TCL0 Input Port 1 P2 0 TCLO0 P2 1 P2 2 CLO P2 3 BUZ I O Port 2 Basic Timer 4 Bit Accumula...

Page 4: ...2 71 70 69 68 67 66 65 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 KS57C2308 KS57C2316 TOP VIEW SEG2 SEG1 SEG0 COM0 COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2 VDD VSS XOUT XIN TEST XTIN XTOUT RESET P0 0 INT4 P0 1 SCK P0 2 SO P0 3 SI P1 0 INT0 P1 1 INT1 P1 2 INT2 P1 3 TCL0 P2 0 TCLO0 P2 1 P2 2 CLO P2 3 BUZ P3 0 LCDCK P3 1 SCDSY P3 2 P3 3 P4...

Page 5: ...istors are software assignable 32 33 34 35 LCDCK LCDSY Input D P4 0 P4 3 P5 0 P5 3 I O 4 bit I O ports N channel open drain output up to 5 V 1 4 and 8 bit read write and test are possible Ports 4 and 5 can be paired to support 8 bit data transfer 4 bit pull up resistors are software assignable 36 43 Input E P6 0 P6 3 P7 0 P7 3 I O 4 bit I O ports Port 6 pins are individually software configurable ...

Page 6: ...ing edge signals 26 P1 2 Input A 1 INT4 I External interrupt input with detection of rising or falling edge 20 P0 0 Input A 1 KS0 KS7 I O Quasi interrupt inputs with falling edge detection 44 51 P6 0 P7 3 Input D CLO I O CPU clock output 30 P2 2 Input D BUZ I O 2 4 8 or 16 kHz frequency output for buzzer sound with 4 19 MHz main system clock or 32 768 kHz subsystem clock 31 P2 3 Input D XIN XOUT C...

Page 7: ... TRIGGER VDD IN P CHANNEL PULL UP RESISTOR RESISTOR ENABLE Figure 1 4 Pin Circuit Type A 1 P1 P0 0 P0 3 VDD P CHANNEL DATA OUTPUT DISABLE N CHANNEL OUT Figure 1 5 Pin Circuit Type C P CHANNEL PULL UP RESISTOR RESISTOR ENABLE DATA OUTPUT DISABLE CIRCUIT TYPE A I O VDD CIRCUIT TYPE C Figure 1 6 Pin Circuit Type D P0 1 P0 2 P2 P3 P6 P7 ...

Page 8: ...L UP RESISTOR I O CIRCUIT TYPE A VDD PNE Figure 1 7 Pin Circuit Type E P4 P5 VLC0 VLC1 LCD SEGMENT COMMON DATA VLC2 OUT Figure 1 8 Pin Circuit Type H 15 SEG COM VLC0 VLC1 LCD SEGMENT PORT 8 DATA VLC2 VDD OUT Figure 1 9 Pin Circuit Type H 16 P8 IN SCHMITT TRIGGER VDD Figure 1 10 Pin Circuit Type B RESET ...

Page 9: ...is used to store the vector addresses required to execute system resets and interrupts Start addresses for interrupt service routines are stored in this area along with the values of the enable memory bank EMB and enable register bank ERB flags that are used to set their initial value for the corresponding service routines The 16 byte area can be used alternately as general purpose ROM REF Instruc...

Page 10: ...esses of interrupt service routines are stored in this area along with the enable memory bank EMB and enable register bank ERB flag values that are needed to initialize the service routines 12 byte vector addresses are organized as follows NOTE PC13 is used for KS57C2316 P2316 microcontroller To set up the vector address area for specific programs use the instruction VENTn The programming tips on ...

Page 11: ...0 RESET EMB 1 ERB 0 Jump to RESET address by RESET VENT1 0 0 INTB EMB 0 ERB 0 Jump to INTB address by INTB ORG 0006H INT0 interrupt not used VENT3 0 0 INT1 EMB 0 ERB 0 Jump to INT1 address by INT1 VENT4 0 0 INTS EMB 0 ERB 0 Jump to INTS address by INTS ORG 000CH INTT0 interrupt not used ORG 0010H 3 If an INT0 interrupt is not used and if its corresponding vector interrupt area is not fully utilize...

Page 12: ... using REF instructions you can execute instructions larger than one byte In summary there are three ways you can use the REF instruction Using the 1 byte REF instruction to execute one 2 byte or two 1 byte instructions Branching to any location by referencing a branch instruction stored in the look up table Calling subroutines at any location by referencing a call instruction stored in the look u...

Page 13: ...ect the bank you want to select as working data memory Data stored in RAM locations are 1 4 and 8 bit addressable One exception is the LCD data register area which is 1 bit and 4 bit addressable only Initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following power RESET However when RESET signal is generated in power d...

Page 14: ...k 15 With indirect addressing only bank 0 000H 0FFH can be accessed When the EMB flag is set to logic one all three data memory banks can be accessed according to the current SMB value For 8 bit addressing two 4 bit registers are addressed as a register pair Also when using 8 bit instructions to address RAM locations remember to use the even numbered register address as the instruction operand Wor...

Page 15: ...ck and general purpose registers 100H 1DFH General purpose registers 1 1 1 1E0H 1FFH LCD Data registers F80H FFFH I O mapped hardware registers 15 0 1 15 PROGRAMMING TIP Clearing Data Memory Banks 0 and 1 Clear banks 0 and 1 of the data memory area RAMCLR SMB 1 RAM 100H 1FFH clear LD HL 00H LD A 0H RMCL1 LD HL A INCS HL JR RMCL1 SMB 0 RAM 010H 0FFH clear LD HL 10H RMCL0 LD HL A INCS HL JR RMCL0 ...

Page 16: ...ointer values used for indirect addressing Unused registers may be used as general purpose memory Working register data can be manipulated as 1 bit units 4 bit units or using paired registers as 8 bit units 000H 001H 002H 003H 004H 005H 006H 007H 00FH 010H 017H 018H 01FH 008H A E L H X W Z Y A Y REGISTER BANK 1 REGISTER BANK 2 REGISTER BANK 3 A Y A Y WORKING REGISTER BANK 0 DATA MEMORY BANK 0 Figu...

Page 17: ...sing Table 2 3 Working Register Organization and Addressing ERB Setting SRB Settings Selected Register Bank 3 2 1 0 0 0 0 Always set to bank 0 0 0 Bank 0 1 0 0 0 1 Bank 1 1 0 Bank 2 1 1 Bank 3 Paired Working Registers Each of the register banks is subdivided into eight 4 bit registers These registers named Y Z W X H L E and A can either be manipulated individually using 4 bit instructions or toget...

Page 18: ...ounters by letting you transfer a value to the L register and increment or decrement it using a single instruction C A EA 1 BIT ACCUMULATOR 4 BIT ACCUMULATOR 8 BIT ACCUMULATOR Figure 2 6 1 Bit 4 Bit and 8 Bit Accumulator Recommendation for Multiple Interrupt Processing If more than four interrupts are being processed at one time you can avoid possible loss of working register data by using the PUS...

Page 19: ...0H EA LD HL 40H INCS HL LD WX EA LD YZ EA POP EA POP EA register contents from stack POP YZ POP YZ register contents from stack POP WX POP WX register contents from stack POP HL POP HL register contents from stack POP SB POP current SMB SRB IRET The POP instructions execute alternately with the PUSH instructions If an SMB n instruction is used in an interrupt service routine a PUSH and POP SB inst...

Page 20: ...ed the stack pointer is referenced to restore the PC and PSW and the next instruction is executed The SP can address stack registers in bank 0 addresses 000H 0FFH regardless of the current value of the enable memory bank EMB flag and the select memory bank SMB flag Although general purpose register areas can be used for stack operations be careful to avoid data loss due to simultaneous use of the ...

Page 21: ...es for the enable memory bank EMB flag and the enable register bank ERB flag are also pushed to the stack Since six 4 bit stack locations are used per CALL you may nest subroutine calls up to the number of levels permitted in the stack Interrupt Routines An interrupt routine references the SP to push the contents of the PC and the program status word PSW to the stack Six 4 bit stack locations are ...

Page 22: ...tructions The end of a subroutine call is signaled by the return instruction RET or SRET The RET or SRET uses the SP to reference the six 4 bit stack locations used for the CALL and to write this data back to the PC the EMB and the ERB After the RET or SRET has executed the SP is incremented by six and points to the next free stack location IRET Instructions The end of an interrupt sequence is sig...

Page 23: ...ations the 4 bit register names BSC0 and BSC2 must be specified and the upper and lower 8 bits manipulated separately If the values of the L register are 0H at BSC0 L the address and bit location assignment is FC0H 0 If the L register content is FH at BSC0 L the address and bit location assignment is FC3H 3 Table 2 4 BSC Register Organization Name Address Bit 3 Bit 2 Bit 1 Bit 0 BSC0 FC0H BSC0 3 B...

Page 24: ...MSB LSB FB0H IS1 IS0 EMB ERB FB1H C SC2 SC1 SC0 The PSW can be manipulated by 1 bit or 4 bit read write and by 8 bit read instructions depending on the specific bit or bits being addressed The PSW can be addressed during program execution regardless of the current value of the enable memory bank EMB flag Part or all of the PSW is saved to stack prior to execution of a subroutine call or hardware i...

Page 25: ...re restored to the PSW Table 2 6 shows the effects of IS0 and IS1 flag settings Table 2 6 Interrupt Status Flag Bit Settings IS1 Value IS0 Value Status of Currently Executing Process Effect of IS0 and IS1 Settings on Interrupt Request Control 0 0 0 All interrupt requests are serviced 0 1 1 Only high priority interrupt s as determined in the interrupt priority register IPR are serviced 1 0 2 No mor...

Page 26: ...e EMB Flag to Select Memory Banks EMB flag settings for memory bank selection 1 When EMB 0 SMB 1 Non essential instruction since EMB 0 LD A 9H LD 90H A F90H A bank 15 is selected LD 34H A 034H A bank 0 is selected SMB 0 Non essential instruction since EMB 0 LD 90H A F90H A bank 15 is selected LD 34H A 034H A bank 0 is selected SMB 15 Non essential instruction since EMB 0 LD 20H A 020H A bank 0 is ...

Page 27: ...ing the correct flag status before the interrupt service routine is executed During the interrupt routine the ERB value is automatically pushed to the stack area along with the other PSW bits Afterwards it is popped back to the FB0H 0 bit location The initial ERB flag settings for each vectored interrupt are defined using VENTn instructions PROGRAMMING TIP Using the ERB Flag to Select Register Ban...

Page 28: ...bit read write instructions independent of other bits in the PSW Only the ADC and SBC instructions and the instructions listed in Table 2 7 affect the carry flag Table 2 7 Valid Carry Flag Manipulation Instructions Operation Type Instructions Carry Flag Manipulation Direct manipulation SCF Set carry flag to 1 RCF Clear carry flag to 0 reset carry flag CCF Invert carry flag value complement carry f...

Page 29: ...logic one SCF C 1 LD EA 0C3H EA 0C3H LD HL 0AAH HL 0AAH ADC EA HL EA 0C3H 0AAH 1H C 1 2 Logical AND bit 3 of address 3FH with P3 3 and output the result to P4 0 LD H 3H Set the upper four bits of the address to the H register value LDB C H 0FH 3 C bit 3 of 3FH BAND C P3 3 C C AND P3 3 LDB P4 0 C Output result from carry flag to P4 0 ...

Page 30: ...ADDRESS SPACES KS57C2308 P2308 C2316 P2316 2 22 NOTES ...

Page 31: ...nd EMB 1 apply specifically to the memory bank indicated by the SMB instruction and any restrictions to the addressable area within banks 0 1 or 15 Direct and indirect 1 bit 4 bit and 8 bit addressing methods can be used Several RAM locations are addressable at all times regardless of the current EMB flag setting Here are a few guidelines to keep in mind regarding data memory addressing When you a...

Page 32: ...ers RAM Areas Addressing Mode NOTES 1 X means don t care 2 Blank columns indicate RAM areas that are not addressable given the addressing method and enable memory bank EMB flag setting shown in the column headers EMB 1 EMB 0 SMB 0 SMB 0 SMB 1 SMB 1 07FH 080H F80H FFFH BANK 15 Peripheral Hardware Registers FB0H FBFH FC0H SMB 15 SMB 15 FF0H BANK 1 Display Registers SMB 1 SMB 1 1FFH Figure 3 1 RAM Ad...

Page 33: ...alue is automatically saved to stack and then restored when the interrupt routine has completed At the beginning of a program the initial EMB and ERB flag values for each vectored interrupt must be set by using VENT instruction The EMB and ERB can be set or reset by bit manipulation instructions BITS BITR despite the current SMB setting PROGRAMMING TIP Initializing the EMB and ERB Flags The follow...

Page 34: ...nk 15 for direct addressing For indirect addressing only locations 000H 0FFH in bank 0 are addressable regardless of SMB value To address the peripheral hardware register bank 15 using indirect addressing the EMB flag must first be set to 1 and the SMB value to 15 When a RESET occurs the EMB flag is set to the value contained in bit 7 of ROM address 0000H EMB Independent Addressing At any time sev...

Page 35: ... of ERB flag status and the SRB value that is set using the SRB n instruction The current SRB value is retained until another register is requested by program software PUSH SB and POP SB instructions are used to save and restore the contents of SRB during interrupts and subroutine calls RESET clears the 4 bit SRB value to logic zero Select Memory Bank SMB Instruction To select one of the four avai...

Page 36: ... Description EMB Flag Setting Addressable Area Memory Bank Hardware I O Mapping 000H 07FH Bank 0 DA b Direct a bit is indicated by the RAM address DA memory bank selection and a the specified bit number b 0 F80H FFFH Bank 15 All 1 bit addressable peripherals SMB 15 1 000H FFFH SMB 0 1 15 mema b Direct a bit is indicated by the addressable area mema and a the bit number b x FB0H FBFH FF0H FFFH Bank...

Page 37: ...AG EQU 34H 3 BFLAG EQU 85H 3 CFLAG EQU 0BAH 0 SMB 0 BITS AFLAG 34H 3 1 BITS BFLAG 85H 3 1 BTST CFLAG If 0BAH 0 1 skip BITS BFLAG Else if 0BAH 0 0 085H 3 1 BITS P3 0 FF3H 0 P3 0 1 1 Bit Indirect Addressing 1 If EMB 0 AFLAG EQU 34H 3 BFLAG EQU 85H 3 CFLAG EQU 0BAH 0 SMB 0 LD H 0BH H 0BH BTSTZ H CFLAG If 0BAH 0 1 0BAH 0 0 and skip BITS CFLAG Else if 0BAH 0 0 FBAH 0 1 2 If EMB 1 AFLAG EQU 34H 3 BFLAG ...

Page 38: ...i cated by the memory bank selection and register HL 0 000H 0FFH Bank 0 1 000H FFFH SMB 0 1 15 All 4 bit addressable peripherals SMB 15 WX Indirect 4 bit address indi cated by register WX x 000H 0FFH Bank 0 WL Indirect 4 bit address indi cated by register WL x 000H 0FFH Bank 0 NOTE x means don t care PROGRAMMING TIP 4 Bit Addressing Modes 4 Bit Direct Addressing 1 If EMB 0 ADATA EQU 46H BDATA EQU ...

Page 39: ...DATA EQU 46H BDATA EQU 66H SMB 1 Non essential instruction since EMB 0 LD HL BDATA LD WX ADATA COMP LD A WL A bank 0 040H 046H CPSE A HL If bank 0 060H 066H A skip SRET DECS L JR COMP RET 2 If EMB 1 compare bank 0 locations 040H 046H to bank 1 locations 160H 166H ADATA EQU 46H BDATA EQU 66H SMB 1 LD HL BDATA LD WX ADATA COMP LD A WL A bank 0 040H 046H CPSE A HL If bank 1 160H 166H A skip SRET DECS...

Page 40: ...TA EQU 46H BDATA EQU 66H SMB 1 Non essential instruction since EMB 0 LD HL BDATA LD WX ADATA TRANS LD A WL A bank 0 040H 046H XCHD A HL Bank 0 060H 066H A JR TRANS 2 If EMB 1 exchange bank 0 locations 040H 046H to bank 1 locations 160H 166H ADATA EQU 46H BDATA EQU 66H SMB 1 LD HL BDATA LD WX ADATA TRANS LD A WL A bank 0 040H 046H XCHD A HL Bank 1 160H 166H A JR TRANS ...

Page 41: ...ls 1 000H FFFH SMB 0 1 15 SMB 15 HL Indirect the 8 bit address indi cated by the memory bank selection and register HL the 4 bit L register value must be an even number 0 000H 0FFH Bank 0 1 000H FFFH SMB 0 1 15 All 8 bit addressable peripherals SMB 15 PROGRAMMING TIP 8 Bit Addressing Modes 8 Bit Direct Addressing 1 If EMB 0 ADATA EQU 46H BDATA EQU 8EH SMB 15 Non essential instruction since EMB 0 L...

Page 42: ... 12 PROGRAMMING TIP 8 Bit Addressing Modes Continued 8 Bit Indirect Addressing 1 If EMB 0 ADATA EQU 46H SMB 1 Non essential instruction since EMB 0 LD HL ADATA LD EA HL A 046H E 047H 2 If EMB 1 ADATA EQU 46H SMB 1 LD HL ADATA LD EA HL A 146H E 147H ...

Page 43: ... direct addressing regardless of the current SMB value 1 bit direct and indirect addressing can be used for specific locations in bank 15 regardless of the current EMB value I O MAP FOR HARDWARE REGISTERS Table 4 1 contains detailed information about I O mapping for peripheral hardware in bank 15 register locations F80H FFFH Use the I O map as a quick reference source when writing application prog...

Page 44: ... F8BH are not mapped F8CH LMOD 3 2 1 0 W 3 No Yes F8DH 7 6 5 4 F8EH LCON 0 2 0 0 W No Yes No Location F8FH is not mapped F90H TMOD0 3 2 0 0 W 3 No Yes F91H 0 6 5 4 F92H TOE U 2 TOE0 U 2 U 2 R W Yes No No Location F93H is not mapped F94H TCNT0 3 2 1 0 R No No Yes F95H 7 6 5 4 F96H TREF0 3 2 1 0 W No No Yes F97H 7 6 5 4 F98H WDMOD 3 2 1 0 W No No Yes F99H 7 6 5 4 F9AH WDFLAG 3 0 0 0 W Yes Yes No Loc...

Page 45: ...s Yes FC1H BSC1 3 2 1 0 FC2H BSC2 3 2 1 0 FC3H BSC3 3 2 1 0 FD0H CLMOD 3 0 1 0 W No Yes No Locations FD1H FD5H are not mapped FD6H PNE PNE4 3 PNE4 2 PNE4 1 PNE4 0 W No No Yes FD7H PNE5 3 PNE5 2 PNE4 1 PNE5 0 Locations FD8H FDBH are not mapped FDCH PUMOD PM 3 PM 2 PM 1 PM 0 W No No Yes FDDH PM 7 PM 6 PM 5 PM 4 Locations FDEH FDFH are not mapped FE0H SMOD 3 2 1 0 W 3 R W No Yes FE1H 7 6 5 0 Location...

Page 46: ...can be read or written by specific bit manipulation instructions only REGISTER DESCRIPTIONS In this section register descriptions are presented in a consistent format to familiarize you with the memory mapped I O locations in bank 15 of the RAM Figure 4 1 describes the features of the register description format Register descriptions are arranged in alphabetical order Programmers can use this sect...

Page 47: ...d only W Write only R W Read write Register and bit IDs used for bit addressing Description of the effect of specific bit Name of individual bit or related bits W 0 2 2 4 W 0 1 1 4 W 0 0 0 4 CLMOD 2 CLMOD 1 0 Associated hardware module CPU Bit 2 0 Always logic zero Enable Disable Clock Output Control Bit 0 1 Disable clock output Enable clock output Clock Source and Frequency Selection Control Bits...

Page 48: ...Bits 0 0 0 Input clock frequency Interrupt interval time wait time fxx 212 1 02 kHz 220 fxx 250 ms 0 1 1 Input clock frequency Interrupt interval time wait time fxx 29 8 18 kHz 217 fxx 31 3 ms 1 0 1 Input clock frequency Interrupt interval time wait time fxx 27 32 7 kHz 215 fxx 7 82 ms 1 1 1 Input clock frequency Interrupt interval time wait time fxx 25 131 kHz 213 fxx 1 95 ms NOTES 1 When a RESET...

Page 49: ...trol Bit 0 Disable clock output 1 Enable clock output 2 Bit 2 0 Always logic zero 1 0 Clock Source and Frequency Selection Control Bits 0 0 Select CPU clock source fx 4 fx 8 fx 64 or fxt 4 1 05 MHz 524 kHz 65 5 kHz or 8 19 kHz 0 1 Select system clock fxx 8 524 kHz 1 0 Select system clock fxx 16 262 kHz 1 1 Select system clock fxx 64 65 5 kHz NOTE fxx is the system clock given a clock frequency of ...

Page 50: ...the INT1 pin 1 Enable interrupt requests at the INT1 pin IRQ1 INT1 Interrupt Request Flag Generate INT1 interrupt This bit is set and cleared by hardware when rising or falling edge detected at INT1 pin IE0 INT0 Interrupt Enable Flag 0 Disable interrupt requests at the INT0 pin 1 Enable interrupt requests at the INT0 pin IRQ0 INT0 Interrupt Request Flag Generate INT0 interrupt This bit is set and ...

Page 51: ...2 0 Always logic zero IE2 INT2 Interrupt Enable Flag 0 Disable INT2 interrupt requests at the INT2 pin 1 Enable INT2 interrupt requests at the INT2 pin IRQ2 INT2 Interrupt Request Flag Generate INT2 quasi interrupt This bit is set and is not cleared automatically by hardware when a rising or falling edge is detected at INT2 or KS0 KS7 respectively Since INT2 is a quasi interrupt IRQ2 flag must be ...

Page 52: ...errupt requests at the INT4 pin 1 Enable interrupt requests at the INT4 pin IRQ4 INT4 Interrupt Request Flag Generate INT4 interrupt This bit is set and cleared automatically by hardware when rising or falling signal edge detected at INT4 pin IEB INTB Interrupt Enable Flag 0 Disable INTB interrupt requests 1 Enable INTB interrupt requests IRQB INTB Interrupt Request Flag Generate INTB interrupt Th...

Page 53: ...W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 3 2 Bits 3 2 0 Always logic zero IES INTS Interrupt Enable Flag 0 Disable INTS interrupt requests 1 Enable INTS interrupt requests IRQS INTS Interrupt Request Flag Generate INTS interrupt This bit is set and cleared automatically by hardware when serial data transfer completion signal received from serial I O interface ...

Page 54: ... Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 3 2 Bits 3 2 0 Always logic zero IET0 INTT0 Interrupt Enable Flag 0 Disable INTT0 interrupt requests 1 Enable INTT0 interrupt requests IRQT0 INTT0 Interrupt Request Flag Generate INTT0 interrupt This bit is set and cleared automatically by hardware when contents of TCNT0 and TREF0 registers match ...

Page 55: ...R W Bit Addressing 1 4 1 4 1 4 1 4 3 2 Bits 3 2 0 Always logic zero IEW INTW Interrupt Enable Flag 0 Disable INTW interrupt requests 1 Enable INTW interrupt requests IRQW INTW Interrupt Request Flag Generate INTW interrupt This bit is set when the timer interval is set to 0 5 seconds or 3 91 ms NOTE Since INTW is a quasi interrupt the IRQW flag must be cleared by software ...

Page 56: ...elect CPU clock as a sampling clock 1 Select sampling clock frequency of the selected system clock fxx 64 2 Bit 2 0 Always logic zero 1 0 External Interrupt Mode Control Bits 0 0 Interrupt requests are triggered by a rising signal edge 0 1 Interrupt requests are triggered by a falling signal edge 1 0 Interrupt requests are triggered by both rising and falling signal edges 1 1 Interrupt request fla...

Page 57: ...errupt 1 INT1 Mode Register FB5H Bit 3 2 1 0 Identifier 0 0 0 IMOD1 0 RESET Value 0 0 0 0 Read Write W W W W Bit Addressing 4 4 4 4 3 1 Bits 3 1 0 Always logic zero 0 External Interrupt 1 Edge Detection Control Bit 0 Rising edge detection 1 Falling edge detection ...

Page 58: ...2 0 RESET Value 0 0 0 0 Read Write W W W W Bit Addressing 4 4 4 4 3 Bits 3 0 Always logic zero 2 0 External Interrupt 2 Edge Detection Selection Bit 0 0 0 Select rising edge at INT2 pin 0 0 1 Select falling edge at KS4 KS7 0 1 0 Select falling edge at KS2 KS7 0 1 1 Select falling edge at KS0 KS7 1 Ignore selection of falling edge at KS4 KS7 ...

Page 59: ...processing 1 Enable processing for all interrupt service requests 2 0 Interrupt Priority Assignment Bits 0 0 0 Normal interrupt handling according to default priority settings 0 0 1 Process INTB and INT4 interrupts at highest priority 0 1 0 Process INT0 interrupts at highest priority 0 1 1 Process INT1 interrupts at highest priority 1 0 0 Process INTS interrupts at highest priority 1 0 1 Process I...

Page 60: ...ic zero 0 LCD Display Control Bit 0 LCD output low turns display off cut off current to dividing resistor and output port 8 latch contents 1 If LMOD 3 0 turns display off output port 8 latch contents If LMOD 3 1 COM and SEG output in display mode LCD display on NOTES 1 You can manipulate LCON 0 when you try to turn ON OFF LCD display internally If you want to control LCD ON OFF or LCD contrast ext...

Page 61: ...nd 28 31 0 1 Segment 24 27 1 bit output at P8 4 P8 7 1 0 Segment 28 31 1 bit output at P8 0 P8 3 1 1 1 bit output only at P8 0 P8 3 and P8 4 P8 7 5 4 LCD Clock LCDCK Frequency Selection Bits 0 0 fw 29 64 Hz 0 1 fw 28 128 Hz 1 0 fw 27 256 Hz 1 1 fw 26 512 Hz NOTE Assuming watch timer clock fw 32 768 kHz 3 0 Duty and Bias Selection for LCD Display 0 LCD display off 1 0 0 0 1 4 duty 1 3 bias 1 0 0 1 ...

Page 62: ...4 4 3 2 CPU Operating Mode Control Bits 0 0 Enable normal CPU operating mode 0 1 Initiate idle power down mode 1 0 Initiate stop power down mode 1 0 CPU Clock Frequency Selection Bits 0 0 If SCMOD 0 0 fx 64 if SCMOD 0 1 fxt 4 1 0 If SCMOD 0 0 fx 8 if SCMOD 0 1 fxt 4 1 1 If SCMOD 0 0 fx 4 if SCMOD 0 1 fxt 4 NOTE fx is the main system clock fxt is the subsystem clock ...

Page 63: ...ction Flag 0 Set P6 2 to input mode 1 Set P6 2 to output mode PM6 1 P6 1 I O Mode Selection Flag 0 Set P6 1 to input mode 1 Set P6 1 to output mode PM6 0 P6 0 I O Mode Selection Flag 0 Set P6 0 to input mode 1 Set P6 0 to output mode PM3 3 P3 3 I O Mode Selection Flag 0 Set P3 3 to input mode 1 Set P3 3 to output mode PM3 2 P3 2 I O Mode Selection Flag 0 Set P3 2 to input mode 1 Set P3 2 to output...

Page 64: ...essing 8 8 8 8 8 8 8 8 PM7 P7 I O Mode Selection Flag 0 Set P7 to input mode 1 Set P7 to output mode 6 Bit 6 0 Always logic zero PM5 P5 I O Mode Selection Flag 0 Set P5 to input mode 1 Set P5 to output mode PM4 P4 I O Mode Selection Flag 0 Set P4 to input mode 1 Set P4 to output mode 3 Bit 3 0 Always logic zero PM2 P2 I O Mode Selection Flag 0 Set P2 to input mode 1 Set P2 to output mode 1 0 Bits ...

Page 65: ...annel Open Drain Configurable Bit 0 Configure P5 1 as a push pull 1 Configure P5 1 as a n channel open drain PNE5 0 P5 0 N Channel Open Drain Configurable Bit 0 Configure P5 0 as a push pull 1 Configure P5 0 as a n channel open drain PNE4 3 P4 3 N Channel Open Drain Configurable Bit 0 Configure P4 3 as a push pull 1 Configure P4 3 as a n channel open drain PNE4 2 P4 2 N Channel Open Drain Configur...

Page 66: ...determined in the interrupt priority register IPR 1 0 Do not service any more interrupt requests 1 1 Undefined EMB Enable Data Memory Bank Flag 0 Restrict program access to data memory to bank 15 F80H FFFH and to the locations 000H 07FH in the bank 0 only 1 Enable full access to data memory banks 0 1 2 and 15 ERB Enable Register Bank Flag 0 Select register bank 0 as working register area 1 Select ...

Page 67: ...istor 1 Connect port 5 pull up resistor PUR4 Connect Disconnect Port 4 Pull Up Resistor Control Bit 0 Disconnect port 4 pull up resistor 1 Connect port 4 pull up resistor PUR3 Connect Disconnect Port 3 Pull Up Resistor Control Bit 0 Disconnect port 3 pull up resistor 1 Connect port 3 pull up resistor PUR2 Connect Disconnect Port 2 Pull Up Resistor Control Bit 0 Disconnect port 2 pull up resistor 1...

Page 68: ...lock Oscillation Control Bits 0 0 0 Select main system clock fx enable main system clock 0 0 1 Select sub system clock fxt enable main system clock 0 1 0 Select main system clock fx disable sub system clock 1 0 1 Select sub system clock fxt disable main system clock 1 Bit 1 0 Always logic zero NOTE SCMOD bits 3 and 0 cannot be modified simultaneously by a 4 bit instruction they can only be modifie...

Page 69: ...clock frequency if you have selected a CPU clock of fxx 64 NOTE All kHz frequency ratings assume a system clock of 4 19MHz 4 Bit 4 0 Always logic zero 3 Initiate Serial I O Operation Bit 1 Clear IRQS flag and 3 bit clock counter to logic zero then initiate serial transmission When SIO transmission starts this bit is cleared by hardware to logic zero 2 Enable Disable SIO Data Shifter and Clock Coun...

Page 70: ...nput at TCL0 pin on rising edge 0 0 1 External clock input at TCL0 pin on falling edge 1 0 0 fxx 210 4 09 kHz 1 0 1 fxx 28 16 4 kHz 1 1 0 fxx 26 65 5 kHz 1 1 1 fxx 24 262 kHz NOTE fxx Selected system clock of 4 19 MHz 3 Clear Counter and Resume Counting Control Bit 1 Clear TCNT0 IRQT0 and TOL0 and resume counting immediately This bit is cleared automatically when counting starts 2 Enable Disable T...

Page 71: ...gister F92H Bit 3 2 1 0 Identifier U TOE0 U U RESET Value 0 0 0 0 Read Write R W Bit Addressing 1 3 Bit3 U Unknown TOE0 Timer Counter 0 Output Enable Flag 0 Disable timer counter 0 output at the TCLO0 pin 1 Enable timer counter 0 output at the TCLO0 pin 1 0 Bits 1 0 U Unknown ...

Page 72: ...it 3 2 1 0 Identifier WDTCF 0 0 0 RESET Value 0 0 0 0 Read Write W W W W Bit Addressing 1 4 1 4 1 4 1 4 WDTCF Watchdog Timer Counter Clear Flag 1 Clears the watchdog timer counter 2 0 Bits 2 0 0 Always logic zero NOTE After watchdog timer is cleared by writing 1 this bit is cleared to 0 automatically ...

Page 73: ... Register F99H F98H Bit 7 6 5 4 3 2 1 0 Identifier 7 6 5 4 3 2 1 0 RESET Value 1 0 1 0 0 1 0 1 Read Write W W W W W W W W Bit Addressing 8 8 8 8 8 8 8 8 WDMOD Watchdog Timer Enable Disable Control 5AH Disable watchdog timer function Others Enable watchdog timer function ...

Page 74: ...t Level Control Bit 0 Input level to XTIN pin is low 1 bit read only addressable for test 1 Input level to XTIN pin is high 1 bit read only addressable for test 2 Enable Disable Watch Timer Bit 0 Disable watch timer and clear frequency dividing circuits 1 Enable watch timer 1 Watch Timer Speed Control Bit 0 Normal speed set IRQW to 0 5 seconds 1 High speed operation set IRQW to 3 91 ms 0 Watch Tim...

Page 75: ...h instruction Several instructions have multiple operand formats Predefined values or labels can be used as instruction operands when addressing immediate data Many of the symbols for specific registers and flags may also be substituted as labels for operations such DA mema memb b and so on Using instruction labels can greatly simplify programming and debugging tasks INSTRUCTION SET FEATURES In th...

Page 76: ...byte or two 1 byte instructions Branching to any location by referencing a branch address that is stored in the look up table Calling subroutines at any location by referencing a call address that is stored in the look up table If necessary an REF instruction can be circumvented by means of a skip operation prior to the REF in the execution sequence In addition the instruction immediately followin...

Page 77: ... A 2H Ignore redundant instruction LD A 3H Ignore redundant instruction LD 23H A Execute instruction 023H 1H If consecutive LD HL imm instructions load 8 bit immediate data to the 8 bit memory pointer pair HL are detected only the first LD is executed and the LDs which immediately follow are ignored For example LD HL 10H HL 10H LD HL 20H Ignore redundant instruction LD A 3H A 3H LD EA 35H Ignore r...

Page 78: ...FFFH H DA b All bit manipulatable peripheral hardware All bits of the memory bank specified by EMB and SMB that are bit manipulatable Instructions Which Have Skip Conditions The following instructions have a skip function when an overflow or borrow occurs XCHI INCS XCHD DECS LDI ADS LDD SBS If there is an overflow or borrow from the result of an increment or decrement a skip signal is generated an...

Page 79: ...tion is immediately followed by an ADS A im instruction the ADC or SBC skips on overflow or if there is no borrow to the instruction immediately following the ADS and program execution continues Table 5 3 contains additional information and examples of the ADC A HL and SBC A HL skip feature Table 5 3 Skip Conditions for ADC and SBC Instructions Sample Instruction Sequences If the result of instruc...

Page 80: ...word PSW Port n Pn m th bit of port n Pn m Interrupt priority register IPR Enable memory bank flag EMB Enable register bank flag ERB Table 5 6 Instruction Operand Notation Symbol Definition DA Direct address Indirect address prefix src Source operand dst Destination operand R Contents of register R b Bit location im 4 bit immediate data number imm 8 bit immediate data number Immediate data prefix ...

Page 81: ...r S is used in tables when describing the number of additional machine cycles required for an instruction to execute given that the instruction has a skip function S skip The addition number of machine cycles that will be required to perform the skip usually depends on the size of the instruction being skipped whether it is a 1 byte 2 byte or 3 byte instruction A skip is also executed for SMB and ...

Page 82: ...user s manual for the first time however you may want to scan this detailed information briefly and then return to it later on The following information is provided for each instruction Instruction name Operand s Brief operation description Number of bytes of the instruction and operand s Number of machine cycles required to execute the instruction The tables in this section are arranged according...

Page 83: ... corresponding location 2 2 Table 5 10 Program Control Instructions High Level Summary Name Operand Operation Description Bytes Cycles CPSE R im Compare and skip if register equals im 2 2 S HL im Compare and skip if indirect data memory equals im 2 2 S A R Compare and skip if A equals R 2 2 S A HL Compare and skip if A equals indirect data memory 1 1 S EA HL Compare and skip if EA equals indirect ...

Page 84: ... Load register contents to A 2 2 Ra im Load 4 bit immediate data to register 2 2 RR imm Load 8 bit immediate data to register 2 2 DA A Load contents of A to direct data memory 2 2 Ra A Load contents of A to register 2 2 EA HL Load indirect data memory contents to EA 2 2 EA DA Load direct data memory contents to EA 2 2 EA RRb Load register contents to EA 2 2 HL A Load contents of A to indirect data...

Page 85: ...with carry 1 1 EA RR Add register pair RR to EA with carry 2 2 RRb EA Add EA to register pair RRb with carry 2 2 ADS A im Add 4 bit immediate data to A and skip on carry 1 1 S EA imm Add 8 bit immediate data to EA and skip on carry 2 2 S A HL Add indirect data memory to A and skip on carry 1 1 S EA RR Add register pair RR contents to EA and skip on carry 2 2 S RRb EA Add EA to register pair RRb an...

Page 86: ... if memory bit is set memb L H DA b BITS DA b Set specified memory bit mema b memb L H DA b BITR DA b Clear specified memory bit to logic zero mema b memb L H DA b BAND C mema b Logical AND carry flag with specified memory bit C memb L C H DA b 2 2 BOR C mema b Logical OR carry with specified memory bit C memb L C H DA b BXOR C mema b Exclusive OR carry with specified memory bit C memb L C H DA b ...

Page 87: ...uctions later in Section 5 If you are reading this user s manual for the first time please just scan this very detailed information briefly Most of the general information you will need to write application programs can be found in the high level summary tables in the previous section The following information is provided for each instruction Instruction name Operand s Binary values Operation nota...

Page 88: ... 1 0 1 1 0 0 1 0 IDLE 1 1 1 1 1 1 1 1 PCON 2 1 1 0 1 0 0 0 1 1 STOP 1 1 1 1 1 1 1 1 PCON 3 1 1 0 1 1 0 0 1 1 NOP 1 0 1 0 0 0 0 0 No operation SMB n 1 1 0 1 1 1 0 1 SMB n 0 1 0 0 d3 d2 d1 d0 SRB n 1 1 0 1 1 1 0 1 SRB n n 0 1 2 3 0 1 0 1 0 0 d1 d0 REF memc t7 t6 t5 t4 t3 t2 t1 t0 PC13 0 memc5 0 memc 1 7 0 VENTn EMB 0 1 ERB 0 1 ADR E M B E R B a13 a12 a11 a10 a9 a8 ROM 2 x n 7 6 EMB ERB ROM 2 x n 5 4...

Page 89: ...1 0 1 1 0 1 1 PC13 0 ADR13 0 0 0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 JPS ADR12 1 0 0 1 a11 a10 a9 a8 PC13 0 PC13 12 ADR11 0 a7 a6 a5 a4 a3 a2 a1 a0 JR im PC13 0 ADR PC 15 to PC 16 WX 1 1 0 1 1 1 0 1 PC13 0 PC13 8 WX 0 1 1 0 0 1 0 0 EA 1 1 0 1 1 1 0 1 PC13 0 PC13 8 EA 0 1 1 0 0 0 0 0 CALL ADR14 1 1 0 1 1 0 1 1 SP 1 SP 2 EMB ERB 0 1 a13 a12 a11 a10 a9 a8 SP 3 SP 4 PC7 0 SP 5 SP 6 PC13 8 a7...

Page 90: ...Transfer Instructions Binary Code Summary Name Operand Binary Code Operation Notation XCH A DA 0 1 1 1 1 0 0 1 A DA a7 a6 a5 a4 a3 a2 a1 a0 A Ra 0 1 1 0 1 r2 r1 r0 A Ra A RRa 0 1 1 1 1 i2 i1 i0 A RRa EA DA 1 1 0 0 1 1 1 1 A DA E DA 1 a7 a6 a5 a4 a3 a2 a1 a0 EA RRb 1 1 0 1 1 1 0 0 EA RRb 1 1 1 0 0 r2 r1 0 EA HL 1 1 0 1 1 1 0 0 A HL E HL 1 0 0 0 0 0 0 0 1 XCHI A HL 0 1 1 1 1 0 1 0 A HL then L L 1 sk...

Page 91: ...DA 1 1 0 0 1 1 1 0 A DA E DA 1 a7 a6 a5 a4 a3 a2 a1 a0 EA RRb 1 1 0 1 1 1 0 0 EA RRb 1 1 1 1 1 r2 r1 0 HL A 1 1 0 0 0 1 0 0 HL A DA EA 1 1 0 0 1 1 0 1 DA A DA 1 E a7 a6 a5 a4 a3 a2 a1 a0 RRb EA 1 1 0 1 1 1 0 0 RRb EA 1 1 1 1 0 r2 r1 0 HL EA 1 1 0 1 1 1 0 0 HL A HL 1 E 0 0 0 0 0 0 0 0 LDI A HL 1 0 0 0 1 0 1 0 A HL then L L 1 skip if L 0H LDD A HL 1 0 0 0 1 0 1 1 A HL then L L 1 skip if L 0FH LDC EA...

Page 92: ... AND im 0 0 0 1 d3 d2 d1 d0 A HL 0 0 1 1 1 0 0 1 A A AND HL EA RR 1 1 0 1 1 1 0 0 EA EA AND RR 0 0 0 1 1 r2 r1 0 RRb EA 1 1 0 1 1 1 0 0 RRb RRb AND EA 0 0 0 1 0 r2 r1 0 OR A im 1 1 0 1 1 1 0 1 A A OR im 0 0 1 0 d3 d2 d1 d0 A HL 0 0 1 1 1 0 1 0 A A OR HL EA RR 1 1 0 1 1 1 0 0 EA EA OR RR 0 0 1 0 1 r2 r1 0 RRb EA 1 1 0 1 1 1 0 0 RRb RRb OR EA 0 0 1 0 0 r2 r1 0 XOR A im 1 1 0 1 1 1 0 1 A A XOR im 0 0...

Page 93: ... r2 r1 0 RRb EA 1 1 0 1 1 1 0 0 RRb RRb EA skip on carry 1 0 0 1 0 r2 r1 0 SBC A HL 0 0 1 1 1 1 0 0 C A A HL C EA RR 1 1 0 1 1 1 0 0 C EA EA RR C 1 1 0 0 1 r2 r1 0 RRb EA 1 1 0 1 1 1 0 0 C RRb RRb EA C 1 1 0 0 0 r2 r1 0 SBS A HL 0 0 1 1 1 1 0 1 A A HL skip on borrow EA RR 1 1 0 1 1 1 0 0 EA EA RR skip on borrow 1 0 1 1 1 r2 r1 0 RRb EA 1 1 0 1 1 1 0 0 RRb RRb EA skip on borrow 1 0 1 1 0 r2 r1 0 DE...

Page 94: ... 0 0 1 0 Skip if DA b 0 a7 a6 a5 a4 a3 a2 a1 a0 mema b 1 1 1 1 1 0 0 0 Skip if mema b 0 memb L 1 1 1 1 1 0 0 0 Skip if memb 7 2 L 3 2 L 1 0 0 0 1 0 0 a5 a4 a3 a2 H DA b 1 1 1 1 1 0 0 0 Skip if H DA 3 0 b 0 0 0 b1 b0 a3 a2 a1 a0 BTSTZ mema b 1 1 1 1 1 1 0 1 Skip if mema b 1 and clear memb L 1 1 1 1 1 1 0 1 Skip if memb 7 2 L 3 2 L 1 0 1 and clear 0 1 0 0 a5 a4 a3 a2 H DA b 1 1 1 1 1 1 0 1 Skip if H...

Page 95: ... C AND mema b C memb L 1 1 1 1 0 1 0 1 C C AND memb 7 2 L 3 2 L 1 0 0 1 0 0 a5 a4 a3 a2 C H DA b 1 1 1 1 0 1 0 1 C C AND H DA 3 0 b 0 0 b1 b0 a3 a2 a1 a0 BOR C mema b 1 1 1 1 0 1 1 0 C C OR mema b C memb L 1 1 1 1 0 1 1 0 C C OR memb 7 2 L 3 2 L 1 0 0 1 0 0 a5 a4 a3 a2 C H DA b 1 1 1 1 0 1 1 0 C C OR H DA 3 0 b 0 0 b1 b0 a3 a2 a1 a0 BXOR C mema b 1 1 1 1 0 1 1 1 C C XOR mema b C memb L 1 1 1 1 0 1...

Page 96: ... 0 mema b C memb L C 1 1 1 1 1 1 0 0 memb 7 2 L 3 2 L 1 0 C 0 1 0 0 a5 a4 a3 a2 H DA b C 1 1 1 1 1 1 0 0 H DA 3 0 b C 0 0 b1 b0 a3 a2 a1 a0 C mema b 1 1 1 1 0 1 0 0 C mema b C memb L 1 1 1 1 0 1 0 0 C memb 7 2 L 3 2 L 1 0 0 1 0 0 a5 a4 a3 a2 C H DA b 1 1 1 1 0 1 0 0 C H DA 3 0 b 0 0 b1 b0 a3 a2 a1 a0 Second Byte Bit Addresses mema b 1 0 b1 b0 a3 a2 a1 a0 FB0H FBFH 1 1 b1 b0 a3 a2 a1 a0 FF0H FFFH ...

Page 97: ...s user s manual for the first time please just scan this very detailed information briefly in order to acquaint yourself with the basic features of the instruction set The information elements of the instruction description format are as follows Instruction name mnemonic Full instruction name Source destination format of the instruction operand Operation overview from the High Level Summary table ...

Page 98: ...rogram ADC skips the ADS instruction if an overflow occurs If there is no overflow the ADS instruction is executed normally This condition is valid only for ADC A HL instructions If an overflow occurs following an ADS A im instruction the next instruction will not be skipped Operand Binary Code Operation Notation A HL 0 0 1 1 1 1 1 0 C A A HL C EA RR 1 1 0 1 1 1 0 0 C EA EA RR C 1 0 1 0 1 r2 r1 0 ...

Page 99: ...tment operations a 8 9 decimal addition the contents of the address specified by the HL register is 9H RCF C 0 LD A 8H A 8H ADS A 6H A 8H 6H 0EH ADC A HL A 0EH 9H C 0 7H C 1 ADS A 0AH Skip this instruction because C 1 after ADC result JPS XXX b 3 4 decimal addition the contents of the address specified by the HL register is 4H RCF C 0 LD A 3H A 3H ADS A 6H A 3H 6H 9H ADC A HL A 9H 4H C 0 0DH ADS A...

Page 100: ... unaffected If ADS A im follows an ADC A HL instruction in a program ADC skips the ADS instruction if an overflow occurs If there is no overflow the ADS instruction is executed normally This skip condition is valid only for ADC A HL instructions however If an overflow occurs following an ADS instruction the next instruction is not skipped Operand Binary Code Operation Notation A im 1 0 1 0 d3 d2 d...

Page 101: ...r the ADC A HL does not skip even if overflow occurs This function is useful for decimal adjustment operations a 8 9 decimal addition the contents of the address specified by the HL register is 9H RCF C 0 LD A 8H A 8H ADS A 6H A 8H 6H 0EH ADC A HL A 0EH 9H C 0 7H C 1 ADS A 0AH Skip this instruction because C 1 after ADC result JPS XXX b 3 4 decimal addition the contents of the address specified by...

Page 102: ...he destination The logical AND operation results in 1 whenever the corresponding bits in the two operands are both 1 otherwise a 0 bit is stored The contents of the source are unaffected Operand Binary Code Operation Notation A im 1 1 0 1 1 1 0 1 A A AND im 0 0 0 1 d3 d2 d1 d0 A HL 0 0 1 1 1 0 0 1 A A AND HL EA RR 1 1 0 1 1 1 0 0 EA EA AND RR 0 0 0 1 1 r2 r1 0 RRb EA 1 1 0 1 1 1 0 0 RRb RRb AND EA...

Page 103: ...0 1 C C AND mema b C memb L 1 1 1 1 0 1 0 1 C C AND memb 7 2 L 3 2 L 1 0 0 1 0 0 a5 a4 a3 a2 C H DA b 1 1 1 1 0 1 0 1 C C AND H DA 3 0 b 0 0 b1 b0 a3 a2 a1 a0 Second Byte Bit Addresses mema b 1 0 b1 b0 a3 a2 a1 a0 FB0H FBFH 1 1 b1 b0 a3 a2 a1 a0 FF0H FFFH Examples 1 The following instructions set the carry flag if P1 0 port 1 0 is equal to 1 and assuming the carry flag is already set to 1 SMB 15 C...

Page 104: ...D Continued Examples 3 Register H contains the value 2H and FLAG 20H 3 The address of H is 0010B and FLAG 3 0 is 0000B The resulting address is 00100000B or 20H The bit value for the BAND instruction is 3 Therefore H FLAG 20H 3 FLAG EQU 20H 3 LD H 2H BAND C H FLAG C AND FLAG 20H 3 ...

Page 105: ...nary Code Operation Notation DA b 1 1 b1 b0 0 0 0 0 DA b 0 a7 a6 a5 a4 a3 a2 a1 a0 mema b 1 1 1 1 1 1 1 0 mema b 0 memb L 1 1 1 1 1 1 1 0 memb 7 2 L3 2 L 1 0 0 0 1 0 0 a5 a4 a3 a2 H DA b 1 1 1 1 1 1 1 0 H DA 3 0 b 0 0 0 b1 b0 a3 a2 a1 a0 Second Byte Bit Addresses mema b 1 0 b1 b0 a3 a2 a1 a0 FB0H FBFH 1 1 b1 b0 a3 a2 a1 a0 FF1H FF9H Examples 1 If the bit location 30H 2 in the RAM has a current val...

Page 106: ...B 10B 10B 0F2H 2 INCS L JR BP2 4 If bank 0 location 0A0H 0 is cleared and regardless of whether the EMB value is logic zero BITR has the following effect FLAG EQU 0A0H 0 BITR EMB LD H 0AH BITR H FLAG Bank 0 AH 0H 0 0A0H 0 0 NOTE Since the BITR instruction is used for output functions the pin names used in the examples above may change for different devices in the SAM47 product family ...

Page 107: ...sing modes Operand Binary Code Operation Notation DA b 1 1 b1 b0 0 0 0 1 DA b 1 a7 a6 a5 a4 a3 a2 a1 a0 mema b 1 1 1 1 1 1 1 1 mema b 1 memb L 1 1 1 1 1 1 1 1 memb 7 2 L 3 2 b L 1 0 1 0 1 0 0 a5 a4 a3 a2 H DA b 1 1 1 1 1 1 1 1 H DA 3 0 b 1 0 0 b1 b0 a3 a2 a1 a0 Second Byte Bit Addresses mema b 1 0 b1 b0 a3 a2 a1 a0 FB0H FBFH 1 1 b1 b0 a3 a2 a1 a0 FF0H FFFH Examples 1 If the bit location 30H 2 in t...

Page 108: ...t P1 0AH P2 2 111100B 10B 10B 0F2H 2 INCS L JR BP2 4 If bank 0 location 0A0H 0 is set to 1 and the EMB 0 BITS has the following effect FLAG EQU 0A0H 0 BITR EMB LD H 0AH BITS H FLAG Bank 0 AH 0H 0 0A0H 0 1 NOTE Since the BITS instruction is used for output functions pin names used in the examples above may change for different devices in the SAM47 product family ...

Page 109: ... C C OR memb 7 2 L 3 2 L 1 0 0 1 0 0 a5 a4 a3 a2 C H DA b 1 1 1 1 0 1 1 0 C C OR H DA 3 0 b 0 0 b1 b0 a3 a2 a1 a0 Second Byte Bit Addresses mema b 1 0 b1 b0 a3 a2 a1 a0 FB0H FBFH 1 1 b1 b0 a3 a2 a1 a0 FF0H FFFH Examples 1 The carry flag is logically ORed with the P1 0 value RCF C 0 BOR C P1 0 If P1 0 1 then C 1 if P1 0 0 then C 0 2 The P1 address is FF1H and register L contains the value 9H 1001B ...

Page 110: ...R Continued Examples 3 Register H contains the value 2H and FLAG 20H 3 The address of H is 0010B and FLAG 3 0 is 0000B The resulting address is 00100000B or 20H The bit value for the BOR instruction is 3 Therefore H FLAG 20H 3 FLAG EQU 20H 3 LD H 2H BOR C H FLAG C OR FLAG 20H 3 ...

Page 111: ...Operation Notation DA b 1 1 b1 b0 0 0 1 0 Skip if DA b 0 a7 a6 a5 a4 a3 a2 a1 a0 mema b 1 1 1 1 1 0 0 0 Skip if mema b 0 memb L 1 1 1 1 1 0 0 0 Skip if memb 7 2 L 3 2 L 1 0 0 0 1 0 0 a5 a4 a3 a2 H DA b 1 1 1 1 1 0 0 0 Skip if H DA 3 0 b 0 0 0 b1 b0 a3 a2 a1 a0 Second Byte Bit Addresses mema b 1 0 b1 b0 a3 a2 a1 a0 FB0H FBFH 1 1 b1 b0 a3 a2 a1 a0 FF0H FFFH Examples 1 If RAM bit location 30H 2 is se...

Page 112: ... 3 P2 2 P2 3 and P3 0 P3 3 are tested LD L 0AH BP2 BTSF P1 L First P1 0AH P2 2 111100B 10B 10B 0F2H 2 RET INCS L JR BP2 4 Bank 0 location 0A0H 0 is tested and regardless of the current EMB value BTSF has the following effect FLAG EQU 0A0H 0 BITR EMB LD H 0AH BTSF H FLAG If bank 0 AH 0H 0 0A0H 0 0 then skip RET ...

Page 113: ...llowing the BTST instruction is executed The destination bit value is not affected Operand Binary Code Operation Notation C 1 1 0 1 0 1 1 1 Skip if C 1 DA b 1 1 b1 b0 0 0 1 1 Skip if DA b 1 a7 a6 a5 a4 a3 a2 a1 a0 mema b 1 1 1 1 1 0 0 1 Skip if mema b 1 memb L 1 1 1 1 1 0 0 1 Skip if memb 7 2 L 3 2 L 1 0 1 0 1 0 0 a5 a4 a3 a2 H DA b 1 1 1 1 1 0 0 1 Skip if H DA 3 0 b 1 0 0 b1 b0 a3 a2 a1 a0 Second...

Page 114: ... BTST P2 0 If P2 0 1 then skip RET If P2 0 0 then return JP LABEL3 3 P2 2 P2 3 and P3 0 P3 3 are tested LD L 0AH BP2 BTST P1 L First P1 0AH P2 2 111100B 10B 10B 0F2H 2 RET INCS L JR BP2 4 Bank 0 location 0A0H 0 is tested and regardless of the current EMB value BTST has the following effect FLAG EQU 0A0H 0 BITR EMB LD H 0AH BTST H FLAG If bank 0 AH 0H 0 0A0H 0 1 then skip RET ...

Page 115: ... destination bit value is cleared Operand Binary Code Operation Notation mema b 1 1 1 1 1 1 0 1 Skip if mema b 1 and clear memb L 1 1 1 1 1 1 0 1 Skip if memb 7 2 L 3 2 L 1 0 1 and clear 0 1 0 0 a5 a4 a3 a2 H DA b 1 1 1 1 1 1 0 1 Skip if H DA 3 0 b 1 and clear 0 0 b1 b0 a3 a2 a1 a0 Second Byte Bit Addresses mema b 1 0 b1 b0 a3 a2 a1 a0 FB0H FBFH 1 1 b1 b0 a3 a2 a1 a0 FF0H FFFH Examples 1 Port pin ...

Page 116: ...316 5 42 BTSTZ Bit Test and Skip on True Clear Bit BTSTZ Continued Examples 3 Bank 0 location 0A0H 0 is tested and EMB 0 FLAG EQU 0A0H 0 BITR EMB LD H 0AH BTSTZ H FLAG If bank 0 AH 0H 0 0A0H 0 1 clear and skip BITS H FLAG If 0A0H 0 0 then 0A0H 0 1 ...

Page 117: ...1 1 1 0 1 1 1 C C XOR memb 7 2 L 3 2 L 1 0 0 1 0 0 a5 a4 a3 a2 C H DA b 1 1 1 1 0 1 1 1 C C XOR H DA 3 0 b 0 0 b1 b0 a3 a2 a1 a0 Second Byte Bit Addresses mema b 1 0 b1 b0 a3 a2 a1 a0 FB0H FBFH 1 1 b1 b0 a3 a2 a1 a0 FF0H FFFH Examples 1 The carry flag is logically XORed with the P1 0 value RCF C 0 BXOR C P1 0 If P1 0 1 then C 1 if P1 0 0 then C 0 2 The P1 address is FF1H and register L contains th...

Page 118: ...OR Continued Examples 3 Register H contains the value 2H and FLAG 20H 3 The address of H is 0010B and FLAG 3 0 is 0000B The resulting address is 00100000B or 20H The bit value for the BOR instruction is 3 Therefore H FLAG 20H 3 FLAG EQU 20H 3 LD H 2H BXOR C H FLAG C XOR FLAG 20H 3 ...

Page 119: ...ubroutine may therefore begin anywhere in the full 16 Kbyte program memory address space Operand Binary Code Operation Notation ADR14 1 1 0 1 1 0 1 1 SP 1 SP 2 EMB ERB 0 1 a13 a12 a11 a10 a9 a8 SP 3 SP 4 PC7 0 SP 5 SP 6 PC13 8 a7 a6 a5 a4 a3 a2 a1 a0 PC13 0 ADR13 0 SP SP 6 Example The stack pointer value is 00H and the label PLAY is assigned to program memory location 0E3FH Executing the instructi...

Page 120: ...cleared The subroutine call must therefore be located within the 2 Kbyte block 0000H 07FFH of program memory Operand Binary Code Operation Notation ADR11 1 1 1 0 1 a10 a9 a8 SP 1 SP 2 EMB ERB SP 3 SP 4 PC7 0 SP 5 SP 6 PC10 8 a7 a6 a5 a4 a3 a2 a1 a0 PC13 11 00 PC10 0 ADR10 0 SP SP 6 Example The stack pointer value is 00H and the label PLAY is assigned to program memory location 0345H Executing the ...

Page 121: ...erand Operation Summary Bytes Cycles Complement carry flag 1 1 Description The carry flag is complemented if C 1 it is changed to C 0 and vice versa Operand Binary Code Operation Notation 1 1 0 1 0 1 1 0 C C Example If the carry flag is logic zero the instruction CCF changes the value to logic one ...

Page 122: ... Complement accumulator A 2 2 Description The accumulator value is complemented if the bit value of A is 1 it is changed to 0 and vice versa Operand Binary Code Operation Notation A 1 1 0 1 1 1 0 1 A A 0 0 1 1 1 1 1 1 Example If the accumulator contains the value 4H 0100B the instruction COM A leaves the value 0BH 1011B in the accumulator ...

Page 123: ...rom the destination operand and skips the next instruction if the values are equal Neither operand is affected by the comparison Operand Binary Code Operation Notation R im 1 1 0 1 1 0 0 1 Skip if R im d3 d2 d1 d0 0 r2 r1 r0 HL im 1 1 0 1 1 1 0 1 Skip if HL im 0 1 1 1 d3 d2 d1 d0 A R 1 1 0 1 1 1 0 1 Skip if A R 0 1 1 0 1 r2 r1 r0 A HL 0 0 1 1 1 0 0 0 Skip if A HL EA HL 1 1 0 1 1 1 0 0 Skip if A HL...

Page 124: ...The carry flag value is unaffected Operand Binary Code Operation Notation R 0 1 0 0 1 r2 r1 r0 R R 1 skip on borrow RR 1 1 0 1 1 1 0 0 RR RR 1 skip on borrow 1 1 0 1 1 r2 r1 0 Examples 1 Register pair HL contains the value 7FH 01111111B The following instruction leaves the value 7EH in register pair HL DECS HL 2 Register A contains the value 0H The following instruction sequence leaves the value 0...

Page 125: ...er IPR IME is cleared to logic zero disabling all interrupts Interrupts can still set their respective interrupt status latches but the CPU will not directly service them Operand Binary Code Operation Notation 1 1 1 1 1 1 1 0 IME 0 1 0 1 1 0 0 1 0 Example If the IME bit bit 3 of the IPR is logic one e g all instructions are enabled the instruction DI sets the IME bit to logic zero disabling all in...

Page 126: ... one This allows all interrupts to be serviced when they occur assuming they are enabled If an interrupt s status latch was previously enabled by an interrupt this interrupt can also be serviced Operand Binary Code Operation Notation 1 1 1 1 1 1 1 1 IM 1 1 0 1 1 0 0 1 0 Example If the IME bit bit 3 of the IPR is logic zero e g all instructions are disabled the instruction EI sets the IME bit to lo...

Page 127: ...lowed by at least three NOP instructions This ensures an adequate time interval for the clock to stabilize before the next instruction is executed If more than three NOP instructions are not used after IDLE instruction leakage current could be flown because of the floating state in the internal bus Operand Binary Code Operation Notation 1 1 1 1 1 1 1 1 PCON 2 1 1 0 1 0 0 0 1 1 Example The instruct...

Page 128: ...rflow to 00H If a carry occurs the next instruction is skipped The carry flag value is unaffected Operand Binary Code Operation Notation R 0 1 0 1 1 r2 r1 r0 R R 1 skip on carry DA 1 1 0 0 1 0 1 0 DA DA 1 skip on carry a7 a6 a5 a4 a3 a2 a1 a0 HL 1 1 0 1 1 1 0 1 HL HL 1 skip on carry 0 1 1 0 0 0 1 0 RRb 1 0 0 0 0 r2 r1 0 RRb RRb 1 skip on carry Example Register pair HL contains the value 7EH 011111...

Page 129: ...before the pending interrupt is processed Since the a14 bit of an interrupt return address is not stored in the stack this bit location is always interpreted as a logic zero The starting address in the ROM must for this reason be located in 0000H 3FFFH Operand Binary Code Operation Notation 1 1 0 1 0 1 0 1 PC13 8 SP 1 SP PC7 0 SP 2 SP 3 PSW SP 4 SP 5 SP SP 6 Example The stack pointer contains the ...

Page 130: ... of the program counter with the address specified in the destination operand The destination can be anywhere in the 16 K byte program memory address space Operand Binary Code Operation Notation ADR14 1 1 0 1 1 0 1 1 PC13 0 ADR13 0 0 0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 Example The label SYSCON is assigned to the instruction at program location 07FFH The instruction JP SYSCON at locatio...

Page 131: ...Binary Code Operation Notation ADR12 1 0 0 1 a11 a10 a9 a8 PC13 12 PC13 12 a7 a6 a5 a4 a3 a2 a1 a0 PC11 0 ADR11 0 Example The label SUB is assigned to the instruction at program memory location 00FFH The instruction JPS SUB at location 0EABH will load the program counter with the value 00FFH Normally the JPS instruction jumps to the address in the block in which the instruction is located If the f...

Page 132: ...16 and the range is from 1 to 15 If a 0 1 or any other number that is outside these ranges are used the assembler interprets it as an error For JR WX and JR EA branch relative instructions the valid range for the relative address is 0H 0FFH The destination address for these jumps can be specified to the assembler by a label that lies anywhere within the current 256 byte block Normally the JR WX an...

Page 133: ...nd JPS CCC would be executed If LD EA 03H were to be executed the jump would be to1006H and JPS DDD would be executed ORG 1000H JPS AAA JPS BBB JPS CCC JPS DDD LD WX 00H WX 00H LD EA WX ADS WX EA WX WX WX JR WX Current PC13 8 10H WX 00H 1000H Jump to address 1000H and execute JPS AAA 3 Here is another example ORG 1100H LD A 0H LD A 1H LD A 2H LD A 3H LD 30H A Address 30H A JPS YYY XXX LD EA 00H EA...

Page 134: ...Load contents of A to indirect data memory 1 1 DA EA Load contents of EA to data memory 2 2 RRb EA Load contents of EA to register 2 2 HL EA Load contents of EA to indirect data memory 2 2 Description The contents of the source are loaded into the destination The source s contents are unaffected If an instruction such as LD A im LD EA imm or LD HL imm is written more than two times in succession o...

Page 135: ... a2 a1 a0 EA RRb 1 1 0 1 1 1 0 0 EA RRb 1 1 1 1 1 r2 r1 0 HL A 1 1 0 0 0 1 0 0 HL A DA EA 1 1 0 0 1 1 0 1 DA A DA 1 E a7 a6 a5 a4 a3 a2 a1 a0 RRb EA 1 1 0 1 1 1 0 0 RRb EA 1 1 1 1 0 r2 r1 0 HL EA 1 1 0 1 1 1 0 0 HL A HL 1 E 0 0 0 0 0 0 0 0 Examples 1 RAM location 30H contains the value 4H The RAM location values are 40H 41H and 0AH 3H respectively The following instruction sequence leaves the valu...

Page 136: ...on and Guidelines LD A im Since the redundancy effect occurs with instructions like LD EA imm if this instruction is used consecutively the second and additional instructions of the same type will be treated like NOPs LD A RRa Load the data memory contents pointed to by 8 bit RRa register pairs HL WX WL to the A register LD A DA Load direct data memory contents to the A register LD A Ra Load 4 bit...

Page 137: ... EA RRb Load 8 bit RRb register HL WX YZ to the EA register H W and Y register values are loaded into the E register and the L X and Z values into the A register LD HL A Load A register contents to data memory location pointed to by the 8 bit HL register value LD DA EA Load the A register contents to direct data memory and the E register contents to the next direct data memory location The DA valu...

Page 138: ...ond operand is copied into the location specified by the second or first operand One of the operands must be the carry flag the other may be any directly or indirectly addressable bit The source is unaffected Operand Binary Code Operation Notation mema b C 1 1 1 1 1 1 0 0 mema b C memb L C 1 1 1 1 1 1 0 0 memb 7 2 L 3 2 L 1 0 C 0 1 0 0 a5 a4 a3 a2 H DA b C 1 1 1 1 1 1 0 0 H DA 3 0 b C 0 0 b1 b0 a3...

Page 139: ...the address is 0000B The resulting address is 00100000B or 20H The bit value is 3 Therefore H FLAG 20H 3 FLAG EQU 20H 3 LD H 2H LDB C H FLAG C FLAG 20H 3 4 The following instruction sequence sets the carry flag and the loads the 1 data value to the output pin P2 0 setting it to output mode SCF C 1 LDB P2 0 C P2 0 1 5 The P1 address is FF1H and L 9H 1001B The address memb 7 2 is 111100B and L 3 2 i...

Page 140: ...it working register either WX or EA The contents of the source are unaffected Operand Binary Code Operation Notation EA WX 1 1 0 0 1 1 0 0 EA PC13 8 WX EA EA 1 1 0 0 1 0 0 0 EA PC13 8 EA Examples 1 The following instructions will load one of four values defined by the define byte DB directive to the extended accumulator LD EA 00H CALL DISPLAY JPS MAIN ORG 0500H DB 66H DB 77H DB 88H DB 99H DISPLAY ...

Page 141: ...3 Normally the LDC EA EA and the LDC EA WX instructions reference the table data on the page on which the instruction is located If however the instruction is located at address xxFFH it will reference table data on the next page In this example the upper 4 bits of the address at location 0200H is loaded into register E and the lower 4 bits into register A ORG 01FDH 01FDH LD WX 00H 01FFH LDC EA WX...

Page 142: ...creased by one If a borrow occurs e g if the resulting value in register L is 0FH the next instruction is skipped The contents of data memory and the carry flag value are not affected Operand Binary Code Operation Notation A HL 1 0 0 0 1 0 1 1 A HL then L L 1 skip if L 0FH Example In this example assume that register pair HL contains 20H and internal RAM location 20H contains the value 0FH LD HL 2...

Page 143: ...ted by one If an overflow occurs e g if the resulting value in register L is 0H the next instruction is skipped The contents of data memory and the carry flag value are not affected Operand Binary Code Operation Notation A HL 1 0 0 0 1 0 1 0 A HL then L L 1 skip if L 0H Example Assume that register pair HL contains the address 2FH and internal RAM location 2FH contains the value 0FH LD HL 2FH LDI ...

Page 144: ...ith a 1 µs cycle time five NOPs would therefore cause a 5 µs delay Program execution continues with the instruction immediately following the NOP Only the PC is affected At least three NOP instructions should follow a STOP or IDLE instruction Operand Binary Code Operation Notation 1 0 1 0 0 0 0 0 No operation Example Three NOP instructions follow the STOP instruction to provide a short interval fo...

Page 145: ...nd is logically ORed with the destination operand The result is stored in the destination The contents of the source are unaffected Operand Binary Code Operation Notation A im 1 1 0 1 1 1 0 1 A A OR im 0 0 1 0 d3 d2 d1 d0 A HL 0 0 1 1 1 0 1 0 A A OR HL EA RR 1 1 0 1 1 1 0 0 EA EA OR RR 0 0 1 0 1 r2 r1 0 RRb EA 1 1 0 1 1 1 0 0 RRb RRb OR EA 0 0 1 0 0 r2 r1 0 Example If the accumulator contains the ...

Page 146: ...s read and the SP is incremented by two The value read is then transferred to the variable indicated by the destination operand Operand Binary Code Operation Notation RR 0 0 1 0 1 r2 r1 0 RRL SP RRH SP 1 SP SP 2 SB 1 1 0 1 1 1 0 1 SRB SP SMB SP 1 SP SP 2 0 1 1 0 0 1 1 0 Example The SP value is equal to 0EDH and RAM locations 0EFH through 0EDH contain the values 2H 3H and 4H respectively The instru...

Page 147: ...cation addressed by the stack pointer thereby adding a new element to the top of the stack Operand Binary Code Operation Notation RR 0 0 1 0 1 r2 r1 1 SP 1 RRH SP 2 RRL SP SP 2 SB 1 1 0 1 1 1 0 1 SP 1 SMB SP 2 SRB SP SP 2 0 1 1 0 0 1 1 1 Example As an interrupt service routine begins the stack pointer contains the value 0FAH and the data pointer register pair HL contains the value 20H The instruct...

Page 148: ...mmary Bytes Cycles Reset carry flag to logic zero 1 1 Description The carry flag is cleared to logic zero regardless of its previous value Operand Binary Code Operation Notation 1 1 1 0 0 1 1 0 C 0 Example Assuming the carry flag is set to logic one the instruction RCF resets clears the carry flag to logic zero ...

Page 149: ...B ERB PC13 12 PC13 0 memc 5 0 memc 1 7 0 SP SP 4 When the reference area is specified by any other instruction the memc and memc 1 instructions are executed Instructions referenced by REF occupy 2 bytes of memory space for two 1 byte instructions or one 2 byte instruction and must be written as an even number from 0020H to 007FH in ROM In addition the destination address of the TJP and TCALL instr...

Page 150: ...ing example ORG 0020H AAA LD HL 00H BBB LD EA FFH CCC TCALL SUB1 DDD TJP SUB2 ORG 0080H REF AAA LD HL 00H REF BBB LD EA FFH REF CCC CALL SUB1 REF DDD JP SUB2 2 The following example shows how the REF instruction is executed in relation to LD instructions that have a redundancy effect ORG 0020H AAA LD EA 40H ORG 0100H LD EA 30H REF AAA Not skipped REF AAA LD EA 50H Skipped SRB 2 ...

Page 151: ... Symbol Instruction ORG 0020H 83 00 A1 LD HL 00H 83 03 A2 LD HL 03H 83 05 A3 LD HL 05H 83 10 A4 LD HL 10H 83 26 A5 LD HL 26H 83 08 A6 LD HL 08H 83 0F A7 LD HL 0FH 83 F0 A8 LD HL 0F0H 83 67 A9 LD HL 067H 41 0B A10 TCALL SUB1 01 0D A11 TJP SUB2 ORG 0100H 20 REF A1 LD HL 00H 21 REF A2 LD HL 03H 22 REF A3 LD HL 05H 23 REF A4 LD HL 10H 24 REF A5 LD HL 26H 25 REF A6 LD HL 08H 26 REF A7 LD HL 0FH 27 REF ...

Page 152: ...r CALLS Operand Binary Code Operation Notation 1 1 0 0 0 1 0 1 PC13 8 SP 1 SP PC7 0 SP 2 SP 3 PSW EMB ERB SP SP 6 Example The stack pointer contains the value 0FAH RAM locations 0FAH 0FBH 0FCH and and 0FDH contain 1H 0H 5H and 2H respectively The instruction RET leaves the stack pointer with the new value of 00H and program execution continues from location 0125H During a return from subroutine PC...

Page 153: ...rry flag are together rotated one bit to the right Bit 0 moves into the carry flag and the original carry value moves into the bit 3 accumulator position C 3 0 Operand Binary Code Operation Notation A 1 0 0 0 1 0 0 0 C A 0 A3 C A n 1 A n n 1 2 3 Example The accumulator contains the value 5H 0101B and the carry flag is cleared to logic zero The instruction RRC A leaves the accumulator with the valu...

Page 154: ...flag was set before the SBC instruction was executed a borrow was needed for the previous step in multiple precision subtraction In this case the carry bit is subtracted from the destination along with the source operand Operand Binary Code Operation Notation A HL 0 0 1 1 1 1 0 0 C A A HL C EA RR 1 1 0 1 1 1 0 0 C EA EA RR C 1 1 0 0 1 r2 r1 0 RRb EA 1 1 0 1 1 1 0 0 C RRb RRb EA C 1 1 0 0 0 r2 r1 0...

Page 155: ...ction is useful for decimal adjustment operations a 8 6 decimal addition the contents of the address specified by the HL register is 6H RCF C 0 LD A 8H A 8H SBC A HL A 8H 6H C 0 2H C 0 ADS A 0AH Skip this instruction because no borrow after SBC result JPS XXX b 3 4 decimal addition the contents of the address specified by the HL register is 4H RCF C 0 LD A 3H A 3H SBC A HL A 3H 4H C 0 0FH C 1 ADS ...

Page 156: ...ected Operand Binary Code Operation Notation A HL 0 0 1 1 1 1 0 1 A A HL skip on borrow EA RR 1 1 0 1 1 1 0 0 EA EA RR skip on borrow 1 0 1 1 1 r2 r1 0 RRb EA 1 1 0 1 1 1 0 0 RRb RRb EA skip on borrow 1 0 1 1 0 r2 r1 0 Examples 1 The accumulator contains the value 0C3H register pair HL contains the value 0C7H and the carry flag is cleared to logic zero RCF C 0 SBS EA HL EA 0C3H 0C7H SBS instructio...

Page 157: ...mary Bytes Cycles Set carry flag to logic one 1 1 Description The SCF instruction sets the carry flag to logic one regardless of its previous value Operand Binary Code Operation Notation 1 1 1 0 0 1 1 1 C 1 Example If the carry flag is cleared to logic zero the instruction SCF sets the carry flag to logic one ...

Page 158: ...ta memory spaces differ for various devices in the SAM47 product family the n value of the SMB instruction will also vary Addresses Register Areas Bank SMB 000H 01FH Working registers 0 0 020H 0FFH Stack and general purpose registers n00H 7FFH General purpose registers n n 1 14 n n 1 14 F80H FFFH I O mapped hardware registers 15 15 The enable memory bank EMB flag must always be set to 1 in order f...

Page 159: ...gs Selected Register Bank 3 2 1 0 0 0 0 x x Always set to bank 0 0 0 Bank 0 1 0 0 0 1 Bank 1 1 0 Bank 2 1 1 Bank 3 NOTE x not applicable The enable register bank flag ERB must always be set for the SRB instruction to execute successfully for register banks 0 1 2 and 3 In addition if the ERB value is logic zero register bank 0 is always selected regardless of the SRB value Operand Binary Code Opera...

Page 160: ...ng address and the contents of the location addressed by the stack pointer are popped into the program counter Operand Binary Code Operation Notation 1 1 1 0 0 1 0 1 PC13 8 SP 1 SP PC7 0 SP 3 SP 2 EMB ERB SP 4 SP SP 6 Example If the stack pointer contains the value 0FAH and RAM locations 0FAH 0FBH 0FCH and 0FDH contain the values 1H 0H 5H and 2H respectively the instruction SRET leaves the stack p...

Page 161: ...n adequate time interval for the clock to stabilize before the next instruction is executed If more than three NOP instructions are not used after STOP instruction leakage current could be flown because of the floating state in the internal bus Operand Binary Code Operation Notation 1 1 1 1 1 1 1 1 PCON 3 1 1 0 1 1 0 0 1 1 Example Given that bit 3 of the PCON register is cleared to logic zero and ...

Page 162: ...the vector interrupts are acknowledged Then when an interrupt is generated the EMB and ERB values of the previous routine are automatically pushed onto the stack and then popped back when the routine is completed After the return from interrupt IRET you do not need to set the EMB and ERB values again Instead use BITR and BITS to clear these values in your program routine The starting addresses for...

Page 163: ...o branch to the RESET routine labeled RESET setting EMB to 1 and ERB to 0 when RESET is activated When a basic timer interrupt is generated VENT1 causes the program to branch to the basic timer s interrupt service routine INTA and to set the EMB value to 0 and the ERB value to 1 VENT2 then branches to INTB VENT3 to INTC and so on setting the appropriate EMB and ERB values Each interrupt service ro...

Page 164: ...h the contents of the indicated destination variable and writes the original contents of the accumulator to the source Operand Binary Code Operation Notation A DA 0 1 1 1 1 0 0 1 A DA a7 a6 a5 a4 a3 a2 a1 a0 A Ra 0 1 1 0 1 r2 r1 r0 A Ra A RRa 0 1 1 1 1 i2 i1 i0 A RRa EA DA 1 1 0 0 1 1 1 1 A DA E DA 1 a7 a6 a5 a4 a3 a2 a1 a0 EA RRb 1 1 0 1 1 1 0 0 EA RRb 1 1 1 0 0 r2 r1 0 EA HL 1 1 0 1 1 1 0 0 A HL...

Page 165: ...then decrements the contents of register L If the content of register L is 0FH the next instruction is skipped The value of the carry flag is not affected Operand Binary Code Operation Notation A HL 0 1 1 1 1 0 1 1 A HL then L L 1 skip if L 0FH Example Register pair HL contains the address 20H and internal RAM location 20H contains the value 0FH LD HL 20H LD A 0H XCHD A HL A 0FH and L L 1 HL 0 JPS...

Page 166: ...pair HL and then increments the contents of register L If the content of register L is 0H a skip is executed The value of the carry flag is not affected Operand Binary Code Operation Notation A HL 0 1 1 1 1 0 1 0 A HL then L L 1 skip if L 0H Example Register pair HL contains the address 2FH and internal RAM location 2FH contains 0FH LD HL 2FH LD A 0H XCHI A HL A 0FH and L L 1 0 HL 0 JPS XXX Skippe...

Page 167: ...ogical XOR operation between the source and destination variables and stores the result in the destination The source contents are unaffected Operand Binary Code Operation Notation A im 1 1 0 1 1 1 0 1 A A XOR im 0 0 1 1 d3 d2 d1 d0 A HL 0 0 1 1 1 0 1 1 A A XOR HL EA RR 1 1 0 1 1 1 0 0 EA EA XOR RR 0 0 1 1 0 r2 r1 0 RRb EA 1 1 0 1 1 1 0 0 RRb RRb XOR EA 0 0 1 1 0 r2 r1 0 Example If the extended ac...

Page 168: ...SAM47 INSTRUCTION SET KS57C2308 P2308 C2316 P2316 5 94 NOTES ...

Page 169: ...Oscillator Circuits Interrupts Power Down RESET I O Ports Timers and Timer Counters LCD Controller Driver Electrical Data Mechanical Data KS57P2308 P2316 OTP ...

Page 170: ......

Page 171: ...heral hardware operate on the system clock frequency supplied through these circuits Specifically a clock pulse is required by the following peripheral modules LCD controller Basic timer Timer counter 0 Watch timer Clock output circuit Serial I O interface CPU Clock Notation In this document the following notation is used for descriptions of the CPU clock fx Main system clock fxt Subsystem clock f...

Page 172: ...selected and oscillation started when all SCMOD bits are cleared to logic zero By setting SCMOD 3 SCMOD 2 and SCMOD 0 to different values CPU can operate in a subsystem clock source and start or stop main or sub system clock oscillation To stop main system clock oscillation you must use the STOP instruction assuming the main system clock is selected or manipulate SCMOD 3 to 1 assuming the sub syst...

Page 173: ...Timer LCD Controller Clock Output Circuit SIO fxx CPU stop signal By IDLE or STOP instruction XIN XOUT fx Main system clock fxt Sub system clock fxx System clock Sub System Oscillator Circuit 1 4 Main System Oscillator Circuit Selector SCMOD 3 SCMOD 0 SCMOD 2 PCON 0 PCON 1 PCON 2 PCON 3 Frequency Dividing Circuit 1 8 1 4096 Selector 1 2 1 16 Oscillator Control Circuit Selector fxt fx 1 2 16 Oscill...

Page 174: ...IRCUITS XIN XOUT Figure 6 2 Crystal Ceramic Oscillator XIN XOUT Figure 6 3 External Oscillator XIN XOUT R Figure 6 4 RC Oscillator SUBSYSTEM OSCILLATOR CIRCUITS XTIN XTOUT 32 768 kHz Figure 6 5 Crystal Ceramic Oscillator XTIN XTOUT External Clock Figure 6 6 External Oscillator ...

Page 175: ...lag EMB PCON bits 1 and 0 can be written only by 4 bit RAM control instruction PCON is a write only register There are three basic choices Main system clock fx or subsystem clock fxt Divided fx clock frequency of 4 8 or 64 Divided fxt clock frequency of 4 PCON 1 and PCON 0 settings are also connected with the system clock mode control register SCMOD If SCMOD 0 0 the main system clock is always sel...

Page 176: ... varies depending on whether the main system clock fx or a subsystem clock fxt is used and on how the oscillator clock signal is divided by 4 8 or 64 Table 6 2 shows corresponding cycle times in microseconds Table 6 2 Instruction Cycle Times for CPU Clock Rates Oscillation Source Selected CPU Clock Resulting Frequency Cycle Time µs fx 4 19 MHz fx 64 65 5 kHz 15 3 fx 8 524 0 kHz 1 91 fx 4 1 05 MHz ...

Page 177: ...s 0 SCMOD 3 SCMOD 2 and SCMOD 0 bits can be manipulated by 1 bit write instructions In other words SCMOD 0 SCMOD 2 and SCMOD 3 cannot be modified simultaneously by a 4 bit write Bit 1 is always logic zero FB7H SCMOD 3 SCMOD 2 0 SCMOD 0 SCMOD A subsystem clock fxt can be selected as the system clock by manipulating the SCMOD 3 and SCMOD 0 bit settings If SCMOD 3 0 and SCMOD 0 1 the subsystem clock ...

Page 178: ...Sub oscillator runs System clock is the sub oscillation clock STOP instruction 1 Main oscillator stops CPU is in idle mode Sub oscillator still runs BToverflow and reset After the overflow of basic timer 1 256 x BT clock fxt CPU operation and main oscillation automatically start Set SCMOD 3 to 1 Main oscillator stops CPU still operates Sub oscillator still runs Set SCMOD 3 to 0 or reset Sub oscill...

Page 179: ...STOP instruction D Sub operating mode Main oscillator is stopped by SCMOD 3 Sub oscillator runs System clock is the sub oscillation clock C Sub ldle Mode Main oscillator is stopped by SCMOD 3 Sub oscillator runs System clock is the sub oscillation clock IDLE instruction D Sub Stop mode Main oscillator is stopped by SCMOD 3 Sub oscillator runs System clock is the sub oscillation clock Setting SCMOD...

Page 180: ...normal operating mode and a main system clock of fx 64 and you want to switch from the fx clock to a subsystem clock and to stop the main system clock To do this you first need to set SCMOD 0 to 1 This switches the clock from fx to fxt but allows main system clock oscillation to continue Before the switch actually goes into effect a certain number of machine cycles must elapse After this time inte...

Page 181: ...o 1 or STOP instruction when an external clock is used as the main system clock 3 When the system clock is switched to the subsystem clock it is necessary to disable any interrupts which may occur during the time intervals shown in Table 6 6 4 N A means not available 5 fx Main system clock fxt Sub system clock M C Machine Cycle When fx is 4 19 MHz and fxt is 32 768 kHz PROGRAMMING TIP Switching Be...

Page 182: ...ck source without initiating clock oscillation and disables clock output CLMOD 3 is the enable disable clock output control bit CLMOD 1 and CLMOD 0 are used to select one of four possible clock sources and frequencies normal CPU clock fxx 8 fxx 16 or fxx 64 Table 6 7 Clock Output Mode Register CLMOD Organization CLMOD Bit Settings Resulting Clock Output CLMOD 1 CLMOD 0 Clock Source Frequency 0 0 C...

Page 183: ... 64 CPU clock 4 Clock Selector CLMOD 3 CLMOD 2 CLMOD 1 CLMOD 0 P2 2 OUTPUT LATCH PM 2 Figure 6 7 CLO Output Pin Circuit Diagram CLOCK OUTPUT PROCEDURE The procedure for outputting clock pulses to the CLO pin may be summarized as follows 1 Disable clock output by clearing CLMOD 3 to logic zero 2 Set the clock output frequency CLMOD 1 CLMOD 0 3 Load 0 to the output latch of the CLO pin P2 2 4 Set th...

Page 184: ...7C2308 P2308 C2316 P2316 6 14 PROGRAMMING TIP CPU Clock Output to the CLO Pin To output the CPU clock to the CLO pin BITS EMB SMB 15 LD EA 04H LD PMG2 EA P2 Output mode BITR P2 2 Clear P2 2 pin output latch LD A 9H LD CLMOD A ...

Page 185: ...ircuit Three kinds of interrupts are supported Internal interrupts generated by on chip processes External interrupts generated by external peripheral devices Quasi interrupts used for edge detection and as clock sources Table 7 1 Interrupt Types and Corresponding Port Pin s Interrupt Type Interrupt Name Corresponding Port Pins External interrupts INT0 INT1 INT4 P1 0 P1 1 P0 0 Internal interrupts ...

Page 186: ...ss Then if necessary you can modify the enable flags during the interrupt service routine When the interrupt service routine is returned to the main routine by the IRET instruction the original values saved in the stack are restored and the main program continues program execution with these values Software Generated Interrupts To generate an interrupt request from software the program manipulates...

Page 187: ...0 0 IS1 0 0 1 Stores the contents of PC and PSW in stack area set PC contents to corresponding vector address IS1 0 0 1 Retains until interrupt service routine is completed IS1 0 1 0 NO NO NO NO YES YES YES YES YES NO Reset corresponding IRQx flag Are both interrupt sources of shared vector address used IRQx flag value remains 1 Jump to interrupt start address YES NO Retains value until IME 1 Reta...

Page 188: ...IMOD0 INTB INT4 INT0 INT1 INTS INTT0 INTW Power Down Mode Release Signal IME IPR IS1 IS0 Interrupt Control Unit Vector Interrupt Generator Noise Filtering Circuit Edge Detection Circuit Selector IMOD2 INT2 KS0 KS7 IET0 IES IE1 IE0 IE4 IEB IEW IE2 Figure 7 2 Interrupt Control Circuit Diagram ...

Page 189: ...S1 and IS0 are incremented by one and the values are stored in the stack along with the other PSW bits After the interrupt routine has been serviced the modified IS1 and IS0 values are automatically restored from the stack by an IRET instruction IS0 and IS1 can be manipulated directly by 1 bit write instructions regardless of the current value of the enable memory bank flag EMB Before you can modi...

Page 190: ...iced In this way the high and low priority requests can be serviced in parallel see Figure 7 4 Table 7 2 IS1 and IS0 Bit Manipulation for Multi Level Interrupt Handling Process Status Before INT Effect of Isx Bit Setting After INT ACK IS1 IS0 IS1 IS0 0 0 0 All interrupt requests are serviced 0 1 1 0 1 Only high priority interrupts as determined by the current settings in the IPR register are servi...

Page 191: ...to logic one The IME flag mapped FB2H 3 can be directly manipulated by EI and DI instructions regardless of the current enable memory bank EMB value Table 7 4 Interrupt Priority Register Settings NOTE During normal interrupt processing interrupts are processed in the order in which they occur If two or more interrupt requests are received simultaneously the priority level is determined according t...

Page 192: ...gger The INT4 interrupt is an exception since its input signal generates an interrupt request on both rising and falling edges Since INT2 is a qusi interrupt the interrupt request flag IRQ2 must be cleared by software FB4H IMOD0 3 0 IMOD0 1 IMOD0 0 FB5H 0 0 0 IMOD1 0 FB6H 0 IMOD2 2 IMOD2 1 IMOD2 0 IMOD0 IMOD1 and IMOD2 are addressable by 4 bit write instructions RESET clears all IMOD values to log...

Page 193: ...he pulse width of the clock selected by IMOD0 This is true even when the INT0 pin is used for general purpose input INT0 CPU clock fxx 64 INT1 NOISE FILTER EDGE IRQ0 IMOD0 IMOD1 CLOCK SELECTOR P1 1 P1 0 EDGE IRQ1 Figure 7 5 Circuit Diagram for INT0 and INT1 Pins When modifying the IMOD registers it is possible to accidentally set an interrupt request flag To avoid unwanted interrupts take these pr...

Page 194: ...If a rising or falling edge is detected at any one of the selected KS pin by the IMOD2 register the IRQ2 flag is set to logic one and a release signal for power down mode is generated Table 7 6 IMOD2 Register Bit Settings IMOD2 0 IMOD2 2 IMOD2 1 IMOD2 0 Effect of IMOD2 Settings 0 0 0 Select rising edge at INT2 pin 0 0 1 Select falling edge at KS4 KS7 0 1 0 Select falling edge at KS2 KS7 0 1 1 Sele...

Page 195: ... P2308 C2316 P2316 INTERRUPTS 7 11 INT2 KS7 KS6 KS5 KS4 KS3 KS2 KS1 KS0 IRQ2 FALLING EDGE DETECTION CIRCUIT CLOCK SELECTOR RISING EDGE DETECTION CIRCUIT IMOD2 Figure 7 6 Circuit Diagram for INT2 and KS0 KS7 Pins ...

Page 196: ...errupt Enable Flags IEx IEx flags when set to logical one enable specific interrupt requests to be serviced When the interrupt request flag is set to logical one an interrupt will not be serviced until its corresponding IEx flag is also enabled Interrupt enable flags can be read written or tested directly by 1 bit instructions IEx flags can be addressed directly at their specific RAM addresses des...

Page 197: ...re an interrupt is generated When two interrupts share the same service routine start address interrupt processing may occur in one of two ways When only one interrupt is enabled the IRQx flag is cleared automatically when the interrupt has been serviced When two interrupts are enabled the request flag is not automatically cleared so that the user has an opportunity to locate the source of the int...

Page 198: ...4 PROGRAMMING TIP Enabling the INTB and INT4 Interrupts To simultaneously enable INTB and INT4 interrupts INTB DI BTSTZ IRQB IRQB 1 JP INT4 If no INT4 interrupt if yes INTB interrupt is processed EI IRET INT4 BITR IRQ4 INT4 is processed EI IRET ...

Page 199: ...nd on external interrupt requests is detailed in Table 8 1 NOTE Do not use stop mode if you are using an external clock source because XIN input must be restricted internally to VSS to reduce current leakage Idle or main stop modes are terminated either by a RESET or by an interrupt which is enabled by the corresponding interrupt enable flag IEx When power down mode is terminated by RESET a normal...

Page 200: ...r 0 Operates only if TCL0 is selected as counter clock Operates only if TCL0 is selected as counter clock Operates only if TCL0 is selected as counter clock Timer counter 0 operates Watch timer Operates only if sub clock fxt is selected as counter clock Watch timer stops Watch timer stops Watch timer operates LCD controller Operates only if sub clock fxt is selected as LCD clock LCDCK LCD controll...

Page 201: ...ON 31 3 ms 4 19 MHz NORMAL MODE IDLE MODE NORMAL MODE NORMAL OSCILLATION RESET Figure 8 1 Timing When Idle Mode is Released by RESET NORMAL MODE IDLE MODE NORMAL MODE NORMAL OSCILLATION MODE RELEASE SIGNAL IDLE INSTRUCTION CLOCK SIGNAL INTERRUPT ACKNOWLEDGE IME 1 Figure 8 2 Timing When Idle Mode is Released by an Interrupt ...

Page 202: ...AL MODE OSCILLATION RESUMES STOP MODE OSCILLATION STOPS Figure 8 3 Timing When Stop Mode is Released by RESET OSCILLATION STABILIZATION BMOD SETTING NORMAL MODE IDLE MODE NORMAL MODE OSCILLATION RESUMES STOP MODE OSCILLATION STOPS MODE RELEASE SIGNAL STOP INSTRUCTION CLOCK SIGNAL INT ACK IME 1 Figure 8 4 Timing When Main Stop or Main Sub Stop Mode is Release by an Interrupt ...

Page 203: ...MA2SUB Main system clock subsystem clock switch subroutine SMB 15 LD EA 00H LD P2 EA All key strobe outputs to low level LD A 3H LD IMOD2 A Select KS0 KS7 enable SMB 0 BITR IRQW BITR IRQ2 BITS IEW BITS IE2 CLKS1 CALL WATDIS Execute clock and display changing subroutine BTSTZ IRQ2 JR CIDLE CALL SUB2MA Subsystem clock main system clock switch subroutine EI RET CIDLE IDLE Engage idle mode NOP NOP NOP...

Page 204: ...t pins according to the information in Table 8 2 2 Disable pull up resistors for input pins configured to VDD or VSS levels in order to check the current input option Reason If the input level of a port pin is set to VSS when a pull up resistor is enabled it will draw an unnecessarily large current 3 Disable the pull up resistors of input pins connected to the external device by making the necessa...

Page 205: ...0 2 SO P0 3 SI Input mode Connect to VDD Output mode No connection P1 0 INT0 P1 1 INT1 P1 2 INT2 P1 3 TCL0 Connect to VDD 1 P2 0 TCLO0 P2 1 P2 2 CLO P2 3 BUZ Input mode Connect to VDD Output mode No connection P3 2 P3 3 P3 1 LCDSY P3 0 LCDCK Input mode Connect to VDD Output mode No connection P8 0 SEG24 P8 7 SEG31 No connection 2 SEG0 SEG23 COM0 COM3 No connection VLC0 VLC2 No connection XTIN Conn...

Page 206: ...POWER DOWN KS57C2308 P2308 C2316 P2316 8 8 NOTES ...

Page 207: ...down mode most hardware register values are set to the reset values described in Table 9 1 The current status of several register values is however always retained when a RESET occurs during idle or stop mode If a RESET occurs during normal operating mode their values are undefined Current values that are retained in this case are as follows Carry flag Data memory values General purpose registers ...

Page 208: ...ndefined Skip flag SC0 SC2 0 0 Interrupt status flags IS0 IS1 0 0 Bank enable flags EMB ERB Bit 6 of address 0000H in program memory is transferred to the ERB flag and bit 7 of the address to the EMB flag Bit 6 of address 0000H in program memory is transferred to the ERB flag and bit 7 of the address to the EMB flag Stack pointer SP Undefined Undefined Data Memory RAM Working registers E A L H X W...

Page 209: ...Count register BCNT Undefined Undefined Mode register BMOD 0 0 Timer Counters 0 and 1 Count registers TCNT0 0 0 Reference registers TREF0 FFH FFH Mode registers TMOD0 0 0 Output enable flags TOE0 0 0 Watchdog Timer WDT mode register WDMOD A5H A5H WDT clear flag WDTCF 0 0 Watch Timer Watch timer mode register WMOD 0 0 LCD Driver Controller LCD mode register LMOD 0 0 LCD control register LCON 0 0 Di...

Page 210: ...RESET KS57C2308 P2308 C2316 P2316 9 4 NOTES ...

Page 211: ...gs PM are used to configure I O ports to input or output mode by setting or clearing the corresponding I O buffer Pull Up Resistor Mode Register PUMOD The pull up resistor mode registers PUMOD are used to assign internal pull up resistors by software to specific ports When a configurable I O port pin is used as an output pin its assigned pull up resistor is automatically disabled even though the p...

Page 212: ... set to N channel open drain output up to 5 volts 1 4 and 8 bit read write test are possible Ports 4 and 5 can be paired to support 8 bit data transfer Pull up resistors are software assignable pull up resistor are automatically disable for output 6 7 I O 8 P6 0 P6 3 P7 0 P7 3 FF6H FF7H 4 bit I O port Port 6 pins are individually software configurable as input or output 1 and 4 bit read write test...

Page 213: ... Ports to Input or Output Configure ports 3 and 6 as an output port BITS EMB SMB 15 LD EA 0FFH LD PMG1 EA P3 and P6 Output PULL UP RESISTOR MODE REGISTER PUMOD The pull up resistor mode registers PUMOD1 and PUMOD2 are used to assign internal pull up resistors by software to specific ports When a configurable I O port pin is used as an output pin its assigned pull up resistor is automatically disab...

Page 214: ...d in bank 1 of data memory instead of bank 15 To address port 8 output pins use the settings EMB 1 and SMB 1 The LCD mode register LMOD is used to control whether the pin address is used for LCD data output or for normal data output Table 10 5 LMOD 7 and LMOD 6 Setting for Port 8 Output Control LMOD 7 LMOD 6 LCD Output Segments 1 Bit Output Pins 0 0 Seg 24 31 0 1 Seg 24 27 P8 4 P8 7 Seg 28 31 1 0 ...

Page 215: ... 10 5 Table 10 6 Port 8 Pin Addresses and LCD Segment Correspondence Port 8 Pin Number RAM Address LCD Segment P8 0 1F8H SEG24 P8 1 1F9H SEG25 P8 2 1FAH SEG26 P8 3 1FBH SEG27 P8 4 1FCH SEG28 P8 5 1FDH SEG29 P8 6 1FEH SEG30 P8 7 1FFH SEG31 ...

Page 216: ... VDD When and SO act as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings to the pull up resistor mode register PUMOD NOTE PUMOD 0 INT4 8 P0 0 INT4 P0 2 SO P0 3 SI P0 1 SCK SCK Figure 10 1 Port 0 Circuit Diagram ...

Page 217: ...PORT 1 CIRCUIT DIAGRAM VDD PUMOD 1 INT0 P1 1 P1 2 P1 3 P1 0 N R Circuit INT1 INT2 TCL0 INT0 CPU clock fxx 64 INT1 Edge Detection IRQ0 IMOD0 IMOD1 Clock Selector P1 1 P1 0 Edge Detection IRQ1 Noise Filter IMOD0 Figure 10 2 Port 1 Circuit Diagram ...

Page 218: ...2 1 P2 2 CLO P2 3 BUZ PM2 Output Latch When a port pin acts as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings to the pull up resistor mode register PUMOD NOTE TCLO0 BUZ CLO PUMOD 2 VDD Figure 10 3 Port 2 Circuit Diagram ...

Page 219: ...When a port pin acts as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings to the pull up resistor mode register PUMOD NOTE M U X PMx 2 PMx 3 PMx 1 PMx 0 Px 0 Px 1 Px 2 Px 3 Output Latch PUMOD x Figure 10 4 Port 3 and 6 Circuit Diagram ...

Page 220: ...S Push Pull or N Channel Open Deain When a port pin acts as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings to the pull up resistor mode register PUMOD NOTE x port number 4 5 PM x PUMOD x PNEx 3 PNEx 2 PNEx 1 PNEx 0 Figure 10 5 Port 4 and 5 Circuit Diagram ...

Page 221: ... P7 1 P7 2 P7 3 When a port pin acts as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings to the pull up resistor mode register PUMOD NOTE PUMOD 7 Output Latch M U X VDD PM7 Figure 10 6 Port 7 Circuit Diagram ...

Page 222: ...I O PORTS KS57C2308 P2308 C2316 P2316 10 12 NOTES ...

Page 223: ...imer and is used to determine clock oscillation stabilization time when stop mode is released by an interrupt and after a RESET The 8 bit timer counter TC0 is programmable timer counter that is used primarily for event counting and for clock frequency modification and output In addition TC0 generates a clock signal that can be used by the serial I O interface The watch timer WT module consists of ...

Page 224: ...hat corresponds to the frequency selected by BMOD BCNT continues incrementing as it counts BT clocks until an overflow occurs An overflow causes the BT interrupt request flag IRQB to be set to logic one to signal that the designated time interval has elapsed An interrupt request is then generated BCNT is cleared to logic zero and counting continues from 00H Oscillation Stabilization Interval Contr...

Page 225: ...trols watchdog timer operation 8 bit F98H F99H 8 bit write only A5H WDTCF Control Clear the watchdog timer s counter 1 bit F9AH 3 1 bit write only 0 NOTE U means that the value is undetermined after a RESET Clear Signal Bits Instruction Clock Selector IRQB Interrupt Request Overflow CPU Clock Start Signals By Interrupts 1 Bit R W Clock Input Clear IRQB 4 Clear BCNT BMOD 3 BMOD 2 BMOD 1 BMOD 0 8 WD...

Page 226: ...en BMOD 3 is set to logic one enabled by a 1 bit write instruction the contents of the BT counter register BCNT and the BT interrupt request flag IRQB are both cleared to logic zero and timer operation is restarted The combination of bit settings in the remaining three registers BMOD 2 BMOD 1 and BMOD 0 determines the clock input frequency and oscillation stabilization interval Table 11 2 Basic Ti...

Page 227: ...ly resumes counting with incoming clock signal NOTE Always execute a BCNT read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing If after two consecutive reads the BCNT values match you can select the latter value as valid data Until the results of the consecutive reads match however the read operation must be repeated until the validation cond...

Page 228: ...s at 4 19 MHz BITS EMB SMB 15 LD A 0BH LD BMOD A Wait time is 31 3 ms NOP STOP Get into stop for power down mode NOP NOP NOP NORMAL OPERATING MODE STOP MODE IDLE MODE 31 3 ms CPU OPERATION STOP INSTRUCTION STOP MODE IS RELEASED BY INTERRUPT NORMAL OPERATING MODE 3 To set the basic timer interrupt interval time to 1 95 ms at 4 19 MHz BITS EMB SMB 15 LD A 0FH LD BMOD A EI BITS IEB Basic timer interr...

Page 229: ...current BMOD bit setting is generated When WDCNT has incremented to hexadecimal 07H it is cleared to 00H and an overflow is generated The overflow causes the system RESET When the interrupt request is generated BCNT immediately resumes counting incoming clock signals WATCHDOG TIMER COUNTER CLEAR FLAG WDTCF The watchdog timer counter clear flag WDTCF is a 1 bit write instruction When WDTCF is set t...

Page 230: ...316 P2316 11 8 PROGRAMMING TIP Using the Watchdog Timer RESET DI BITS EMB SMB 15 LD EA 00H LD SP EA LD A 0DH WDCNT input clock is 7 82 ms LD BMOD A MAIN BITS WDTCF Main routine operation period must be shorter than watchdog timer s period JP MAIN ...

Page 231: ...register TMOD0 is used to activate the timer counter and to select the basic clock frequency to be used for timer counter operations To dynamically modify the basic frequency new values can be loaded into the TMOD0 register during program execution TC0 FUNCTION SUMMARY 8 bit programmable timer Generates interrupts at specific time intervals based on the selected clock frequency External event coun...

Page 232: ...g the current value of the counter register TCNT0 with the reference value previously programmed into the reference register TREF0 Output latch TOL0 Where a clock pulse is stored pending output to the serial I O circuit or to the TC0 output pin TCLO0 When the contents of the TCNT0 and TREF0 registers coincide the timer counter interrupt request flag IRQT0 is set to 1 the status of TOL0 is inverted...

Page 233: ...Counter Counts clock pulses matching the TMOD0 frequency setting 8 bit F94H F95H 8 bit read only 0 TREF0 Reference Stores reference value for the timer counter 0 interval setting 8 bit F96H F97H 8 bit write only FFH TOE0 Flag Controls timer counter 0 output to the TCLO0 pin 1 bit F92H 2 1 bit write only 0 Clock Selector TCNT0 8 Bit Comparator TOL0 IRQT0 TMOD0 7 TMOD0 6 TMOD0 5 TMOD0 4 TMOD0 3 TMOD...

Page 234: ...ne Set the TC0 interrupt enable flag IET0 to logic one Set TMOD0 3 to logic one TCNT0 IRQT0 and TOL0 are cleared to logic zero and timer counter operation starts Disable Timer Counter 0 Set TMOD0 2 to logic zero Clock signal input to the counter register TCNT0 is halted The current TCNT0 value is retained and can be read if necessary ...

Page 235: ...equency specified by TMOD0 4 TMOD0 6 settings To generate an interrupt request the TC0 interrupt request flag IRQT0 is set to logic one the status of TOL0 is inverted and the interrupt is generated The content of TCNT0 is then cleared to 00H and TC0 continues counting The interrupt request mechanism for TC0 includes an interrupt enable flag IET0 and an interrupt request flag IRQT0 TC0 OPERATION SE...

Page 236: ...he external clock signal occurs With the exception of the different TMOD0 4 TMOD0 6 settings the operation sequence for TC0 s event counter function is identical to its programmable timer counter function To activate the TC0 event counter function Set TMOD0 2 to 1 to enable TC0 Clear TMOD0 6 to 0 to select the external clock source at the TCL0 pin Select TCL0 edge detection for rising or falling s...

Page 237: ...value for P2 0 must be set to 0 In summary the operational sequence required to output a TC0 generated clock signal to the TCLO0 pin is as follows 1 Load a reference value to TREF0 2 Set the internal clock frequency in TMOD0 3 Initiate TC0 clock output to TCLO0 TMOD0 2 1 4 Set P2 0 mode flag to 1 5 Clear P2 0 output latch to 0 6 Set TOE0 flag to 1 Each time TCNT0 overflows and an interrupt request...

Page 238: ...rnal clock source and loading a reference value into the TC0 reference register TREF0 you can divide the incoming clock signal by the TREF0 value and then output this modified clock frequency to the TCLO0 pin The sequence of operations used to divide external clock input can be summarized as follows 1 Load a signal divider value to the TREF0 register 2 Clear TMOD0 6 to 0 to enable external clock i...

Page 239: ...The TMOD0 6 TMOD0 5 and TMOD0 4 bit settings are used together to select the TC0 clock source This selection involves two variables Synchronization of timer counter operations with either the rising edge or the falling edge of the clock signal input at the TCL0 pin and Selection of one of four frequencies based on division of the incoming system clock frequency for use in internal TC0 operation Ta...

Page 240: ...ing edges 0 0 1 External clock input TCL0 on falling edges 1 0 0 fxx 210 4 09 kHz 1 0 1 fxx 28 16 4 kHz 1 1 0 fxx 26 65 5 kHz 1 1 1 fxx 24 262 kHz NOTE fxx selected system clock of 4 19 MHz PROGRAMMING TIP Restarting TC0 Counting Operation 1 Set TC0 timer interval to 4 09 kHz BITS EMB SMB 15 LD EA 4CH LD TMOD0 EA EI BITS IET0 2 Clear TCNT0 IRQT0 and TOL0 and restart TC0 counting operation BITS EMB...

Page 241: ...ith reference clock specified by TMOD0 register specifically TMOD0 6 TMOD0 5 and TMOD0 4 is input Each time TCNT0 is incremented the new value is compared with the reference value stored in the TC0 reference buffer TREF0 When TCNT0 TREF0 an match signal occurs in the comparator the interrupt request flag IRQT0 is set to logic one and an interrupt request is generated to indicate that the specified...

Page 242: ...mer counter 0 output enable flag TOE0 controls output from timer counter 0 to the TCLO0 pin TOE0 is addressable by 1 bit write instructions MSB LSB F92H U TOE0 U U NOTE U indicates unknown state When you set the TOE0 flag to 1 the contents of TOL0 can be output to the TCLO0 pin Whenever a RESET occurs TOE0 is automatically set to logic zero disabling all TC0 output Even when the TOE0 flag is disab...

Page 243: ...ow these steps 1 Select the timer counter 0 mode register with a maximum setup time of 62 5 ms assume the TC0 counter clock fxx 210 and TREF0 is set to FFH 2 Calculate the TREF0 value 30 ms TREF0 value 1 4 09 kHz TREF0 1 30 ms 244 µs 122 9 7AH TREF0 value 7AH 1 79H 3 Load the value 79H to the TREF0 register BITS EMB SMB 15 LD EA 79H LD TREF0 EA LD EA 4CH LD TMOD0 EA ...

Page 244: ... zero by program software as soon as a requested interrupt service routine has been executed Using a System or Subsystem Clock Source The watch timer can generate interrupts based on the system clock frequency or on the subsystem clock When the zero bit of the WMOD register is set to 1 the watch timer uses the subsystem clock signal fxt as its source if WMOD 0 0 the system clock fxx is used as the...

Page 245: ...atch for I O port 2 3 is cleared to 0 The port 2 3 output mode flag PM2 set to output mode Timing Tests in High Speed Mode By setting WMOD 1 to 1 the watch timer will function in high speed mode generating an interrupt every 3 91 ms At its normal speed WMOD 1 0 the watch timer generates an interrupt request every 0 5 seconds High speed mode is useful for timing events for program debugging sequenc...

Page 246: ... 14 Enable Disable Clock Selector fx Main System Clock 4 19 MHz fxt Subsystem Clock 32 768 kHz fw Watch Timer Frequency fxx System Clock BUZ WMOD 7 WMOD 6 WMOD 5 WMOD 4 WMOD 3 WMOD 2 WMOD 1 WMOD 0 P2 3 PM2 fw 8 4 kHz fw 4 8 kHz fw 2 16 kHz Frequency Dividing Circuit fw 2 512 Hz 6 fLCD fw 16 2 kHz Figure 11 4 Watch Timer Circuit Diagram ...

Page 247: ...D 3 Buzzer frequency selection WMOD 4 and WMOD 5 Enable disable buzzer output WMOD 7 Table 11 8 Watch Timer Mode Register WMOD Organization Bit Name Values Function Address WMOD 7 0 Disable buzzer BUZ signal output F89H 1 Enable buzzer BUZ signal output WMOD 6 0 Always logic zero WMOD 5 4 0 0 2 kHz buzzer BUZ signal output 0 1 4 kHz buzzer BUZ signal output 1 0 8 kHz buzzer BUZ signal output 1 1 1...

Page 248: ...ck as the LCD display clock a 0 5 second interrupt and 2 kHz buzzer enable BITS EMB SMB 15 LD EA 04H LD PMG2 EA P2 3 output mode BITR P2 3 LD EA 85H LD WMOD EA BITS IEW 2 Sample real time clock processing method CLOCK BTSTZ IRQW 0 5 second check RET No return Yes 0 5 second interrupt generation Increment HOUR MINUTE SECOND ...

Page 249: ...isplay output are determined by bit settings in the LCD mode register LMOD The LCD control register LCON is used to turn the LCD display on and off to switch current to the dividing resistors for the LCD display and to output LCD clock LCDCK and synchronizing signal LCDSY for LCD display expansion Data written to the LCD display RAM can be transferred to the segment signal pins automatically witho...

Page 250: ...F4H 3 1FFH 0 1FFH 1 1FFH 2 1FFH 3 4 4 LMOD 8 COM3 COM2 COM1 COM0 COM CONTROL VLC0 VLC1 VLC2 LCDSY LCDCK SEG30 P8 6 SEG29 P8 5 SEG28 P8 4 SEG27 P8 3 SEG26 P8 2 SEG25 P8 1 SEG24 P8 0 SEG23 SEG22 SEG21 SEG20 SEG19 SEG0 f LCD LCON S E L S E L Port 3 latch 0 1 PMG1 M U X M U X M U X S E G M E N T D R I V E R LCD VOLTAGE CONTROL 1 0 Figure 12 2 LCD Circuit Diagram ...

Page 251: ...nized with the fLCD signal RAM addresses in this location that are not used for LCD display can be allocated to general purpose use SEG0 1E0H 1E1H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH 1F9H 1F8H COM3 COM2 COM1 COM0 BIT0 P8 0 P8 1 P8 2 P8 3 P8 4 P8 5 P8 6 P8 7 BIT1 BIT2 BIT3 SEG1 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 Figure 12 3 LCD Display Data RAM Organization Table 12 1 Common Signal Pins Used...

Page 252: ...his bit is used for internal testing only always logic zero LCON 2 0 Disable LCDCK and LCDSY signal outputs 1 Enable LCDCK and LCDSY signal outputs LCON 1 0 Always logic zero LCON 0 0 LCD output low display off cut off current to dividing resistor and output port 8 latch contents 1 If LMOD 3 0 LCD display off output port 8 latch contents If LMOD 3 1 COM and SEG output in display mode LCD display o...

Page 253: ...D display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source and running The LCD mode register LMOD controls the output mode of the 8 pins used for normal outputs P8 0 P8 7 Bits LMOD 7 6 define the segment output and normal bit output configuration Table 12 4 LCD Mode Register LMOD Organization LMOD 7 LMOD 6 LCD Output Segments and 1 Bit Outpu...

Page 254: ... 1 2 VLCD 2 3 VLCD VLC2 1 3 VLCD 1 2 VLCD 1 3 VLCD GND 0 V 0 V 0 V NOTE The LCD panel display may deteriorate if DC voltage is applied between the common and segment signals Therefore always drive the LCD panel with AC voltage LCD VOLTAGE DIVIDING RESISTORS On chip voltage dividing resistors for the LCD drive power supply can be configured by internal voltage dividing resistors Using these interna...

Page 255: ...2R R R R BIAS PIN VLC0 VLC1 VLC2 VDD LCON 0 VSS 2R R R R VLCD 2 5 V 1 2 Bias BIAS PIN VLC0 VLC1 VLC2 VDD R Voltage dividing resistor R External resistor LCON 0 VSS 2R R R R VLCD 5 V Static and 1 3 Bias BIAS PIN VLC0 VLC1 VLC2 VDD Static and 1 3 Bias VLCD VLCD 2 5 V at VDD 5 V VLCD 5 V at VDD 5 V VLCD 3 V at VDD 3 V VLCD 3 V at VDD 5 V Figure 12 4 Voltage Dividing Resistor Circuit Diagrams ...

Page 256: ... and COM3 pins In 1 2 duty mode be open the COM2 and COM3 pin In 1 3 duty mode be open the COM3 pin Table 12 6 Common Signal Pins Used Per Duty Cycle Display Mode COM0 Pin COM1 Pin COM2 Pin COM3 Pin Static Selected N C N C N C 1 2 duty Selected Selected N C N C 1 3 duty Selected Selected Selected N C 1 4 duty Selected Selected Selected Selected NOTE NC means that no connection is required VLCD Tf ...

Page 257: ...316 P2316 LCD CONTROLLER DRIVER 12 9 VLCD Tf 2 x T COM0 1 1 2 DUTY VLC0 VLC1 2 VSS VLCD Tf 3 x T COM0 1 1 3 DUTY VLC0 VLC1 2 VSS T LCDCK Tf Frame frequency Figure 12 6 LCD Common Signal Waveform at 1 2 Bias 1 2 1 3 Duty ...

Page 258: ... KS57C2308 P2308 C2316 P2316 12 10 T LCDCK Tf Frame frequency VLCD Tf 4 x T COM0 3 1 4 DUTY VLC0 VLC1 VSS VLC2 VLCD Tf 3 x T COM0 2 1 3 DUTY VLC0 VLC1 VSS VLC2 Figure 12 7 LCD Common Signal Waveform at 1 3 Bias 1 3 1 4 Duty ...

Page 259: ...the bit value of a display RAM location is 1 a select signal is sent to the corresponding segment pin When the display bit is 0 a no select signal is sent to the corresponding segment pin Each bias has select and no select signals Table 12 7 Select No Select Signals for LCD Static Display Mode SEG Select No select COM VLC0 VSS VSS VLC0 VSS VLC0 VLC0 VLC0 0 V 0 V T LCDCK T COM VLC0 VSS SEG SELECT T...

Page 260: ... LCD 1 2 Bias Display Mode SEG Select Non select COM VLC0 VSS VSS VLC0 Select VSS VLC0 VLC0 VLC0 0 V 0 V Non select VLC1 VLC2 1 2 VLCD 1 2 VLCD 1 2 VLCD 1 2 VLCD T LCDCK T COM VLC0 VSS SEG SELECT T VLC1 2 VSS VLC0 VLC1 2 NO SELECT Figure 12 9 Select No select Bias Signals in 1 2 Bias Display Mode ...

Page 261: ... 1 3 Bias Display Mode SEG Select Non select COM VLC0 VSS VSS VLC0 Select VSS VLC0 VLC0 VLC0 0 V 0 V Non select VLC1 VLC2 1 3 VLCD 1 3 VLCD 1 3 VLCD 1 3 VLCD T LCDCK T COM VLC0 SEG SELECT T VLC2 VSS VLC0 VLC1 NO SELECT VLC1 VSS VLC2 Figure 12 10 Select No select Bias Signals in 1 3 Bias Display Mode ...

Page 262: ...LCD CONTROLLER DRIVER KS57C2308 P2308 C2316 P2316 12 14 VLCD VLCD 0 V SEG12 VLC0 VSS SEG11 VLC0 VSS COM0 VLC0 VSS COM0 SEG11 COM0 SEG12 VLCD VLCD 0 V Tf Figure 12 11 LCD Signal Waveforms in Static Mode ...

Page 263: ...1F0H 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH 0 1 1 1 1 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1E0H 1E1H 1E2H 1E3H 1E4H 1E5H 1E6H 1E7H 0 0 0 0 0 1 1 0 X X X X X X X X X X X X X X X X X X X X X X X X SEG29 SEG30 SEG31 SEG22 ...

Page 264: ... P2308 C2316 P2316 12 16 VLCD V LCD V LC0 VSS VLC1 2 VLC0 VSS VLC1 2 VLC0 VSS VLC1 2 1 2 V LCD 1 2 V LCD 0 V LCD 1 2 V LCD 1 2 V LCD 0 VLCD COM1 SEG9 COM0 SEG9 COM1 SEG9 COM0 Tf Figure 12 13 LCD Signal Waveforms at 1 2 Duty 1 2 Bias ...

Page 265: ... 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH 1E0H 1E1H 1E2H 1E3H 1E4H 1E5H 1E6H 1E7H SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 Bit 0 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 1 1 0 0 1 1 1 0 1 0 0 1 1 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 0 X X X X X X X X X ...

Page 266: ... LC1 2 COM0 Tf VLC0 VSS VLC1 2 COM1 VLC0 V SS V LC1 2 COM2 VLC0 V SS V LC1 2 SEG12 VLCD V LCD 1 2 V LCD 1 2 V LCD 0 COM0 SEG12 V LCD 1 2 VLCD 1 2 V LCD 0 V LCD COM1 SEG12 V LCD 1 2 VLCD 1 2 V LCD 0 V LCD COM2 SEG12 Figure 12 15 LCD Signal Waveforms at 1 3 Duty 1 2 Bias ...

Page 267: ...0H 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH 1E0H 1E1H 1E2H 1E3H 1E4H 1E5H 1E6H 1E7H SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 X 1 0 X 0 0 X 1 0 X 1 1 0 0 X 1 0 X 1 0 X 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 0 1 1 X X 0 0 1 1 1 0 X X X 0 0 X 1 0 X X X ...

Page 268: ...CD COM2 SEG12 1 3 VLCD 0 VLCD 1 3 VLCD VLCD COM1 SEG12 1 3 VLCD 0 VLCD LCD 1 3 VLCD VLCD COM0 SEG12 1 3 VLCD 0 V SEG12 V V LC0 SS VLC2 VLC1 COM2 V V LC0 SS VLC2 VLC1 COM1 V V LC0 SS VLC2 VLC1 COM0 V V LC0 SS VLC2 VLC1 Figure 12 17 LCD Signal Waveforms at 1 3 Duty 1 3 Bias ...

Page 269: ...0H 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH 1E0H 1E1H 1E2H 1E3H 1E4H 1E5H 1E6H 1E7H SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 X 1 0 X 0 0 X 1 0 X 1 1 0 0 X 1 0 X 1 0 X 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 0 1 1 X X 0 0 1 1 1 0 X X X 0 0 X 1 0 X X X ...

Page 270: ...LC0 SS VLC2 VLC1 COM1 V V LC0 SS V LC2 VLC1 COM2 V V LC0 SS VLC2 VLC1 COM3 V V LC0 SS VLC2 VLC1 SEG13 V V LC0 SS VLC2 VLC1 COM0 SEG13 1 3 VLCD V LCD V LCD 1 3 V LCD 0 COM1 SEG13 1 3 VLCD V LCD VLCD 1 3 VLCD 0 T f Figure 12 19 LCD Signal Waveforms at 1 4 Duty 1 3 Bias ...

Page 271: ... 1 1 1 1 1 1 1 0 1 0 0 0 1 1 1 0 1 1 1 0 1 1 1 1 0 0 0 1 0 1 0 1 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1E0H 1E1H 1E2H 1E3H 1E4H 1E5H 1E6H 1E7H 0 0 0 1 0 1 1 0 0 1 1 1 1 1 1 1 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0 0 SEG29 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG30 S...

Page 272: ...LCD CONTROLLER DRIVER KS57C2308 P2308 C2316 P2316 12 24 NOTES ...

Page 273: ...n internal or an external clock source or the TOL0 signal that is generated by the 8 bit timer counter TC0 If the TOL0 clock signal is used you can modify its frequency to adjust the serial data transmission rate SERIAL I O OPERATION SEQUENCE The general operation sequence of the serial I O interface can be summarized as follows 1 Set SIO mode to transmit and receive or to receive only 2 Select MS...

Page 274: ...m Clock INTERNAL BUS LSB or MSB first SBUF 8 BIT SI CLOCK SELECTOR R Q D TOL0 CPU CLK fxx 2 fxx 2 R S Q SO SMOD 7 SMOD 6 SMOD 5 SMOD 3 SMOD 2 SMOD 1 SMOD 0 Q0 Q1 Q2 3 BIT COUNTER CLEAR OVERFLOW IRQS CK 8 INTERNAL BUS BITS 8 P0 1 SCK 10 4 Figure 13 1 Serial I O Interface Circuit Diagram ...

Page 275: ...ster SMOD Organization SMOD 0 0 Most significant bit MSB is transmitted first 1 Least significant bit LSB is transmitted first SMOD 1 0 Receive only mode output buffer is off 1 Transmit and receive mode output buffer is on SMOD 2 0 Disable the data shifter and clock counter retain contents of IRQS flag when serial transmission is halted 1 Enable the data shifter and clock counter set IRQS flag to ...

Page 276: ...SI SO IRQS DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 TRANSMIT COMPLETE SET SMOD 3 Figure 13 2 SIO Timing in Transmit Receive Mode SCK SI SO IRQS DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 TRANSMIT COMPLETE SET SMOD 3 HIGH IMPEDANCE Figure 13 3 SIO Timing in Receive Only Mode ...

Page 277: ... each rising edge of the SIO clock When receive only mode is used incoming data are input to the SIO buffer at the rate of one bit for each rising edge of the SIO clock PROGRAMMING TIP Setting Transmit Receive Modes for Serial I O 1 Transmit the data value 48H through the serial I O interface using an internal clock frequency of fxx 24 and in MSB first mode BITS EMB SMB 15 LD EA 48H LD SBUF EA LD ...

Page 278: ...z at 4 19 MHz in LSB first mode BITR EMB LD EA TDATA TDATA address BANK0 20H 7FH LD SBUF EA LD EA 8FH LD SMOD EA SIO start EI BITS IES INTS PUSH SB Store SMB SRB PUSH EA Store EA BITR EMB LD EA TDATA EA Transmit data TDATA address BANK0 20H 7FH XCH EA SBUF Transmit data Receive data LD RDATA EA RDATA address BANK0 20H 7FH BITS SMOD 3 SIO start POP EA POP SB IRET KS57C2308 C2316 P0 1 SO P0 2 SI P0 ...

Page 279: ... BITR EMB LD EA TDATA TDATA address BANK0 20H 7FH LD SBUF EA LD EA 0FH LD SMOD EA SIO start EI BITS IES INTS PUSH SB Store SMB SRB PUSH EA Store EA BITR EMB LD EA TDATA EA Transmit data TDATA address BANK0 20H 7FH XCH EA SBUF Transmit data Receive data LD RDATA EA RDATA address BANK0 20H 7FH BITS SMOD 3 SIO start POP EA POP SB IRET KS57C2308 C2316 P0 1 SO P0 2 SI P0 3 EXTERNAL DEVICE SCK High Spee...

Page 280: ...SERIAL I O INTERFACE KS57C2308 P2308 C2316 P2316 13 8 NOTES ...

Page 281: ...characteristics Subsystem clock oscillator characteristics I O capacitance A C electrical characteristics Operating voltage range Miscellaneous Timing Waveforms A C timing measurement point Clock timing measurement at XIN Clock timing measurement at XTIN TCL timing Input timing for RESET Input timing for external interrupts Serial data transfer timing Stop Mode Characteristics and Timing Waveforms...

Page 282: ...rature TA 40 to 85 C Storage Temperature Tstg 65 to 150 NOTE The values for Output Current Low IOL are calculated as Peak Value Duty Table 14 2 D C Electrical Characteristics TA 40 C to 85 C VDD 1 8 V to 5 5 V Parameter Symbol Conditions Min Typ Max Units Input high voltage VIH1 All input pins except those specified below for VIH2 VIH3 0 7 VDD VDD V VIH2 Ports 0 1 6 7 and RESET 0 8 VDD VDD VIH3 XI...

Page 283: ...t ILIL1 VIN 0 V All input pins except XIN XOUT XTIN and XTOUT 3 ILIL2 VIN 0 V XIN XOUT XTIN and XTOUT 20 Output high leakage current ILOH1 VOUT VDD All output pins 3 µA Output low leakage current ILOL VOUT 0 V All output pins 3 Pull up resistor RL1 Ports 0 7 VIN 0 V VDD 5 V 25 47 100 KΩ VDD 3 V 50 95 200 RL2 VIN 0 V VDD 5 V RESET 100 220 400 VDD 3 V 200 450 800 LCD voltage dividing resistor RLCD T...

Page 284: ... 4 SCMOD 000B crystal oscillator C1 C2 22pF 6 0 MHz 4 19 MHz 1 0 0 9 2 5 2 0 VDD 3 V 10 6 0 MHz 4 19 MHz 0 5 0 4 1 0 0 8 IDD3 Sub operating VDD 3 V 10 CPU fxt 4 SCMOD 1001B 32 kHz crystal oscillator 15 30 µA IDD4 Sub Idle mode VDD 3 V 10 CPU fxt 4 SCMOD 1101B 32 kHz crystal oscillator 6 15 IDD5 Stop mode VDD 5 V 10 CPU fxt 4 SCMOD 1101B 0 5 3 IDD6 3 Stop mode VDD 5 V 10 CPU fx 4 SCMOD 0100B NOTES ...

Page 285: ...ge 4 ms Crystal Oscillator C1 C2 XIN XOUT Oscillation frequency 1 0 4 6 0 MHz Stabilization time 2 VDD 4 5 V to 5 5 V 10 ms VDD 1 8 V to 4 5 V 30 External Clock XIN XOUT XIN input frequency 1 0 4 6 0 MHz XIN input high and low level width tXH tXL 83 3 ns RC Oscillator R XIN XOUT Frequency 1 VDD 5 V R 20 KΩ VDD 5 V R 38 KΩ VDD 3 V 0 4 2 0 1 0 2 MHz NOTES 1 Oscillation frequency and XIN input freque...

Page 286: ... 4 5 V 10 External Clock XTIN XTOUT XTIN input frequency 1 32 100 kHz XTIN input high and low level width tXTL tXTH 5 15 µs NOTES 1 Oscillation frequency and XTIN input frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for oscillating stabilization after a power on occurs Table 14 5 Input Output Capacitance TA 25 C VDD 0 V Parameter Symbol Conditi...

Page 287: ... width tKH tKL VDD 1 8 V to 5 5 V External SCK source 400 ns Internal SCK source tKCY 2 50 VDD 1 8 V to 5 5 V External SCK source 1600 Internal SCK source tKCY 2 150 SI setup time to tSIK External SCK source 100 ns SCK high Internal SCK source 150 SI hold time to tKSI External SCK source 400 ns SCK high Internal SCK source 400 Output delay for SCK to SO tKSO VDD 2 7 V to 5 5 V External SCK source ...

Page 288: ...arameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR Normal operation 1 8 6 5 V Data retention supply current IDDDR VDDDR 1 8 V 0 1 10 µA Release signal set time tSREL Normal operation 0 µs Oscillator stabilization wait tWAIT Released by RESET 217 fx ms time 1 Released by interrupt 2 NOTES 1 During oscillator stabilization wait time all CPU operations must be stopped to ...

Page 289: ...E INTERNAL RESET IDLE MODE OPERATING MODE tSREL Figure 14 2 Stop Mode Release Timing When Initiated By RESET VDD EXECUTION OF STOP INSTRUCTION VDDDR DATA RETENTION MODE STOP MODE tWAIT tSREL IDLE MODE NORMAL OPERATING MODE POWER DOWN MODE TERMINATING SIGNAL INTERRUPT REQUEST Figure 14 3 Stop Mode Release Timing When Initiated By Interrupt Request ...

Page 290: ...DD 0 8 VDD 0 2 VDD MEASUREMENT POINTS Figure 14 4 A C Timing Measurement Points Except for XIN and XTIN Xin tXL tXH x VDD 0 1 V 0 1 V 1 f Figure 14 5 Clock Timing Measurement at XIN XTin tXTL tXTH 1 f VDD 0 1 V 0 1 V xt Figure 14 6 Clock Timing Measurement at XTIN ...

Page 291: ...11 TCL0 tTIL0 tTIH0 1 f 0 2 VDD TI0 0 8 VDD Figure 14 7 TCL0 Timing RESET tRSL 0 2 VDD Figure 14 8 Input Timing for RESET Signal INT0 1 2 4 KS0 to KS7 tINTL tINTH 0 8 VDD 0 2 VDD Figure 14 9 Input Timing for External Interrupts and Quasi Interrupts ...

Page 292: ...ELECTRICAL DATA KS57C2308 P2308 C2316 P2316 14 12 SCK tKL tKH tKCY 0 8 VDD INPUT DATA OUTPUT DATA 0 2 VDD 0 8 VDD 0 2 VDD SI SO tKSO tSIK tKSI Figure 14 10 Serial Data Transfer Timing ...

Page 293: ...ce package Package dimensions in millimeters Pad diagram Pad pin coordinate data table NOTE Dimensions are in millimeters 0 80 0 20 0 10 MAX 0 15 0 10 0 05 0 8 2 65 0 10 3 00 MAX 0 05 MIN 17 90 0 3 14 00 0 2 1 00 80 QFP 1420C 23 90 0 3 80 0 80 1 0 35 0 1 0 15 MAX 20 00 0 2 0 80 0 80 0 20 Figure 15 1 80 QFP 1420C Package Dimensions ...

Page 294: ...MECHANICAL DATA KS57C2308 P2308 C2316 P2316 15 2 NOTES ...

Page 295: ...ersion of the KS57C2308 C2316 microcontroller It has an on chip EPROM instead of masked ROM The EPROM is accessed by a serial data format The KS57P2308 P2316 is fully compatible with the KS57C2308 C2316 both in function and in pin configuration Because of its simple programming requirements the KS57P2308 P2316 is ideal for use as an evaluation chip for the KS57C2308 C2316 ...

Page 296: ... 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 KS57P2308 KS57P2316 TOP VIEW SEG2 SEG1 SEG0 COM0 COM1 COM2 COM3 BIAS VLC0 SDAT VLC1 SCLK VLC2 VDD VDD VSS VSS XOUT XIN VPP TEST XTIN XTOUT RESET P0 0 INT4 P0 1 P0 2 SO P0 3 SI P1 0 INT0 P1 1 INT1 P1 2 INT2 P1 3 TCL0 P2 0 TCLO0 P2 1 P2 2 CLO P2 3 BUZ P3 0 LCDCK P3 1 SCDSY P3 2 P3 3 P4 0 P4 1 P4 2 P4 3 P5...

Page 297: ...amming Table 16 2 Comparison of KS57P2308 P2316 and KS57C2308 C2316 Features Characteristic KS57P2308 P2316 KS57C2308 C2316 Program Memory 8 K 16 K byte EPROM 8 K 16 Kbyte mask ROM Operating Voltage VDD 1 8 V to 5 5 V 1 8 V to 5 5 V OTP Programming Mode VDD 5 V VPP TEST 12 5 V Pin Configuration 80 QFP 80 QFP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACT...

Page 298: ...perature TA 40 to 85 C Storage Temperature Tstg 65 to 150 NOTE The values for Output Current Low IOL are calculated as Peak Value Duty Table 16 5 D C Electrical Characteristics TA 40 C to 85 C VDD 1 8 V to 5 5 V Parameter Symbol Conditions Min Typ Max Units Input high voltage VIH1 All input pins except those specified below for VIH2 VIH3 0 7 VDD VDD V VIH2 Ports 0 1 6 7 and RESET 0 8 VDD VDD VIH3 ...

Page 299: ...ent ILIL1 VIN 0 V All input pins except XIN XOUT XTIN and XTOUT 3 ILIL2 VIN 0 V XIN XOUT XTIN and XTOUT 20 Output high leakage current ILOH1 VOUT VDD All output pins 3 µA Output low leakage current ILOL VOUT 0 V All output pins 3 Pull up resistor RL1 Ports 0 7 VIN 0 V VDD 5 V 25 47 100 KΩ VDD 3 V 50 95 200 RL2 VIN 0 V VDD 5 V RESET 100 220 400 VDD 3 V 200 450 800 LCD voltage dividing resistor RLCD...

Page 300: ...fx 4 SCMOD 000B crystal oscillator C1 C2 22pF 6 0 MHz 4 19 MHz 1 0 0 9 2 5 2 0 VDD 3 V 10 6 0 MHz 4 19 MHz 0 5 0 4 1 0 0 8 IDD3 Sub operating VDD 3 V 10 CPU fxt 4 SCMOD 1001B 32 kHz crystal oscillator 15 30 µA IDD4 Sub Idle mode VDD 3 V 10 CPU fxt 4 SCMOD 1101B 32 kHz crystal oscillator 6 15 IDD5 Stop mode VDD 5 V 10 CPU fxt 4 SCMOD 1101B 0 5 3 IDD6 3 Stop mode VDD 5 V 10 CPU fx 4 SCMOD 0100B NOTE...

Page 301: ...ange 4 ms Crystal Oscillator C1 C2 XIN XOUT Oscillation frequency 1 0 4 6 0 MHz Stabilization time 2 VDD 4 5 V to 5 5 V 10 ms VDD 1 8 V to 4 5 V 30 External Clock XIN XOUT XIN input frequency 1 0 4 6 0 MHz XIN input high and low level width tXH tXL 83 3 ns RC Oscillator R XIN XOUT Frequency 1 VDD 5 V R 20 KΩ VDD 5 V R 38 KΩ VDD 3 V 0 4 2 0 1 0 2 MHz NOTES 1 Oscillation frequency and XIN input freq...

Page 302: ...to 4 5 V 10 External Clock XTIN XTOUT XTIN input frequency 1 32 100 kHz XTIN input high and low level width tXTL tXTH 5 15 µs NOTES 1 Oscillation frequency and XTIN input frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for oscillating stabilization after a power on occurs Table 16 8 Input Output Capacitance TA 25 C VDD 0 V Parameter Symbol Condi...

Page 303: ...ow width tKH tKL VDD 1 8 V to 5 5 V External SCK source 400 ns Internal SCK source tKCY 2 50 VDD 1 8 V to 5 5 V External SCK source 1600 Internal SCK source tKCY 2 150 SI setup time to tSIK External SCK source 100 ns SCK high Internal SCK source 150 SI hold time to tKSI External SCK source 400 ns SCK high Internal SCK source 400 Output delay for SCK to SO tKSO VDD 2 7 V to 5 5 V External SCK sourc...

Page 304: ...C Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR Normal operation 1 8 6 5 V Data retention supply current IDDDR VDDDR 1 8 V 0 1 10 µA Release signal set time tSREL Normal operation 0 µs Oscillator stabilization wait tWAIT Released by RESET 217 fx ms time 1 Released by interrupt 2 NOTES 1 During oscillator stabilization wait time all CPU operations must be stopped ...

Page 305: ...ODE INTERNAL RESET IDLE MODE OPERATING MODE tSREL Figure 16 3 Stop Mode Release Timing When Initiated By RESET VDD EXECUTION OF STOP INSTRUCTION VDDDR DATA RETENTION MODE STOP MODE tWAIT tSREL IDLE MODE NORMAL OPERATING MODE POWER DOWN MODE TERMINATING SIGNAL INTERRUPT REQUEST Figure 16 4 Stop Mode Release Timing When Initiated By Interrupt Request ...

Page 306: ... VDD 0 8 VDD 0 2 VDD MEASUREMENT POINTS Figure 16 5 A C Timing Measurement Points Except for XIN and XTIN Xin tXL tXH x VDD 0 1 V 0 1 V 1 f Figure 16 6 Clock Timing Measurement at XIN XTin tXTL tXTH 1 f VDD 0 1 V 0 1 V xt Figure 16 7 Clock Timing Measurement at XTIN ...

Page 307: ...6 13 TCL0 tTIL0 tTIH0 1 f 0 2 VDD TI0 0 8 VDD Figure 16 8 TCL0 Timing RESET tRSL 0 2 VDD Figure 16 9 Input Timing for RESET Signal INT0 1 2 4 KS0 to KS7 tINTL tINTH 0 8 VDD 0 2 VDD Figure 16 10 Input Timing for External Interrupts and Quasi Interrupts ...

Page 308: ...KS57P2308 P2316 OTP KS57C2308 P2308 C2316 P2316 16 14 SCK tKL tKH tKCY 0 8 VDD INPUT DATA OUTPUT DATA 0 2 VDD 0 8 VDD 0 2 VDD SI SO tKSO tSIK tKSI Figure 16 11 Serial Data Transfer Timing ...

Page 309: ...dress First Location VDD 5V VPP 12 5V x 0 Program One 1ms Pulse Increment X x 10 Verify 1 Byte Last Address VDD VPP 5 V Compare All Byte Device Passed Increment Address Verify Byte Device Failed PASS FAIL NO FAIL YES FAIL NO Figure 16 12 OTP Programming Algorithm ...

Page 310: ...KS57P2308 P2316 OTP KS57C2308 P2308 C2316 P2316 16 16 NOTES ...

Page 311: ...tes object code in standard hexadecimal format Assembled program code includes the object code that is used for ROM data and required SMDS program control data To assemble programs SAMA requires a source file and an auxiliary definition DEF file with device specific information SASM57 The SASM57 is an relocatable assembler for Samsung s KS57 series microcontrollers The SASM57 takes a source file c...

Page 312: ...BREAK DISPLAY UNIT TARGET APPLICATION SYSTEM PROBE ADAPTER TB572308A 16A TARGET BOARD PROM MTP WRITER UNIT TRACE TIMER UNIT SAM4 BASE UNIT POWER SUPPLY UNIT POD RS 232C IBM PC AT or Compatible BUS SMDS2 EVA CHIP Figure 17 1 SMDS Product Configuration SMDS2 ...

Page 313: ...roller It is supported by the SMDS2 development system SM1248A TB572308A 16A 1 25 EXTERNAL TRIGGERS CH1 CH2 OFF ON To User_Vcc RESET STOP IDLE 100 PIN CONNECTOR 40 PIN CONNECTOR 1 2 39 40 J101 144 QFP KS57E2308 EVA CHIP 74HC11 40 PIN CONNECTOR 1 2 39 40 J102 BIAS V LC0 V LC1 V LC2 1 36 MDS XTAL XTI MDS XTAL XI Figure 17 2 TB572308A 16A Target Board Configuration ...

Page 314: ...ARGET SYSTEM VCC The SMDS2 SMDS2 supplies VCC only to the target board evaluation chip The target system must have its own power supply Table 17 2 Main clock Selection Settings for TB572308A 16A Sub Clock Setting Operating Mode Comments XTAL MDS XI SMDS2 SMDS2 EVA CHIP KS57E2308 No connection 100 pin connector XIN XOUT Set the XI switch to MDS when the target board is connected to the SMDS2 SMDS2 ...

Page 315: ...ch to XTAL when the target board is used as a standalone unit and is not connected to the SMDS2 SMDS2 Table 17 4 Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part Comments EXTERNAL TRIGGERS CH1 CH2 Connector from external trigger sources of the application system You can connect an external trigger source to one of the two external trigger channels CH1 or CH...

Page 316: ...S3 P7 1 KS5 P7 3 KS7 P8 6 SEG30 P8 4 SEG28 P8 2 SEG26 P8 0 SEG24 SEG22 SEG20 SEG18 SEG16 SEG14 SEG12 SEG10 SEG8 SEG6 SEG4 P5 2 P6 0 KS0 P6 2 KS2 P7 0 KS4 P7 2 KS6 P8 7 SEG31 P8 5 SEG29 P8 3 SEG27 P8 1 SEG25 SEG23 SEG21 SEG19 SEG17 SEG15 SEG13 SEG11 SEG9 SEG7 SEG5 SEG3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 SCK Figure 17 3 40 P...

Page 317: ... applicable See ROM Selection Form Customer sample Risk order See Risk Order Sheet Please answer the following questions For what kind of product will you be using this order New product Upgrade of an existing product Replacement of an existing product Other If you are replacing an existing product please indicate the former product name What are the main reasons you decided to use a Samsung micro...

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Page 319: ... Package Number of Pins ____________ Package Type _____________________ Intended Application ________________________________________________________________ Product Model Number ________________________________________________________________ Customer Risk Order Agreement We hereby request SEC to produce the above named product in the quantity stated below We believe our risk order product to be ...

Page 320: ......

Page 321: ...um ________________________________________________________________ Company Name ________________________________________________________________ Signature Engineer ________________________________________________________________ Please answer the following questions Application Product Model ID _______________________ Audio Video Telecom LCD Databank Caller ID LCD Game Industrials Home Appliance ...

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Page 323: ...um ________________________________________________________________ Company Name ________________________________________________________________ Signature Engineer ________________________________________________________________ Please answer the following questions Application Product Model ID _______________________ Audio Video Telecom LCD Databank Caller ID LCD Game Industrials Home Appliance ...

Page 324: ...y Dates and Quantity ROM Code Release Date Required Delivery Date of Device Quantity Please answer the following questions What is the purpose of this order New product development Upgrade of an existing product Replacement of an existing microcontroller Other If you are replacing an existing microcontroller please indicate the former microcontroller name What are the main reasons you decided to u...

Page 325: ......

Page 326: ...Protection 1 Yes No Please answer the following questions Are you going to continue ordering this device Yes No If so how much will you be ordering _________________ PCS Application Product Model ID _______________________ Audio Video Telecom LCD Databank Caller ID LCD Game Industrials Home Appliance Office Automation Remocon Other Please describe in detail its application ________________________...

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Page 328: ...Protection 1 Yes No Please answer the following questions Are you going to continue ordering this device Yes No If so how much will you be ordering _________________ PCS Application Product Model ID _______________________ Audio Video Telecom LCD Databank Caller ID LCD Game Industrials Home Appliance Office Automation Remocon Other Please describe in detail its application ________________________...

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