rtd cpuModule CMX147786HX, User Manual

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CMX147786HX RTD Embedded Technologies, Inc.
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06 RTC Day of the Week
07 RTC Day of the Month
08 RTC Month
09 RTC Year
0A RTC Status Register A
• Bit 7: RTC Update In Progress (Read Only) - RTC regis-
ters should not be accessed when this bit is high.
• Bits 6-4: Divider for 32.768 KHz input (should always be
010)
• Bits 3-0: Rate select for periodic interrupt.
0B RTC Status Register B
• Bit 7: Inhibit Update - When high, the RTC is prevented
from updating.
• Bit 6: Periodic Interrupt Enable - When high, the RTC
IRQ will be asserted by the periodic interrupt.
• Bit 5: Alarm Interrupt Enable - When high, the RTC IRQ
will be asserted when the current time matches the alarm
time.
• Bit 4: Update Ended Interrupt Enable - When high, the
RTC IRQ will be asserted every time the RTC updates
(once per second).
• Bit 3: Square Wave Enable - Not used.
• Bit 2: Data Mode - Sets the data format of the RTC clock/
calendar registers (0=BCD, 1=binary). This is typically
set to BCD mode.
• Bit 1: Hours Byte Format - Sets the hour byte to 12 or 24
hour time (0=12 hour, 1=24 hour). This is typically set to
24 hour mode.
• Bit 0: Daylight Savings Enable - When high, the RTC will
automatically update itself for Daylight Savings Time. It
is recommended to leave this bit low and let the operating
system manage time zones and DST.
0C RTC Status Register C (Read Only)
• Bit 7: IRQ Flag - Indicates that the Real Time Clock IRQ
is asserted. Goes high whenever one of the enabled inter-
rupt conditions in Register B occurs.
• Bit 6: Periodic Flag
• Bit 5: Alarm Flag
• Bit 4: Update Ended Flag
• Bit 3-0: Reserved
Reading this register will also clear any of the set flags (IRQ, Period-
ic, Alarm, Update Ended). Note that even if the interrupt source is not
enabled in Register B, the flags in Register C bits 4, 5, and 6 may still
be set.
0D RTC Status Register D
• Bit 7: Valid Time/Date (always reads 1)
• Bits 6-0: Reserved
Table 35: Real Time Clock Registers