CMX147786HX
RTD Embedded Technologies, Inc.
48
PC/104 Bus Termination
Termination of PC/104 bus signals is not recommended since this cpuModule incorporates source
termination on bus signals and may cause malfunctions of the cpuModule.
RESETDRV
O
This line, active high, is used to reset the devices on the bus, at power-
on or after a reset command.
SA0-19
O
Address bits 0 to 19: these lines are used to address the memory space
and the I/O space. SA0 is the least significant bit while SA19 is the most
significant bit.
SBHE*
O
This active-low signal indicates a transfer of the most significant data
byte (SD15-SD8).
SD8-15
I/O
Data bits: these are the high-byte data bus lines. SD8 is the least signif-
icant bit; SD15 the most significant bit.
SD0-7
I/O
Data bits: these are the low-byte data bus lines. SD0 is the least signifi-
cant bit; SD7 the most significant bit.
SMEMR*
O
Memory Read command, active low.
SMEMW*
O
Memory Write command, active low.
SYSCLK
O
System Clock, 8.0MHz with a 50% duty cycle. Only driven during ex-
ternal bus cycles.
TC
O
Terminal Count: this line is active high and indicates the conclusion of
a DMA transfer.
Table 26: PC/104 Bus Signals
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