± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr.
–
Ithaca, NY 14850
© 2019 Kionix
–
All Rights Reserved
tel: 607-257-1080 – fax:607-257-1146
894-12874-1907311402-0.17
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Page
39
of
73
1.19 LP_CNTL1 (0X3A)
Low Power Control 1: The Averaging Filter Control setting determines both - the number of internal acceleration samples
to be averaged in Low Power mode and the number of internal acceleration samples to be averaged for digital engines
operation (Directional-Tap
TM
/ Double-Tap
TM
, Tilt, Wake-Up, Back-to-Sleep, Free fall, Advanced Data Path) both in
High
Performance
and
Low Power
modes. In Low Power mode, this setting has a direct effect on power consumption and
noise performance and thus can be used to optimize the performance of the accelerometer. Note that to properly change
the value of this register, the PC1 bit in CNTL1 must first be set to “0”.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
AVC2
AVC1
AVC0
Reserved
Reserved
Reserved
Reserved
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
01000011
Address:
0x3A
AVC<2:0>
– Averaging Filter Control.
000 = No Averaging (requires IIR_BYPASS = 0 setting in ODCNTL register)
001 = 2 Samples Averaged
010 = 4 Samples Averaged
011 = 8 Samples Averaged
100 = 16 Samples Averaged (default)
101 = 32 Samples Averaged
110 = 64 Samples Averaged
111 = 128 Samples Averaged
Reserved
– these bits are reserved, and their values should not be changed.
1.20 LP_CNTL2 (0X3B)
Low Power Control 2: The advanced low power control setting reduces the power consumption of the KX134-1211 even
further in Low Power and Standby modes. Note: This setting cannot be used in Low Power mode if any of the following
digital engines is enabled: Advanced Data Path, Tap
TM
/Double-Tap
TM
, Free fall, or Tilt. This setting can be used with
Wake-up / Back-to-Sleep engines. This setting has no effect in High-performance mode. Note that to properly change
the value of this register, the PC1 bit in
CNTL1 must first be set to “0”.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LPSTPSEL
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
10011010
Address:
0x3B
LPSTPSEL
– Digital power shut-off select
LPSTPLEL = 0
– Digital power shut-off disabled (default)
LPSTPLEL = 1
– Digital power shut-off enabled.
Reserved
– these bits are reserved, and their values should not be changed.
