Rohm BU7963GUW Technical Notes Download Page 3 | Manualshive

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Technical Note

3/19

BU7963GUW

www.rohm.com

2010.04 - Rev.A

© 2010 ROHM Co., Ltd. All rights reserved.

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Block Diagram

I/F

Logic

Parallel

to

Serial

Odd

Parity

Timing

Generator

Tx

Reset

Generator

Clock

Detection

PLL

Tx

PCLK

Control

Control

Logic

Reference

PD[26:0]

PCLK

CKD

DRVR

XSD

LS[1:0]

RVS

POL_PCLK

PLL_BW

TEST[1:0]

MSVDD

DVDD

DGND

MSGND

High Speed I/F

D0-

D0+

D1-

D1+

D2-

D2+

CLK-

CLK+

Fig.2. Block Diagram

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Summary of Contents for BU7963GUW

Page 1: ...4 to 45MHz 4 Depending on the data transfer rate one two or three differential data channels can be selected Applications Serial Interface for LCD Display Interface of Mobile Devices Application Absol...

Page 2: ...A 2010 ROHM Co Ltd All rights reserved Package View Fig 1 Package View VBGA063W050 0 08 S 1PIN MARK 5 0 0 1 5 0 0 1 0 10 S 0 75 0 1 0 75 0 1 P 0 5 7 P 0 5 7 0 5 0 05 S AB M A H G F E D C B A 1 2 3 4...

Page 3: ...Block Diagram I F Logic Parallel to Serial Odd Parity Timing Generator Tx Reset Generator Clock Detection PLL Tx PCLK Control Control Logic Reference PD 26 0 PCLK CKD DRVR XSD LS 1 0 RVS POL_PCLK PLL_...

Page 4: ...D16 PD14 PD13 PD10 CKD B PCLK PD18 PD15 PD12 PD11 PD9 PD8 C PD22 PD20 PLL_BW DVDD N C RVS PD7 PD6 D PD23 PD21 N C DGND DGND DVDD PD4 PD5 E PD25 PD24 DVDD DGND MSGND N C PD1 PD3 F PD26 LS0 MSVDD MSGND...

Page 5: ...Schematic CLK 1 Analog O CLK pin When RVS L CLK When RVS H D1 Hi Z D CLK 1 Analog O CLK pin When RVS L CLK When RVS H D1 Hi Z D D0 1 Analog O D0 pin When RVS L D0 When RVS H D2 Hi Z D D0 1 Analog O D0...

Page 6: ...quivalent Schematic XSD 1 CMOS I Shutdown pin L shutdown H normal operation Input A LS0 1 CMOS I Selection of the number of data channel and the data format Refer to Selection of the number of MSDL3 c...

Page 7: ...15 0 120 450 L H 2 channel 8 0 30 0 240 900 H L 3 channel 12 0 45 0 360 1350 H H Inhibit setting MSDL3 Pin Assignment RVS determines the assignment of MSDL3 pins CLK CLK D0 D0 D1 D1 and D2 D2 Only th...

Page 8: ...olarity L Capture parallel data at falling edge H default Capture parallel data at rising edge PLL Bandwidth Selection BU7963GUW controls the range of the CLK CLK input frequency PCLK output frequency...

Page 9: ...UW is monitoring whether PCLK input is running or not and the link switches to Active Mode when PCLK running is detected 3 Active Mode BU7963GUW goes to Active Mode when XSD H and PCLK is running All...

Page 10: ...D1channel CLK channel PD26 PD25 PD24 PD19 PD20 PD21 PD22 PD23 PD18 PD15 PD16 PD17 PD13 PD14 PD12 PD11 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD0 PD1 PD2 PD26 PD14 Fig 8 MSDL3 Protocol for 2 channel Data 27...

Page 11: ...1 0 7 x DVDD DVDD V IO 1mA CKD pin Table 12 Current Consumption Ta 25 C DVDD MSVDD 1 80V and DGND MSGND 0 00V unless otherwise noted Parameter Symbol Limits Unit Conditions Min Typ Max Shutdown Curren...

Page 12: ...uency fTX_PCLK1 4 15 MHz LS0 L LS1 L fTX_PCLK2 8 30 MHz LS0 H LS1 L fTX_PCLK3 12 45 MHz LS0 L LS1 H PCLK Input Duty Cycle tTX_DUTY 33 67 Input Data Setup Time tTX_DS 5 0 ns POL_PCLK H Input Data Hold...

Page 13: ...BU7963GUW Fig 11 Serial Data input AC Timing Table 14 Serial Data input AC Timing Ta 25 C DVDD MSVDD 1 80V and DGND MSGND 0 00V unless otherwise noted Parameter Symbol Limits Unit Conditions Min Typ M...

Page 14: ...mbol Limits Unit Conditions Min Typ Max Core power supply startup time tTX_VDD_IOV 0 0 2 ms Reset Valid After Power Supplied tTX_VDD_XSD 10 s PCLK clock input startup time tTX_IN_VAL 10 s MSDL3 output...

Page 15: ...0V and DGND MSGND 0 00V unless otherwise noted Parameter Symbol Limits Unit Conditions Min Typ Max MSDL3 output delay time tTX_OUT_INV 100 s XSD hold time tTX_XSD_VDD 10 s Core power off time tTX_VDD_...

Page 16: ...D of Rx State1 State2 tTX_XSD_OUT tTX_XSD_CTL tTX_IN_XSD tTX_CTL_XSD tRX_CTL_XSD tRX_XSD_CTL Tx BU7963GUW Rx BU7964GUW Fig 14 Frequency Change Sequence Table 17 Frequency Change Sequence Ta 25 C DVDD...

Page 17: ...tx 200 500 ps Operating Frequency fopr_tx 225 MHz TX Hi Z State Leak Current ILEAK_TX 3 3 A Shutdown mode or standby mode OutP D0 D1 D2 Vcm_tx Single ended OutN D0 D1 D2 Differential OutP OutN Vdiff_t...

Page 18: ...10K 5 27 PLLBW1 PLLBW0 LS1 F_XS TEST 1 0 DGND DVDD MSGND MSVDD DVDD DGND 100p 2 0 1 2 MSGND MSVDD 100p 3 0 1 3 DVDD DGND 1 8V 1 8V 1 8V GND 1 8V GND CKD CPO D2 D2 D2 D2 100p 3 0 1 3 100p 2 0 1 2 1 8V...

Page 19: ...tiple of the minimum quantity Tape and Reel information Embossed carrier tape with dry pack Tape Quantity Direction of feed The direction is the 1pin of product is at the upper left when you hold reel...

Page 20: ...ical information The Products specified in this document are intended to be used with general use electronic equipment or devices such as audio visual equipment office automation equipment commu nicat...

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