Rohm BU7963GUW, Technical Notes

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Technical Note
12/19
BU7963GUW
www.rohm.com
2010.04 - Rev.A
© 2010 ROHM Co., Ltd. All rights reserved.
2) AC Characteristics
Parallel Data Input Timing
Fig.10 Parallel Data Input AC Timing
Table 13. Parallel Data Input AC Timing
Ta=25°C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted.
Parameter Symbol
Limits
Unit Conditions
Min Typ Max
PCLK Input Frequency
f
TX_PCLK1
4 - 15 MHz LS0=L, LS1=L
f
TX_PCLK2
8 - 30 MHz LS0=H, LS1=L
f
TX_PCLK3
12 - 45 MHz LS0=L, LS1=H
PCLK Input Duty Cycle t
TX_DUTY
33 - 67 %
Input Data Setup Time t
TX_DS
5.0 - - ns POL_PCLK=H
Input Data Hold Time t
TX_DH
5.0 - - ns POL_PCLK=H
Input Signal Rise Time 1 t
TX_R1
- - 10 ns PCLK Frequency
≦
30MHz
Input Signal Rise Time 2 t
TX_R2
- - 5 ns PCLK Frequency ＞ 30MHz
Input Signal Fall Time 1 t
TX_F1
- - 10 ns PCLK Frequency
≦
30MHz
Input Signal Fall Time 2 t
TX_F2
- - 5 ns PCLK Frequency ＞ 30MHz
PD[26:0]
PCLK
t
TX_DS
t
TX_DH
0.7×DVDD
0.3×DVDD
0.7×DVDD
0.3×DVDD
t
TX_R1/
t
TX_R2
t
TX_F1/
t
TX_F2