11/17
SYMBOL PARAMETER
TEST
CONDITIONS
LIMITS
UNIT
MIN. TYP.
(1)
MAX.
TMDS DIFFERENTIAL PINS (Y/Z)
t
PLH
Propagation delay time
low-high-level output
See Figure 5-2, AV
CC
= 3.3V,
R
T
= 50
Ω
- 480 - ps
t
PHL
Propagation delay time
low-high-level output
- 500 - ps
t
r
Differential output signal rise
time (20%-80%)
- 150 - ps
t
f
Differential output signal fall
time (20%-80%)
- 150 - ps
t
sk(p)
Pulse skew (
|
t
PHL
- t
PLH
|
) -
20
-
ps
t
sk(D)
Intra-pair differential skew,
see Figure 5-3.
- 50 - ps
t
sk(o)
Inter-pair channel-to-channel
output skew
- 50 - ps
t
sk(pp)
Part to part skew
-
400
-
ps
DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK)
t
pdLHTR
(DDC)
Propagation delay time,
low-to-high-level output
Tx to Rx
R
L
= 4.7k
Ω
C
L
= 100pF
- 650 - ns
t
pdHLTR
(DDC)
Propagation delay time,
high-to-low-level output
Tx to Rx
- 200 - ns
t
pdLHRT
(DDC)
Propagation delay time,
low-to-high-level output
Rx to Tx
R
L
= 1.67k
Ω
C
L
= 400pF
- 500 - ns
t
pdHLRT
(DDC)
Propagation delay time,
high-to-low-level output
Rx to Tx
- 350 - ns
tr Tx
(DDC)
Tx output Rise time
R
L
= 4.7k
Ω
C
L
= 100pF
- 800 - ns
tf Tx
(DDC)
Tx output Fall time
-
150
-
ns
tr Rx
(DDC)
Rx output Rise time
R
L
= 1.67k
Ω
C
L
= 400pF
- 950 - ns
tf Rx
(DDC)
Rx output Fall time
-
50
-
ns
t
sx
Select to switch output
-
8
-
ns
t
dis
Disable
time
-
5
-
ns
t
en
Enable
time
-
7
-
ns
t
sx(DDC)
Switch time from SCLn to
SCL_SINK
C
L
=10pF -
800
-
Ns
STATUS PINS (HPD1,HPD2,HPD3)
t
pdLH(HPD)
Propagation delay time,
low-to-high-level output from
HPD_SINK to HPDn(n=1,2,3)
C
L
=10pF -
5
-
ns
t
pdHL(HPD)
Propagation delay time,
high-to-low-level output
from
HPD_SINK to HPDn(n=1,2,3)
C
L
=10pF -
5
-
ns
t
sx(HPD)
Switch time from port select to
the latest valid status of HPD
C
L
=10pF -
8
-
ns
Note:
1. All typical values are at 25
℃
and with a 3.3V supply.
