Technical Note
5/20
BH1730FVC
www.rohm.com
2012.02 - Rev.A
© 2012 ROHM Co., Ltd. All rights reserved.
●
I
2
C Bus Access and Write / Read format
1 ) I
2
C Bus interface timing chart
Write measurement command and Read measurement result are done by I
2
C Bus interface. Please refer the formally
specification of I
2
C Bus interface, and follow the formally timing chart.
2) Main write Format
1. Case of “Write to Command Register”
ST
Slave Address
0101001
W
0
ACK
Data to Command Register
1XXXXXXX
ACK
SP
2. Case of “Write to Data Register”
ST
Slave Address
0101001
W
0
ACK
Data specified at register address field
0XXXXXXX
ACK
Data specified at register address
field +1
ACK
・・・
ACK
Data specified at register address
field +N
ACK
SP
※
The register address that set in Command register is used.
3. Case of "write to data register after write to Command Register"
ST
Slave Address
0101001
W
0
ACK
Data to Command Register
1XXXXXXX
ACK
Data specified at register address
field
ACK
・・・
ACK
Data specified at register address
field +N
ACK
SP
3) Main read Format
ST
Slave Address
0101001
R
1
ACK
Data specified at register address field
ACK
Data specified at register
address field +1
ACK
・・・
ACK
Data specified at register
address field +N
NACK
SP
※
The register address that set in Command register is used.
※
BH1730FVC operates as I
2
C bus slave device.
※
Please refer formality I
2
C bus specification of NXP semiconductor
BH1730FVC continues to write or read data with address increments until master issues stop condition.
Read cycle is 00h - 01h - 02h - 03h - 04h - 05h - 06h – 07h – 12h – 14h – 15h – 16h – 17h - 00h ………
from master to slave
from slave to master
t
HD ; DAT
S
SDA
SCL
t
HD ; STA
t
LOW
t
f
t
r
t
Sr
t
SU ; STA
t
SU ; DAT
t
f
HD
t
SU;STO
t
BUF
P
t
r
S
t
HIGH
t
HD ; STA
