Technical Note
19/30
BD5446EFV
www.rohm.com
2010.05 - Rev.B
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3) Clock stop protection
This IC has the clock stop protection circuit that make the speaker output mute when the SYS_CLK signal of the digital
audio input stops.
Detecting condition - It will detect when MUTE pin is set High and the SYS_CLK signal stops for about 1usec or more.
The speaker output is muted through a soft-mute when detected.
Releasing condition - It will release when MUTE pin is set High and the SYS_CLK signal returns to the normal clock
operation. The speaker output is outputted through a soft-start when released.
OUT1P (50, 51pin)
SYS_CLK (7pin)
Speaker output
ERROR (24pin)
OUT_DAC2 (22pin)
OUT_DAC1 (23pin)
Clock stop
Clock recover
HiZ-Low
Protection start with
about 1μsec clock stop.
3.3V
Unstable
OUT1N (43, 44pin)
OUT2N (38, 39pin)
OUT2P (31, 32pin)
t
t
t
t
t
Soft-start
43msec(fs=48kHz)
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