Technical Note
12/30
BD5446EFV
www.rohm.com
2010.05 - Rev.B
© 2010 ROHM Co., Ltd. All rights reserved.
●
Input digital audio signal sampling frequency (fs) explanation
PWM sampling frequency, Soft-start, Soft-mute time, and the detection time of the DC voltage protection in the speaker
depends on sampling frequency (fs) of the digital audio input.
Sampling frequency of the
digital audio input
(fs)
PWM sampling frequency
(fpwm)
Soft-start / Soft-mute time
DC voltage protection in
the speaker detection time
32kHz 512kHz 64msec.
64msec.
44.1kHz 705.6kHz 46msec. 46msec.
48kHz 768kHz 43msec.
43msec.
●
For voltage gain (Gain setting)
BD5446EFV prescribe voltage gain at speaker output (BTL output) under the definition 0dBV (1Vrms) as full scale input of
the digital audio input signal. For example, digital audio input signal = Full scale input, Gain setting = 20dB, Load resistance
R
L_SP
= 8
Ω
will give speaker output (BTL output) amplitude as Vo=10Vrms. (Output power Po = Vo
2
/R
L_SP
= 12.5W )
●
Speaker output and DAC output
Digital audio input signal SDATA1 will be output to the speaker. (SDATA2 will not be output to the speaker. DAC output can
be selected either from digital audio input signal SDATA1 or SDATA2.)
●
Format of digital audio input
・
SYS_CLK: It is System Clock input signal.
It will input LRCLK, BCLK, SDATA1 (SDATA2) that synchronizes with this clock that are 256 times of sampling frequency
(256fs).
・
LRCLK: It is L/R clock input signal.
It corresponds to 32kHz/44.1kHz/48kHz with those clock (fs) that are same to the sampling frequency (fs) .
The data of a left channel and a right channel for one sample is input to this section.
・
BCLK: It is Bit Clock input signal.
It is used for the latch of data in every one bit by sampling frequency’s 64 times sampling frequency (64fs).
・
SDATA1 & SDATA2: It is Data input signal.
It is amplitude data. The data length is different according to the resolution of the input digital audio data.
It corresponds to 16/ 20/ 24 bit.
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