C. DCU (DATA COMPRESSION UNIT)
C.1. OVERVIEW
The DCU receives scanned images in binary video data form from the image
processor (SIP3) on the SCU board and compresses the data using MH, MR,
or MMR, whichever is selected. The DCU sends the compressed data to the
SBC (Scan Buffer Controller) on the SCU board.
C.2. FEATURES
For high speed processing, the input/output data processing in the DCU is
16-bit. To make the DCU compact, the FPGA is used for both data input and
output processing.
C.3. BLOCK DIAGRAM
8-bit to 16-bit
Converter
8-bit to 16-bit
Converter
FIFO 1
5k x 8 bits
FIFO 2
5k x 8 bits
SBC
DRAM
4 Mbits x 2
Address
Decoder
Selector
Selector
DICEP-E1
I/O Controller
(FPGA)
Function
Register
A0 - A7
D0 - D7
VDATA0 - VDATA7
VIDEO I/F
G404O501.WMF
Appendix C
October 9th, 1995
DCU (DATA COMPRESSION UNIT)
OVERVIEW
C-1