Renesas Starter Kit+, User Manual

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Renesas Starter Kit+ for RX72N 5. User Circuitry
R20UT4443EG0100 Rev. 1.00 Page 24 of 57
Nov 30, 19
5.12 SDRAM
The RX72N features an SDRAM controller. It is connected to SDRAM on the CPU board with a 16-bit width.
Table 5-14
gives an Overview of the onboard SDRAM.
Table 5-14: Overview of the onboard SDRAM
Specification Contents
Type name MT48LC8M16A2P-6A
Constitution 2Meg x 16 x 4 bank
Capacity 128Mbit
Row address 12bit
Column address 9bit
Number of banks 4
Auto refresh period (tRFC) Min. 60ns
Initialization auto refresh count 2
Precharge command period (tRP) Min. 18ns
Auto refresh request interval 15.625us (64ms/4096)
CAS latency (CL) 2 @SDCLK:80MHz
Write recovery period (tWR) Min. 12ns
ACTIVE-to-PRECHARGE command period (tRAS) 42ns - 120000ns
ACTIVE-to-READ or WRITE delay (tRCD) Min. 18ns
When accessing SDRAM on the CPU board, make the following settings regardless of the operating
frequency of the SDRAM clock. Table 5-15 shows the On-board SDRAM settings.
Table 5-15: On-board SDRAM settings
Register name Setting values Setting details
External Bus Control Register 3 (PFBCR3.SDCLKDRV) 0b0 Use the pin with the SDCLK set for a
frequency no higher than 60 MHz.
Drive Capacity Control Register (PORT6.DSCR) 0b0000000x Normal drive output
Drive Capacity Control Register 2 (PORT6.DSCR2)
Drive Capacity Control Register (PORT7.DSCR)
0bxxxxxxx0
Drive Capacity Control Register 2 (PORT7.DSCR2)
Drive Capacity Control Register (PORTA.DSCR)
0b0000000x
Drive Capacity Control Register 2 (PORTA.DSCR2)
Drive Capacity Control Register (PORTB.DSCR)
0bx0000000
Drive Capacity Control Register 2 (PORTB.DSCR2)
Drive Capacity Control Register (PORTD.DSCR)
0b00000000
Drive Capacity Control Register 2 (PORTD.DSCR2)
Drive Capacity Control Register (PORTE.DSCR)
Drive Capacity Control Register 2 (PORTE.DSCR2)