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Renesas SH7781 Hardware Manual Download Page 260

8. Caches

Rev.1.00 Jan. 10, 2008 Page 230 of 1658
REJ09B0261-0100

•

FLUSH transaction

When the operand cache is enabled, the FLUSH transaction checks the operand cache and if
the hit line is dirty, then the data is written back to the external memory. If the transaction is
not hit to the cache or the hit entry is not dirty, it is no-operation.

(3)

Changes in Instruction Specifications Regarding Coherency Control

Of the operand cache operating instructions, the coherency control-related specifications of OCBI,
OCBP, and OCBWB have been changed from those of the SH-4A with H'20-valued VER bits in
the processor version register (PVR).

•

Changes in the invalidate instruction OCBI@Rn

When Rn is designating an address in a non-cacheable area, this instruction is executed as
NOP in the SH-4A with H'20-valued VER bits in the processor version register (PVR). In this
LSI, this instruction invalidates the operand cache line designated by way = Rn[14:13] and
entry = Rn[12:5] provided that Rn[31:24] = H'F4 (OC address array area). In this process,
writing back of the line does not take place even if the line to be invalidated is dirty. This
operation is only executable in privileged mode, and an address error exception occurs in user
mode. TLB-related exceptions do not occur.

Do not execute this instruction to invalidate the memory-mapped array areas and control
register areas for which Rn[31:24] is not H'F4, and their reserved areas (H'F0 to H'F3, H'F5 to
H'FF).

•

Changes in the purge instruction OCBP@Rn

When Rn is designating an address in a non-cacheable area, this instruction is executed as
NOP in the SH-4A with H'20-valued VER bits in the processor version register (PVR). In this
LSI, this instruction invalidates the operand cache line designated by way = Rn[14:13] and
entry = Rn[12:5] provided that Rn[31:24] = H'F4 (OC address array area). In this process,
writing back of the line takes place when the line to be invalidated is dirty. This operation is
only executable in privileged mode, and an address error exception occurs in user mode. TLB-
related exceptions do not occur.

Do not execute this instruction to invalidate the memory-mapped array areas and control
register areas for which Rn[31:24] is not H'F4, and their reserved areas (H'F0 to H'F3, H'F5 to
H'FF).

•

Changes in the write-back instruction OCBWB@Rn

When Rn is designating an address in a non-cacheable area, this instruction is executed as
NOP in the SH-4A with H'20-valued VER bits in the processor version register (PVR). In this
LSI, provided that Rn[31:24] = H'F4 (OC address array area), this instruction writes back the
operand cache line designated by way = Rn[14:13] and entry = Rn[12:5] if it is dirty and clears

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Summary of Contents for SH7781

Page 1: ...Revision Date Jan 10 2008 32 Hardware Manual Renesas 32 Bit RISC Microcomputer SuperH RISC Engine Family SH7780 Series Rev 1 00 REJ09B0261 0100 SH7785 ...

Page 2: ...gh quality and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are considering the use of our products for such purposes please contact a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set ...

Page 3: ...e moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserve...

Page 4: ...Rev 1 00 Jan 10 2008 Page iv of xxx REJ09B0261 0100 ...

Page 5: ...l was written to explain the hardware functions and electrical characteristics of this LSI to the above users Notes on reading this manual In order to understand the overall functions of the chip Read the manual according to the contents This manual consists of parts on the CPU system control functions peripheral functions and electrical characteristics In order to understand individual instructio...

Page 6: ...ssing Unit DDR Double Data Rate DDRIF DDR SDRAM Interface DMA Direct Memory Access DMAC Direct Memory Access Controller FIFO First In First Out FPU Floating point Unit HAC Audio Codec H UDI User Debugging Interface INTC Interrupt Controller JTAG Joint Test Action Group LBSC Local Bus State Controller LRAM L Memory LRU Least Recently Used LSB Least Significant Bit MMCIF Multimedia Card Interface MM...

Page 7: ...roller PFC Pin Function Controller RISC Reduced Instruction Set Computer RTC Realtime Clock SCIF Serial Communication Interface with FIFO SIOF Serial Interface with FIFO SSI Serial Sound Interface TAP Test Access Port TLB Translation Lookaside Buffer TMU Timer Unit UART Universal Asynchronous Receiver Transmitter UBC User Break Controller WDT Watchdog Timer ...

Page 8: ...Rev 1 00 Jan 10 2008 Page viii of xxx REJ09B0261 0100 All trademarks and registered trademarks are the property of their respective owners ...

Page 9: ...ters 31 2 2 4 Control Registers 33 2 2 5 System Registers 35 2 3 Memory Mapped Registers 39 2 4 Data Formats in Registers 40 2 5 Data Formats in Memory 40 2 6 Processing States 41 2 7 Usage Notes 43 2 7 1 Notes on Self Modifying Code 43 Section 3 Instruction Set 45 3 1 Execution Environment 45 3 2 Addressing Modes 47 3 3 Instruction Set 52 Section 4 Pipelining 65 4 1 Pipelines 65 4 2 Parallel Exec...

Page 10: ...terrupts 120 5 6 4 Priority Order with Multiple Exceptions 121 5 7 Usage Notes 123 Section 6 Floating Point Unit FPU 125 6 1 Features 125 6 2 Data Formats 126 6 2 1 Floating Point Format 126 6 2 2 Non Numbers NaN 129 6 2 3 Denormalized Numbers 130 6 3 Register Descriptions 131 6 3 1 Floating Point Registers 131 6 3 2 Floating Point Status Control Register FPSCR 133 6 3 3 Floating Point Communicati...

Page 11: ... Configuration 170 7 4 2 Instruction TLB ITLB Configuration 173 7 4 3 Address Translation Method 174 7 5 MMU Functions 177 7 5 1 MMU Hardware Management 177 7 5 2 MMU Software Management 177 7 5 3 MMU Instruction LDTLB 178 7 5 4 Hardware ITLB Miss Handling 180 7 5 5 Avoiding Synonym Problems 181 7 6 MMU Exceptions 182 7 6 1 Instruction TLB Multiple Hit Exception 182 7 6 2 Instruction TLB Miss Exce...

Page 12: ...ess Control Register 0 QACR0 218 8 2 3 Queue Address Control Register 1 QACR1 219 8 2 4 On Chip Memory Control Register RAMCR 220 8 3 Operand Cache Operation 222 8 3 1 Read Operation 222 8 3 2 Prefetch Operation 223 8 3 3 Write Operation 224 8 3 4 Write Back Buffer 225 8 3 5 Write Through Buffer 225 8 3 6 OC Two Way Mode 226 8 4 Instruction Cache Operation 227 8 4 1 Read Operation 227 8 4 2 Prefet...

Page 13: ... 1 Instruction Fetch Access from the CPU 256 9 3 2 Operand Access from the CPU and Access from the FPU 256 9 3 3 Access from the SuperHyway Bus Master Module 257 9 3 4 OL Memory Block Transfer 257 9 4 On Chip Memory Protective Functions 260 9 5 Usage Notes 261 9 5 1 Page Conflict 261 9 5 2 Access Across Different Pages 261 9 5 3 On Chip Memory Coherency 261 9 5 4 Sleep Mode 262 9 6 Note on Using 3...

Page 14: ... Setting IRQ IRL 7 0 Pin Function 344 10 7 3 Clearing IRQ and IRL Interrupt Requests 345 Section 11 Local Bus State Controller LBSC 347 11 1 Features 347 11 2 Input Output Pins 350 11 3 Overview of Areas 354 11 3 1 Space Divisions 354 11 3 2 Memory Bus Width 357 11 3 3 PCMCIA Support 358 11 4 Register Descriptions 362 11 4 1 Memory Address Map Select Register MMSELR 364 11 4 2 Bus Control Register...

Page 15: ...Timing Register 0 DBTR0 488 12 4 6 SDRAM Timing Register 1 DBTR1 492 12 4 7 SDRAM Timing Register 2 DBTR2 495 12 4 8 SDRAM Refresh Control Register 0 DBRFCNT0 499 12 4 9 SDRAM Refresh Control Register 1 DBRFCNT1 500 12 4 10 SDRAM Refresh Control Register 2 DBRFCNT2 502 12 4 11 SDRAM Refresh Status Register DBRFSTS 504 12 4 12 DDRPAD Frequency Setting Register DBFREQ 505 12 4 13 DDRPAD DIC ODT OCD ...

Page 16: ...1 13 4 8 PCI Local Bus Basic Interface 653 Section 14 Direct Memory Access Controller DMAC 665 14 1 Features 665 14 2 Input Output Pins 667 14 3 Register Descriptions 668 14 3 1 DMA Source Address Registers 0 to 11 SAR0 to SAR11 675 14 3 2 DMA Source Address Registers B0 to B3 B6 to B9 SARB0 to SARB3 SARB6 to SARB9 676 14 3 3 DMA Destination Address Registers 0 to 11 DAR0 to DAR11 677 14 3 4 DMA D...

Page 17: ...egister Descriptions 739 15 4 1 Frequency Control Register 0 FRQCR0 741 15 4 2 Frequency Control Register 1 FRQCR1 742 15 4 3 Frequency Display Register 1 FRQMR1 745 15 4 4 PLL Control Register PLLCR 747 15 5 Calculating the Frequency 748 15 6 How to Change the Frequency 749 15 6 1 Changing the Frequency of Clocks Other than the Bus Clock 749 15 6 2 Changing the Bus Clock Frequency 749 15 7 Notes ...

Page 18: ...by Control Register 0 MSTPCR0 786 17 3 3 Standby Control Register 1 MSTPCR1 789 17 3 4 Standby Display Register MSTPMR 791 17 4 Sleep Mode 793 17 4 1 Transition to Sleep Mode 793 17 4 2 Releasing Sleep Mode 793 17 5 Deep Sleep Mode 794 17 5 1 Transition to Deep Sleep Mode 794 17 5 2 Releasing Deep Sleep Mode 795 17 6 Module Standby Functions 796 17 6 1 Transition to Module Standby Mode 796 17 6 2 ...

Page 19: ...r CPCR 857 19 3 7 Display Plane Priority Register DPPR 859 19 3 8 Display Unit Extensional Function Enable Register DEFR 862 19 3 9 Horizontal Display Start Register HDSR 864 19 3 10 Horizontal Display End Register HDER 865 19 3 11 Vertical Display Start Register VDSR 866 19 3 12 Vertical Display End Register VDER 867 19 3 13 Horizontal Cycle Register HCR 868 19 3 14 Horizontal Sync Width Register...

Page 20: ...Y Register PnSPYR n 1 to 6 908 19 3 42 Plane n Wrap Around Start Position Register PnWASPR n 1 to 6 909 19 3 43 Plane n Wrap Around Memory Width Register PnWAMWR n 1 to 6 910 19 3 44 Plane n Blinking Time Register PnBTR n 1 to 6 911 19 3 45 Plane n Transparent Color 1 Register PnTC1R n 1 to 6 912 19 3 46 Plane n Transparent Color 2 Register PnTC2R n 1 to 6 913 19 3 47 Plane n Memory Length Registe...

Page 21: ...ER 980 20 3 3 GA Interrupt Source Indicating Register GACISR 981 20 3 4 GA Interrupt Source Indication Clear Register GACICR 982 20 3 5 GA Interrupt Enable Register GACIER 983 20 3 6 GA CL Input Data Alignment Register DRCL_CTL 984 20 3 7 GA CL Output Data Alignment Register DWCL_CTL 985 20 3 8 GA MC Input Data Alignment Register DRMC_CTL 986 20 3 9 GA MC Output Data Alignment Register DWMC_CTL 98...

Page 22: ... MC Future Frame V Pointer Register MCFVPR 1012 20 4 GDTA Operation 1013 20 4 1 Explanation of CL Operation 1013 20 4 2 Explanation of MC Operation 1019 20 5 Interrupt Processing 1029 20 6 Data Alignment 1029 20 7 Usage Notes 1031 20 7 1 Regarding Module Stoppage 1031 20 7 2 Regarding Deep Sleep Modes 1031 20 7 3 Regarding Frequency Changes 1032 Section 21 Serial Communication Interface with FIFO ...

Page 23: ...4 Receive Data Register SIRDR 1109 22 3 5 Transmit Control Data Register SITCR 1110 22 3 6 Receive Control Data Register SIRCR 1111 22 3 7 Status Register SISTR 1112 22 3 8 Interrupt Enable Register SIIER 1118 22 3 9 FIFO Control Register SIFCTR 1120 22 3 10 Clock Select Register SISCR 1122 22 3 11 Transmit Data Assign Register SITDAR 1123 22 3 12 Receive Data Assign Register SIRDAR 1125 22 3 13 C...

Page 24: ...s 1171 24 2 Input Output Pins 1172 24 3 Register Descriptions 1173 24 3 1 Command Registers 0 to 5 CMDR0 to CMDR5 1177 24 3 2 Command Start Register CMDSTRT 1178 24 3 3 Operation Control Register OPCR 1179 24 3 4 Card Status Register CSTR 1181 24 3 5 Interrupt Control Registers 0 to 2 INTCR0 to INTCR2 1183 24 3 6 Interrupt Status Registers 0 to 2 INTSTR0 to INTSTR2 1187 24 3 7 Transfer Clock Contr...

Page 25: ...HACPCML 1275 25 3 5 PCM Right Channel Register HACPCMR 1277 25 3 6 TX Interrupt Enable Register HACTIER 1278 25 3 7 TX Status Register HACTSR 1279 25 3 8 RX Interrupt Enable Register HACRIER 1281 25 3 9 RX Status Register HACRSR 1282 25 3 10 HAC Control Register HACACR 1284 25 4 AC 97 Frame Slot Structure 1286 25 5 Operation 1288 25 5 1 Receiver 1288 25 5 2 Transmitter 1288 25 5 3 DMA 1289 25 5 4 ...

Page 26: ... Common Control Register FLCMNCR 1344 27 3 2 Command Control Register FLCMDCR 1346 27 3 3 Command Code Register FLCMCDR 1348 27 3 4 Address Register FLADR 1349 27 3 5 Address Register 2 FLADR2 1351 27 3 6 Data Counter Register FLDTCNTR 1352 27 3 7 Data Register FLDATAR 1353 27 3 8 Interrupt DMA Control Register FLINTDMACR 1354 27 3 9 Ready Busy Timeout Setting Register FLBSYTMR 1359 27 3 10 Ready ...

Page 27: ...PCR 1412 28 2 15 Port Q Control Register PQCR 1414 28 2 16 Port R Control Register PRCR 1416 28 2 17 Port A Data Register PADR 1418 28 2 18 Port B Data Register PBDR 1419 28 2 19 Port C Data Register PCDR 1420 28 2 20 Port D Data Register PDDR 1421 28 2 21 Port E Data Register PEDR 1422 28 2 22 Port F Data Register PFDR 1423 28 2 23 Port G Data Register PGDR 1424 28 2 24 Port H Data Register PHDR ...

Page 28: ...g Registers 0 and 1 CRR0 and CRR1 1463 29 2 3 Match Address Setting Registers 0 and 1 CAR0 and CAR1 1465 29 2 4 Match Address Mask Setting Registers 0 and 1 CAMR0 and CAMR1 1466 29 2 5 Match Data Setting Register 1 CDR1 1468 29 2 6 Match Data Mask Setting Register 1 CDMR1 1469 29 2 7 Execution Count Break Register 1 CETR1 1470 29 2 8 Channel Match Flag Register CCMFR 1471 29 2 9 Break Control Regi...

Page 29: ... DC Characteristics 1562 32 3 AC Characteristics 1567 32 3 1 Clock and Control Signal Timing 1568 32 3 2 Control Signal Timing 1572 32 3 3 Bus Timing 1574 32 3 4 DBSC2 Signal Timing 1592 32 3 5 INTC Module Signal Timing 1597 32 3 6 PCIC Module Signal Timing 1599 32 3 7 DMAC Module Signal Timing 1601 32 3 8 TMU Module Signal Timing 1602 32 3 9 SCIF Module Signal Timing 1603 32 3 10 H UDI Module Sig...

Page 30: ...ing of Unused Pins 1642 D Turning On and Off Power Supply 1653 D 1 Turning On and Off Between Each Power Supply Series 1653 D 2 Power On and Power Off Sequences for Power Supplies with Different Potentials in DDR2 SDRAM Power Supply Backup Mode 1654 D 3 Turning On and Off Between the Same Power Supply Series 1655 E Version Registers PVR PRR 1656 F Product Lineup 1657 ...

Page 31: ...H 3 and SH 4 microcomputers The CPU and FPU run at 600 MHz The processor also includes an instruction cache an operand cache for which copy back or write through mode is selectable a four entry fully associative instruction TLB translation look aside buffer and an MMU memory management unit with a 64 entry fully associative unified TLB 1 1 Features of the SH7785 The features of the SH7785 are list...

Page 32: ...H 4 processors Instruction length 16 bit fixed length for improved code efficiency Load store architecture Delayed branch instructions Conditional instruction execution Instruction set design based on the C language Super scalar architecture covering both the FPU and CPU provides for the simultaneous execution of any two instructions Instruction execution time Two instructions per cycle max Virtua...

Page 33: ... FPUL Supports FMAC multiply and accumulate instruction Supports FDIV divide and FSQRT square root instructions Supports FLDI0 FLDI1 load constants 0 and 1 instructions Instruction execution times Latency FADD FSUB 3 cycles single precision 5 cycles double precision Latency FMAC FMUL 5 cycles single precision 7 cycles double precision Pitch FADD FSUB 1 cycle single precision double precision Pitch...

Page 34: ...nstruction cache IC 32 Kbyte 4 way set associative 256 entries way 32 byte block length Operand cache OC 32 Kbyte 4 way set associative 256 entries way 32 byte block length Selectable write method copy back or write through Store queue 32 bytes 2 entries One stage copy back buffer and one stage write through buffer LRAM ILRAM 8 Kbyte high speed memory Three independent read write ports 8 16 32 64 ...

Page 35: ...ntroller INTC Nine independent external interrupts NMI and IRQ7 to IRQ0 NMI Falling rising edge selectable IRQ Falling rising edge or high level low level selectable 15 level encoded external interrupts IRL3 to IRL0 or IRL7 to IRL4 On chip module interrupts A priority level can be set for each module The following modules can issue on chip module interrupts TMU DU GDTA SCIF WDT H UDI DMAC HAC PCIC...

Page 36: ...gister values Number of units in burst transfers can be set by register values Connectable as area 0 1 2 3 4 5 or 6 Selectable bus width 64 32 16 8 bit MPX interface Address data multiplexing Connectable as area 1 or 4 Selectable bus widths 64 32 bit SRAM interface with byte control Connectable as area 1 or 4 Selectable bus width 64 32 16 bit PCMCIA interface only for little endian mode Wait cycle...

Page 37: ...val is selectable by a register setting Preceding refresh operations are performed when there are no pending requests Self refresh mode Connectable memory capacity Up to 1 Gbyte With a 32 bit bus width 16 M x 16 bits 256 Mbits x 2 32 M x 16 bits 512 Mbits x 2 64 M x 16 bits 1 Gbit x 2 128 M x 16 bits 2 Gbits x 2 32 M x 8 bits 256 Mbits x 4 64 M x 8 bits 512 Mbits x 4 128 M x 8 bits 1 Gbit x 4 256 ...

Page 38: ...Up to 64 Mbytes of PCI memory space 29 bit address mode Direct memory access controller DMAC Number of channels 12 12 channel physical address DMA controller Four channels support external requests channels 0 to 3 Address space 4 Gbytes Physical address Units of data transfer 8 16 or 32 bits 16 or 32 bytes Address modes Dual address mode Transfer requests External request on chip peripheral module...

Page 39: ...re function only on channel 2 Choice of a maximum of six input clock signals to drive counting external and peripheral clock signals Graphics data translation accelerator GDTA YUV data translation Translation mode YUYV mode YUV 4 2 0 YUV 4 2 2 ARGB mode YUV 4 2 0 ARGB8888 Motion Compensation processing Generation of estimated images using motion vectors in macroblock units 16 x 16 pixels Modes For...

Page 40: ...alettes one can be set for each layer Blending ratio setting Number of color palette planes with blending ratios Four α plane used in common with the display plane Digital RGB output 6 bit precision for each of R G and B Dot clock Can be switched between external input and internal clock division ratio from 1 to 32 Serial communications interface with FIFO SCIF Number of channels Six max On chip 6...

Page 41: ...pling rate 48 kHz On chip prescaler that uses the on chip peripheral clock Serial protocol interface HSPI Number of channels One max Supports full duplex operation Master slave mode Selectable bit rate generated by the on chip baud rate generator Multimedia card interface MMCIF Number of channels One max Supports a subset of version 3 1 of the multimedia card system specification Supports MMC mode...

Page 42: ...e overruns and underruns during access from the CPU or DMA General purpose I O GPIO General purpose I O port pins 111 Some GPIO pins are configurable as interrupts User break controller UBC Supports user break interrupts as a facility for debugging Two break channels Addresses data values types of access and widths of data are all specifiable as break conditions Supports a sequential break functio...

Page 43: ... bus 64 32 16 8 bit 100 MHz Local Bus Controller SRAM ROM PCMCIA MPX SCIF0 HSPI FLCTL Periperal bus Super Hyway CPG TMU WDT SRAM PCI Controller HAC SSI SIOF DMA Controller INTC Debug GDTA SCIF2 MMCIF Display Unit Peripheral Bus Controller DDR bus Local bus DDRII SDRAM Controller DBSC URAM 128 KB HAC SSI Note The PCI bus and the display unit are not available when the local bus width is 64 bits The...

Page 44: ...QS1 IO DDR data strobe 1 12 MDQ11 IO DDR data 11 39 MDQS2 IO DDR data strobe 2 13 MDQ12 IO DDR data 12 40 MDQS3 IO DDR data strobe 3 14 MDQ13 IO DDR data 13 41 MDQS0 IO DDR data strobe 0 antiphase 15 MDQ14 IO DDR data 14 42 MDQS1 IO DDR data strobe 1 antiphase 16 MDQ15 IO DDR data 15 43 MDQS2 IO DDR data strobe 2 antiphase 17 MDQ16 IO DDR data 16 44 MDQS3 IO DDR data strobe 3 antiphase 18 MDQ17 IO...

Page 45: ... 100 D25 IO Local bus data 25 69 MCAS O DDR column address select 101 D26 IO Local bus data 26 70 MWE O DDR write enable 102 D27 IO Local bus data 27 71 MODT O DDR on chip terminator 103 D28 IO Local bus data 28 72 MCKE O DDR clock enable 104 D29 IO Local bus data 29 73 MVREF I DDR reference voltage 105 D30 IO Local bus data 30 74 MBKPRST I DDR backup reset 106 D31 IO Local bus data 31 75 D0 IO Lo...

Page 46: ...data 0 Digital red 0 130 A23 O Local bus address 23 151 D33 AD1 DR1 IO IO O Local bus data 33 PCI address data 1 Digital red 1 131 A24 O Local bus address 24 152 D34 AD2 DR2 IO IO O Local bus data 34 PCI address data 2 Digital red 2 132 A25 O Local bus address 25 153 D35 AD3 DR3 IO IO O Local bus data 35 PCI address data 3 Digital red 3 133 CS0 O Chip select 0 154 D36 AD4 DR4 IO IO O Local bus dat...

Page 47: ...dress data 10 Digital green 4 173 D55 AD23 IO IO Local bus data 55 PCI address data 23 161 D43 AD11 DG5 IO IO O Local bus data 43 PCI address data 11 Digital green 5 174 D56 AD24 IO IO Local bus data 56 PCI address data 24 162 D44 AD12 DB0 IO IO O Local bus data 44 PCI address data 12 Digital blue 0 175 D57 AD25 IO IO Local bus data 57 PCI address data 25 163 D45 AD13 DB1 IO IO O Local bus data 45...

Page 48: ...put clock DU dot clock input 188 TRDY DISP IO O PCI target ready display period 206 INTA IO PCI interrupt A 189 IDSEL I PCI configuration device select 207 EXTAL I External input clock Crystal resonator 190 LOCK ODDF IO IO PCI lock even odd field 208 XTAL O Crystal resonator 191 DEVSEL DCLKOUT IO O PCI device select DU dot clock output 209 PRESET I Power on reset 192 PAR IO PCI parity 210 NMI I No...

Page 49: ...a NAND flash write enable 225 DACK2 SCIF2_TXD MMCCMD SIOF_TXD O O O I O O DMA channel 2 bus acknowledgment SCIF2 transmit data MMCIF command response SIOF transmit data 241 SCIF0_RXD HSPI_RX FRB I I I SCIF0 receive data HSPI receive data NAND flash ready or busy 226 DACK3 SCIF2_SCK MMCDAT SIOF_SCK O O IO IO IO DMA channel 3 bus acknowledgment SCIF2 serial clock MMCIF data SIOF serial clock 242 SCI...

Page 50: ...3 IRL7 FD7 I I IO Mode control 3 IRL interrupt request 7 NAND flash data 7 255 SCIF5_TXD HAC1_SYNC SSI1_WS O O IO SCIF5 transmit data HAC1 synchronous SSI1 serial bit clock 262 MODE4 SCIF3_TXD FCLE I O O Mode control 4 SCIF3 transmit data NAND flash command latch enable 256 SCIF5_RXD HAC1_SDIN SSI1_SCK I I IO SCIF5 receive data HAC1 serial data SSI1 serial data 263 MODE5 SIOF_MCLK I I Mode control...

Page 51: ...T IRQOUT O O Manual reset output Interrupt request output 270 MODE12 DRAK3 CE2B I O O Mode control 12 DMA channel 3 transfer request acknowledge 3 PCMCIA CE2B 275 THDAG Thermal diode 271 MODE13 TCLK IOIS16 I IO I TMU clock PCMCIA IOIS16 276 THDAS Thermal diode 272 MPMD I H UDI emulator mode 277 THDCD I Thermal diode 273 MODE14 I Mode control 14 278 THDCTL I Thermal diode Note This pin must be pull...

Page 52: ...QS 0 MDQS0 MDM0 MDQ5 VSS VDD R W CS3 A3 A2 A1 A0 MDQ12 VSS MDQ10 VDD DDR MDQ11 VSS VDD VSS VSS VSS VSS VSS VSS CS2 VDDQ D1 VSS D0 MDM1 MDQ14 MDQS 1 MDQS1 MDQ15 MDQ8 VSS VSS VSS VSS VSS VDD RD F RAME CS1 CS0 D4 D3 D2 AUDSYNC AUDAT A2 AUDAT A0 AUDAT A1 VDD DDR MDQ9 VDD VSS VSS VSS VSS VSS D12 D8 WE0 REG D7 D6 D5 AUDC K VSS AUDAT A3 VDDQ TDO VSS VSS VSS VSS VSS VSS VDD VSS D11 VDDQ D10 VSS D9 TCK TDI...

Page 53: ...3 D4 CS0 CS1 RD FRAME VDD VSS VSS VSS VSS VSS MDQ8 MDQ15 MDQS1 MDQS 1 MDQ14 MDM1 D5 D6 D7 WE0 REG D8 D12 VSS VSS VSS VSS VSS VDD MDQ9 VDD DDR AUDA TA1 AUDA TA0 AUDA TA2 AUDSY NC D9 VSS D10 VDDQ D11 VSS VDD VSS VSS VSS VSS VSS VSS TDO VDDQ AUDA TA3 VSS AUDCK D13 D14 D15 WE1 D16 MODE13 TCLK IOIS16 VSS VDD THDCD THDAS THDAG ASEBRK BRKACK TDI TCK D17 VDDQ D18 VSS BS VDDQ VDD VSS VDDQ TMS VSS TRST VDDQ...

Page 54: ...3 DBSC4 DBSC4 DBSC4 DBSC4 DBSC4 DBSC4 DBSC4 DBSC5 DBSC5 DBSC5 DBSC5 DBSC5 DBSC5 DBSC5 DBSC6 DBSC6 DBSC6 DBSC6 DBSC6 DBSC6 DBSC6 DBSC7 DBSC7 DBSC7 DBSC7 DBSC7 DBSC7 DBSC7 DBSC8 DBSC8 DBSC8 DBSC8 DBSC8 DBSC8 DBSC8 DBSC9 DBSC9 DBSC9 DBSC9 DBSC9 DBSC9 DBSC9 DBSC10 DBSC10 DBSC10 DBSC10 DBSC10 DBSC10 DBSC10 DBSC11 DBSC11 DBSC11 DBSC11 DBSC11 DBSC11 DBSC11 DBSC12 DBSC12 DBSC12 DBSC12 DBSC12 DBSC12 DBSC12...

Page 55: ... has registers and data formats as shown below 2 1 Data Formats The data formats supported in this LSI are shown in figure 2 1 Byte 8 bits Word 16 bits Longword 32 bits Single precision floating point 32 bits Double precision floating point 64 bits 0 7 0 15 0 31 0 31 30 22 s e f 0 63 62 51 s e f Legend s e f Sign field Exponent field Fraction field Figure 2 1 Data Formats ...

Page 56: ...ed the 16 registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 and non banked general registers R8 to R15 can be accessed as general registers R0 to R15 In this case the eight registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 are accessed by the LDC STC instructions When the RB bit is 0 that is when bank 0 is selected the 16 registers comprising bank 0 general regist...

Page 57: ...gisters FR0 FR15 and XF0 XF15 FR0 FR15 and XF0 XF15 can be assigned to either of two banks FPR0_BANK0 FPR15_BANK0 or FPR0_BANK1 FPR15_BANK1 FR0 FR15 can be used as the eight registers DR0 2 4 6 8 10 12 14 double precision floating point registers or pair registers or the four registers FV0 4 8 12 register vectors while XF0 XF15 can be used as the eight registers XD0 2 4 6 8 10 12 14 register pairs...

Page 58: ... 1111 reserved bits 0 others undefined GBR SSR SPC SGR DBR Undefined Control registers VBR H 00000000 MACH MACL PR Undefined System registers PC H A0000000 Floating point registers FR0 to FR15 XF0 to XF15 FPUL Undefined FPSCR H 00040001 Note Initialized by a power on reset and manual reset The CPU register configuration in each processing mode is shown in figure 2 2 User mode and privileged mode a...

Page 59: ...NK1 3 R3_BANK1 3 R4_BANK1 3 R5_BANK1 3 R6_BANK1 3 R7_BANK1 3 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0 1 4 R1_BANK0 4 R2_BANK0 4 R3_BANK0 4 R4_BANK0 4 R5_BANK0 4 R6_BANK0 4 R7_BANK0 4 c Register configuration in privileged mode RB 0 GBR MACH MACL VBR PR SR SSR PC SPC SGR DBR SGR DBR R0 is used as the index register in indexed register indirect addressing mode and indexed GBR indirect addressing mode ...

Page 60: ...7 in user mode SR MD 0 Allocated to R0 to R7 when SR RB 0 in privileged mode SR MD 1 R0_BANK1 to R7_BANK1 Cannot be accessed in user mode Allocated to R0 to R7 when SR RB 1 in privileged mode SR MD 0 or SR MD 1 SR RB 0 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R...

Page 61: ...15_BANK1 2 Single precision floating point registers FRi 16 registers When FPSCR FR 0 FR0 to FR15 are assigned to FPR0_BANK0 to FPR15_BANK0 when FPSCR FR 1 FR0 to FR15 are assigned to FPR0_BANK1 to FPR15_BANK1 3 Double precision floating point registers or single precision floating point registers DRi 8 registers A DR register comprises two FR registers DR0 FR0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 FR6 ...

Page 62: ...XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 DR0 DR2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 XD0 XMTRX XD2 XD4 XD6 XD8 XD10 XD12 XD14 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 XF0 XF1 XF2 XF3 XF4 X...

Page 63: ...ing mode 0 User mode Some instructions cannot be executed and some resources cannot be accessed 1 Privileged mode This bit is set to 1 by an exception or interrupt 29 RB 1 R W Privileged Mode General Register Bank Specification Bit 0 R0_BANK0 to R7_BANK0 are accessed as general registers R0 to R7 and R0_BANK1 to R7_BANK1 can be accessed using LDC STC instructions 1 R0_BANK1 to R7_BANK1 are accesse...

Page 64: ... this bit see General Precautions on Handling of Product 9 M 0 R W M Bit Used by the DIV0S DIV0U and DIV1 instructions 8 Q 0 R W Q Bit Used by the DIV0S DIV0U and DIV1 instructions 7 to 4 IMASK 1111 R W Interrupt Mask Level Bits An interrupt whose priority is equal to or less than the value of the IMASK bits is masked It can be chosen by CPU operation mode register CPUOPM whether the level of IMAS...

Page 65: ...Saved General Register 15 SGR 32 bits Privileged Mode Initial Value Undefined The contents of R15 are saved to SGR in the event of an exception or interrupt 7 Debug Base Register DBR 32 bits Privileged Mode Initial Value Undefined When the user break debugging function is enabled CBCR UBDE 1 DBR is referenced as the branch destination address of the user break handler instead of VBR 2 2 5 System R...

Page 66: ...gister Bank 0 FPR0_BANK0 to FPR15_BANK0 are assigned to FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1 are assigned to XF0 to XF15 1 FPR0_BANK0 to FPR15_BANK0 are assigned to XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1 are assigned to FR0 to FR15 20 SZ 0 R W Transfer Size Mode 0 Data size of FMOV instruction is 32 bits 1 Data size of FMOV instruction is a 32 bit register pair 64 bits For relationship bet...

Page 67: ...ield Each time an FPU operation instruction is executed the FPU exception cause field is cleared to 0 When an FPU exception occurs the bits corresponding to FPU exception cause field and flag field are set to 1 The FPU exception flag field remains set to 1 until it is cleared to 0 by software For bit allocations of each field see table 2 2 1 0 RM 01 R W Rounding Mode These bits select the rounding...

Page 68: ... not be used 2 The bit location of DR register is used for double precision format when PR 1 In the case of 2 it is used when PR is changed from 0 to 1 Figure 2 5 Relationship between SZ bit and Endian Table 2 2 Bit Allocation for FPU Exception Handling Field Name FPU Error E Invalid Operation V Division by Zero Z Overflow O Underflow U Inexact I Cause FPU exception cause field Bit 17 Bit 16 Bit 1...

Page 69: ...he TLB enables access to a memory mapped register The operation of an access to this area without using the address translation function of the MMU is not guaranteed H FC00 0000 to H FFFF FFFF Access to area H FC00 0000 to H FFFF FFFF in user mode will cause an address error Memory mapped registers can be referenced in user mode by means of access that involves address translation Note Do not acce...

Page 70: ...xtended before being loaded into a register A word operand must be accessed starting from a word boundary even address of a 2 byte unit address 2n and a longword operand starting from a longword boundary even address of a 4 byte unit address 4n An address error will result if this rule is not observed A byte operand can be accessed from any address Big endian or little endian byte order can be sel...

Page 71: ...he reset state is divided into the power on reset state and the manual reset In the power on reset state the internal state of the CPU and the on chip peripheral module registers are initialized In the manual reset state the internal state of the CPU and some registers of on chip peripheral modules are initialized For details see register descriptions for each section 2 Instruction Execution State...

Page 72: ...00 From any state when reset manual reset input Reset state Instruction execution state Sleep instruction execution Power down state Interrupt occurence Reset manual reset clearance Reset manual reset input Reset manual reset input Figure 2 8 Processing State Transitions ...

Page 73: ...or the ICBI instruction can be any address within the range where no address error exception occurs 2 When the Codes to be Modified are in Cacheable Area Write Through SYNCO ICBI Rn All instruction cache areas corresponding to the modified codes should be invalidated by the ICBI instruction The ICBI instruction should be issued to each cache line One cache line is 32 bytes 3 When the Codes to be M...

Page 74: ...2 Programming Model Rev 1 00 Jan 10 2008 Page 44 of 1658 REJ09B0261 0100 ...

Page 75: ... At the start of instruction execution the PC indicates the address of the instruction itself 2 Load Store Architecture This LSI has a load store architecture in which operations are basically executed using registers Except for bit manipulation operations such as logical AND that are executed directly in memory operands in an operation that requires memory access are loaded into registers and the...

Page 76: ...s not changed by ADD operation CMP EQ R1 R0 If R0 R1 T bit is set to 1 BT TARGET Branches to TARGET if T bit 1 R0 R1 In an RTE delay slot the SR bits are referenced as follows In instruction access the MD bit is used before modification and in data access the MD bit is accessed after modification The other bits S T M Q FD BL and RB after modification are used for delay slot instruction execution T...

Page 77: ...nagement Unit MMU Table 3 2 Addressing Modes and Effective Addresses Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula Register direct Rn Effective address is register Rn Operand is register Rn contents Register indirect Rn Effective address is register Rn contents Rn Rn Rn EA EA effective address Register indirect with post increment Rn Effective address ...

Page 78: ...n 1 2 4 Rn 1 2 4 8 Rn 1 2 4 Byte Rn 1 Rn Word Rn 2 Rn Longword Rn 4 Rn Quadword Rn 8 Rn Rn EA Instruction executed with Rn after calculation Register indirect with displacement disp 4 Rn Effective address is register Rn contents with 4 bit displacement disp added After disp is zero extended it is multiplied by 1 byte 2 word or 4 longword according to the operand size Rn Rn disp 1 2 4 1 2 4 disp ze...

Page 79: ...p 1 2 4 disp zero extended Byte GBR disp EA Word GBR disp 2 EA Longword GBR disp 4 EA Indexed GBR indirect R0 GBR Effective address is sum of register GBR and R0 contents GBR R0 GBR R0 GBR R0 EA PC relative with displacement disp 8 PC Effective address is PC 4 with 8 bit displacement disp added After disp is zero extended it is multiplied by 2 word or 4 longword according to the operand size With ...

Page 80: ... 8 bit displacement disp added after being sign extended and multiplied by 2 2 disp sign extended 4 PC PC 4 disp 2 PC 4 disp 2 Branch Target PC relative disp 12 Effective address is PC 4 with 12 bit displacement disp added after being sign extended and multiplied by 2 2 disp sign extended 4 PC PC 4 disp 2 PC 4 disp 2 Branch Target Rn Effective address is sum of PC 4 and Rn PC 4 Rn PC 4 Rn PC 4 Rn ...

Page 81: ...ediate data imm of TRAPA instruction is zero extended and multiplied by 4 Note For the addressing modes below that use a displacement disp the assembler descriptions in this manual show the value before scaling 1 2 or 4 is performed according to the operand size This is done to clarify the operation of the LSI Refer to the relevant assembler notation rules for the actual assembler descriptions dis...

Page 82: ...mediate data disp Displacement Operation notation Transfer direction xx Memory operand M Q T SR flag bits Logical AND of individual bits Logical OR of individual bits Logical exclusive OR of individual bits Logical NOT of individual bits n n n bit shift Instruction code MSB LSB mmmm Register number Rm FRm nnnn Register number Rn FRn 0000 R0 FR0 0001 R1 FR1 1111 R15 FR15 mmm Register number DRm XDm...

Page 83: ... W disp PC Rn disp 2 PC 4 sign extension Rn 1001nnnndddddddd MOV L disp PC Rn disp 4 PC H FFFF FFFC 4 Rn 1101nnnndddddddd MOV Rm Rn Rm Rn 0110nnnnmmmm0011 MOV B Rm Rn Rm Rn 0010nnnnmmmm0000 MOV W Rm Rn Rm Rn 0010nnnnmmmm0001 MOV L Rm Rn Rm Rn 0010nnnnmmmm0010 MOV B Rm Rn Rm sign extension Rn 0110nnnnmmmm0000 MOV W Rm Rn Rm sign extension Rn 0110nnnnmmmm0001 MOV L Rm Rn Rm Rn 0110nnnnmmmm0010 MOV B...

Page 84: ...1 MOV L R0 Rm Rn R0 Rm Rn 0000nnnnmmmm1110 MOV B R0 disp GBR R0 disp GBR 11000000dddddddd MOV W R0 disp GBR R0 disp 2 GBR 11000001dddddddd MOV L R0 disp GBR R0 disp 4 GBR 11000010dddddddd MOV B disp GBR R0 disp GBR sign extension R0 11000100dddddddd MOV W disp GBR R0 disp 2 GBR sign extension R0 11000101dddddddd MOV L disp GBR R0 disp 4 GBR R0 11000110dddddddd MOVA disp PC R0 disp 4 PC H FFFF FFFC...

Page 85: ... imm Rn 0111nnnniiiiiiii ADDC Rm Rn Rn Rm T Rn carry T 0011nnnnmmmm1110 Carry ADDV Rm Rn Rn Rm Rn overflow T 0011nnnnmmmm1111 Overflow CMP EQ imm R0 When R0 imm 1 T Otherwise 0 T 10001000iiiiiiii Comparison result CMP EQ Rm Rn When Rn Rm 1 T Otherwise 0 T 0011nnnnmmmm0000 Comparison result CMP HS Rm Rn When Rn Rm unsigned 1 T Otherwise 0 T 0011nnnnmmmm0010 Comparison result CMP GE Rm Rn When Rn Rm...

Page 86: ...1 DMULU L Rm Rn Unsigned Rn Rm MAC 32 32 64 bits 0011nnnnmmmm0101 DT Rn Rn 1 Rn when Rn 0 1 T When Rn 0 0 T 0100nnnn00010000 Comparison result EXTS B Rm Rn Rm sign extended from byte Rn 0110nnnnmmmm1110 EXTS W Rm Rn Rm sign extended from word Rn 0110nnnnmmmm1111 EXTU B Rm Rn Rm zero extended from byte Rn 0110nnnnmmmm1100 EXTU W Rm Rn Rm zero extended from word Rn 0110nnnnmmmm1101 MAC L Rm Rn Signe...

Page 87: ...n Instruction Code Privileged T Bit New AND Rm Rn Rn Rm Rn 0010nnnnmmmm1001 AND imm R0 R0 imm R0 11001001iiiiiiii AND B imm R0 GBR R0 GBR imm R0 GBR 11001101iiiiiiii NOT Rm Rn Rm Rn 0110nnnnmmmm0111 OR Rm Rn Rn Rm Rn 0010nnnnmmmm1011 OR imm R0 R0 imm R0 11001011iiiiiiii OR B imm R0 GBR R0 GBR imm R0 GBR 11001111iiiiiiii TAS B Rn When Rn 0 1 T Otherwise 0 T In both cases 1 MSB of Rn 0100nnnn0001101...

Page 88: ...000101 LSB ROTCL Rn T Rn T 0100nnnn00100100 MSB ROTCR Rn T Rn T 0100nnnn00100101 LSB SHAD Rm Rn When Rm 0 Rn Rm Rn When Rm 0 Rn Rm MSB Rn 0100nnnnmmmm1100 SHAL Rn T Rn 0 0100nnnn00100000 MSB SHAR Rn MSB Rn T 0100nnnn00100001 LSB SHLD Rm Rn When Rm 0 Rn Rm Rn When Rm 0 Rn Rm 0 Rn 0100nnnnmmmm1101 SHLL Rn T Rn 0 0100nnnn00000000 MSB SHLR Rn 0 Rn T 0100nnnn00000001 LSB SHLL2 Rn Rn 2 Rn 0100nnnn000010...

Page 89: ...anch Rn PC 4 PC 0000nnnn00100011 BSR label Delayed branch PC 4 PR disp 2 PC 4 PC 1011dddddddddddd BSRF Rn Delayed branch PC 4 PR Rn PC 4 PC 0000nnnn00000011 JMP Rn Delayed branch Rn PC 0100nnnn00101011 JSR Rn Delayed branch PC 4 PR Rn PC 0100nnnn00001011 RTS Delayed branch PR PC 0000000000001011 Table 3 9 System Control Instructions Instruction Operation Instruction Code Privileged T Bit New CLRMA...

Page 90: ...DBR Rm 4 Rm 0100mmmm11110110 Privileged LDC L Rm Rn_ BANK Rm Rn_BANK Rm 4 Rm 0100mmmm1nnn0111 Privileged LDS Rm MACH Rm MACH 0100mmmm00001010 LDS Rm MACL Rm MACL 0100mmmm00011010 LDS Rm PR Rm PR 0100mmmm00101010 LDS L Rm MACH Rm MACH Rm 4 Rm 0100mmmm00000110 LDS L Rm MACL Rm MACL Rm 4 Rm 0100mmmm00010110 LDS L Rm PR Rm PR Rm 4 Rm 0100mmmm00100110 LDTLB PTEH PTEL PTEA TLB 0000000000111000 Privilege...

Page 91: ..._BANK Rn Rm_BANK Rn m 0 to 7 0000nnnn1mmm0010 Privileged STC L SR Rn Rn 4 Rn SR Rn 0100nnnn00000011 Privileged STC L GBR Rn Rn 4 Rn GBR Rn 0100nnnn00010011 STC L VBR Rn Rn 4 Rn VBR Rn 0100nnnn00100011 Privileged STC L SSR Rn Rn 4 Rn SSR Rn 0100nnnn00110011 Privileged STC L SPC Rn Rn 4 Rn SPC Rn 0100nnnn01000011 Privileged STC L SGR Rn Rn 4 Rn SGR Rn 0100nnnn00110010 Privileged STC L DBR Rn Rn 4 Rn...

Page 92: ...1nnnn10001101 FLDI1 FRn H 3F80 0000 FRn 1111nnnn10011101 FMOV FRm FRn FRm FRn 1111nnnnmmmm1100 FMOV S Rm FRn Rm FRn 1111nnnnmmmm1000 FMOV S R0 Rm FRn R0 Rm FRn 1111nnnnmmmm0110 FMOV S Rm FRn Rm FRn Rm 4 Rm 1111nnnnmmmm1001 FMOV S FRm Rn FRm Rn 1111nnnnmmmm1010 FMOV S FRm Rn Rn 4 Rn FRm Rn 1111nnnnmmmm1011 FMOV S FRm R0 Rn FRm R0 Rn 1111nnnnmmmm0111 FMOV DRm DRn DRm DRn 1111nnn0mmm01100 FMOV Rm DRn...

Page 93: ...RC FRm FPUL long FRm FPUL 1111mmmm00111101 Table 3 11 Floating Point Double Precision Instructions Instruction Operation Instruction Code Privileged T Bit New FABS DRn DRn H 7FFF FFFF FFFF FFFF DRn 1111nnn001011101 FADD DRm DRn DRn DRm DRn 1111nnn0mmm00000 FCMP EQ DRm DRn When DRn DRm 1 T Otherwise 0 T 1111nnn0mmm00100 Comparison result FCMP GT DRm DRn When DRn DRm 1 T Otherwise 0 T 1111nnn0mmm001...

Page 94: ...ation Instruction Code Privileged T Bit New FMOV DRm XDn DRm XDn 1111nnn1mmm01100 FMOV XDm DRn XDm DRn 1111nnn0mmm11100 FMOV XDm XDn XDm XDn 1111nnn1mmm11100 FMOV Rm XDn Rm XDn 1111nnn1mmmm1000 FMOV Rm XDn Rm XDn Rm 8 Rm 1111nnn1mmmm1001 FMOV R0 Rm XDn R0 Rm XDn 1111nnn1mmmm0110 FMOV XDm Rn XDm Rn 1111nnnnmmm11010 FMOV XDm Rn Rn 8 Rn XDm Rn 1111nnnnmmm11011 FMOV XDm R0 Rn XDm R0 Rn 1111nnnnmmm1011...

Page 95: ... ID E1 E2 E3 WB 1 General Pipeline Instruction fetch Instruction decode Issue Register read Write back Operation Forwarding Address calculation 2 General Load Store Pipeline 3 Special Pipeline 4 Special Load Store Pipeline 5 Floating Point Pipeline 6 Floating Point Extended Pipeline Instruction fetch Instruction decode Issue Operation Write back Operation Operation Register read Forwarding Operati...

Page 96: ...on Description E1 E2 E3 WB CPU EX pipe is occupied S1 S2 S3 WB CPU LS pipe is occupied with memory access s1 s2 s3 WB CPU LS pipe is occupied without memory access E1 S1 Either CPU EX pipe or CPU LS pipe is occupied E1S1 E1s1 Both CPU EX pipe and CPU LS pipe are occupied M2 M3 MS CPU MULT operation unit is occupied FE1 FE2 FE3 FE4 FE5 FE6 FS FPU EX pipe is occupied FS1 FS2 FS3 FS4 FS FPU LS pipe i...

Page 97: ...e cycle 0 to 3 branch cycles 1 2 JSR JMP BRAF BSRF 1 issue cycle 4 branch cycles Branch destination instruction 1 3 RTS 1 issue cycle 0 to 4 branch cycles 1 4 RTE 4 issue cycles 2 branch cycles It is 15 cycles to the ID stage in the first instruction of exception handler 1 5 TRAPA 8 issue cycles 5 cycles 2 branch cycle It is not constant cycles to the clock halted period 1 6 SLEEP 2 issue cycles B...

Page 98: ...on EX type 1 issue cycle 2 2 1 step operation LS type 1 issue cycle 2 3 1 step operation MT type 1 issue cycle 2 4 MOV MT type 1 issue cycle EXT SU BW MOVT SWAP XTRCT ADD CMP DIV DT NEG SUB AND AND NOT OR OR TST TST XOR XOR ROT SHA SHL CLRS CLRT SETS SETT MOV NOP MOVA MOV Note Except for AND OR TST and XOR instructions using GBR relative addressing mode Figure 4 2 Instruction Execution Patterns 2 ...

Page 99: ...ID I2 I3 I1 I2 I3 ID s1 s2 s3 WB E1s1 E1s1 E1s1 E2s2 E2s2 E2s2 E3s3 E3s3 E3s3 WB WB WB I1 ID I2 I3 ID ID ID ID ID ID ID ID ID ID 3 1 Load store 1 issue cycle 3 2 AND B OR B XOR B TST B 3 issue cycles 3 3 TAS B 4 issue cycles 3 4 PREF OCBI OCBP OCBWB MOVCA L SYNCO 1 issue cycle MOV BWL MOV BWL d GBR 3 5 LDTLB 1 issue cycle 3 6 ICBI 8 issue cycles 5 cycles 4 branch cycle 3 7 PREFI 5 issue cycles 5 c...

Page 100: ...2 ID S1 S2 S3 WB I1 ID I2 I3 I1 ID I2 I3 ID ID ID ID ID ID 4 1 LDC to Rp_BANK SSR SPC VBR 1 issue cycle 4 2 LDC to DBR SGR 4 issue cycles 4 3 LDC to GBR 1 issue cycle 4 4 LDC to SR 4 issue cycles 4 branch cycles 4 5 LDC L to Rp_BANK SSR SPC VBR 1 issue cycle 4 6 LDC L to DBR SGR 4 issue cycles 4 7 LDC L to GBR 1 issue cycle 4 8 LDC L to SR 6 issue cycles 4 branch cycles Branch to the next instruct...

Page 101: ...e cycle 4 10 STC from SR 1 issue cycle 4 11 STC L from DBR GBR Rp_BANK SSR SPC VBR SGR 1 issue cycle 4 12 STC L from SR 1 issue cycle 4 13 LDS to PR 1 issue cycle 4 14 LDS L to PR 1 issue cycle 4 15 STS from PR 1 issue cycle 4 16 STS L from PR 1 issue cycle 4 17 BSRF BSR JSR delay slot instructions PR set 0 issue cycle The value of PR is changed in the E3 stage of delay slot instruction When the S...

Page 102: ...B MS I1 I2 ID S1 S2 S3 WB MS I1 I2 ID S1 S2 S3 WB MS M2 M3 MS M2 M3 MS M2 M3 I1 I2 ID S1 S2 S3 WB S1 S2 S3 WB ID ID 5 1 LDS to MACH L 1 issue cycle 5 2 LDS L to MACH L 1 issue cycle 5 3 STS from MACH L 1 issue cycle 5 4 STS L from MACH L 1 issue cycle 5 5 MULS W MULU W 1 issue cycle 5 6 DMULS L DMULU L MUL L 1 issue cycle 5 7 CLRMAC 1 issue cycle 5 8 MAC W 2 issue cycle 5 9 MAC L 2 issue cycle Fig...

Page 103: ... s1 s2 s3 I1 I2 ID WB S1 S2 S3 WB FS1 FS2 FS3 FS4 S1 S2 S3 WB FS1 FS2 FS3 FS4 FS s1 s2 s3 WB I1 I2 ID I1 I2 ID I1 I2 ID I1 I2 ID I1 I2 ID I1 I2 ID s1 s2 s3 FS 6 1 LDS to FPUL 1 issue cycle 6 2 STS from FPUL 1 issue cycle 6 3 LDS L to FPUL 1 issue cycle 6 4 STS L from FPUL 1 issue cycle 6 5 LDS to FPSCR 1 issue cycle 6 6 STS from FPSCR 1 issue cycle 6 7 LDS L to FPSCR 1 issue cycle 6 8 STS L from F...

Page 104: ...6 FS FS I1 I2 I3 ID FS 6 12 Single precision FABS FNEG double precision FABS FNEG 1 issue cycle 6 13 FLDI0 FLDI1 1 issue cycle 6 14 Single precision floating point computation 1 issue cycle 6 15 Single precision FDIV FSQRT 1 issue cycle 6 16 Double precision floating point computation 1 issue cycle 6 17 Double precision floating point computation 1 issue cycle 6 18 Double precision FDIV FSQRT 1 is...

Page 105: ...5 FE6 FS FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 I1 I2 I3 ID FE1 FE2 FE1 FE2 FE3 FE4 FE5 FE6 FS FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 FS FS 6 19 FIPR 1 issue cycle 6 20 FTRV 1 issue cycle 6 21 FSRRA 1 issue cycle 6 22 FSCA 1 issue cycle Function computing unit occupied cycle Function computing unit occupied cycle Figure 4 2 Instruction Execution Patterns 9 ...

Page 106: ...CLRS CLRT CMP DIV0S DIV0U DIV1 DMUS L DMULU L DT EXTS EXTU MOVT MUL L MULS W MULU W NEG NEGC NOT OR imm R0 OR Rm Rn ROTCL ROTCR ROTL ROTR SETS SETT SHAD SHAL SHAR SHLD SHLL SHLL2 SHLL8 SHLL16 SHLR SHLR2 SHLR8 SHLR16 SUB SUBC SUBV SWAP TST imm R0 TST Rm Rn XOR imm R0 XOR Rm Rn XTRCT MT MOV imm Rn MOV Rm Rn NOP BR BF BF S BRA BRAF BSR BSRF BT BT S JMP JSR RTS LS FABS FNEG FLDI0 FLDI1 FLDS FMOV adr F...

Page 107: ...ess SR1 MACH MACL PR SR2 FPUL FPSCR CR1 GBR Rp_BANK SPC SSR VBR CR2 CR1 DBR SGR FR FRm FRn DRm DRn XDm XDn The parallel execution of two instructions can be carried out under following conditions 1 Both addr preceding instruction and addr 2 following instruction are specified within the minimum page size 1 Kbyte 2 The execution of these two instructions is supported in table 4 3 Combination of Pre...

Page 108: ...61 0100 Table 4 3 Combination of Preceding and Following Instructions Preceding Instruction addr EX MT BR LS FE CO EX No Yes Yes Yes Yes MT Yes Yes Yes Yes Yes Following Instruction addr 2 BR Yes Yes No Yes Yes LS Yes Yes Yes No Yes FE Yes Yes Yes Yes No CO No ...

Page 109: ...D S1 S2 S3 WB MS S2 S3 WB S1 ID M3 M2 FE1 FE2 FE3 FE4 FE5 FE6 FE1 FE2 FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 FS I1 I2 I3 ID I1 I2 I3 ID FS FE3 FE4 FE5 FE6 FS 1 Issue Rate Issue rate 3 Issue rates indicates the issue period between one instruction and next instruction E g AND B instruction Next instruction Issue rate 2 E g MAC W instruction Execution cycles indicates ...

Page 110: ... 9 MOV L disp PC Rn LS 1 1 3 1 10 MOV B Rm Rn LS 1 1 3 1 11 MOV W Rm Rn LS 1 1 3 1 12 MOV L Rm Rn LS 1 1 3 1 13 MOV B Rm Rn LS 1 1 3 1 14 MOV W Rm Rn LS 1 1 3 1 15 MOV L Rm Rn LS 1 1 3 1 16 MOV B disp Rm R0 LS 1 1 3 1 17 MOV W disp Rm R0 LS 1 1 3 1 18 MOV L disp Rm Rn LS 1 1 3 1 19 MOV B R0 Rm Rn LS 1 1 3 1 20 MOV W R0 Rm Rn LS 1 1 3 1 21 MOV L R0 Rm Rn LS 1 1 3 1 22 MOV B disp GBR R0 LS 1 1 3 1 2...

Page 111: ...BR LS 1 1 3 1 39 MOV L R0 disp GBR LS 1 1 3 1 40 MOVCA L R0 Rn LS 1 1 3 4 41 MOVCO L R0 Rn CO 1 1 3 9 42 MOVLI L Rm R0 CO 1 1 3 8 43 MOVUA L Rm R0 LS 2 2 3 10 44 MOVUA L Rm R0 LS 2 2 3 10 45 MOVT Rn EX 1 1 2 1 46 OCBI Rn LS 1 1 3 4 47 OCBP Rn LS 1 1 3 4 48 OCBWB Rn LS 1 1 3 4 49 PREF Rn LS 1 1 3 4 50 SWAP B Rm Rn EX 1 1 2 1 51 SWAP W Rm Rn EX 1 1 2 1 Data transfer instructions 52 XTRCT Rm Rn EX 1 ...

Page 112: ...1 69 DMULS L Rm Rn EX 1 2 5 6 70 DMULU L Rm Rn EX 1 2 5 6 71 DT Rn EX 1 1 2 1 72 MAC L Rm Rn CO 2 5 5 9 73 MAC W Rm Rn CO 2 4 5 8 74 MUL L Rm Rn EX 1 2 5 6 75 MULS W Rm Rn EX 1 1 5 5 76 MULU W Rm Rn EX 1 1 5 5 77 NEG Rm Rn EX 1 1 2 1 78 NEGC Rm Rn EX 1 1 2 1 79 SUB Rm Rn EX 1 1 2 1 80 SUBC Rm Rn EX 1 1 2 1 Fixed point arithmetic instructions 81 SUBV Rm Rn EX 1 1 2 1 82 AND Rm Rn EX 1 1 2 1 83 AND ...

Page 113: ...Rn EX 1 1 2 1 99 ROTCR Rn EX 1 1 2 1 100 SHAD Rm Rn EX 1 1 2 1 101 SHAL Rn EX 1 1 2 1 102 SHAR Rn EX 1 1 2 1 103 SHLD Rm Rn EX 1 1 2 1 104 SHLL Rn EX 1 1 2 1 105 SHLL2 Rn EX 1 1 2 1 106 SHLL8 Rn EX 1 1 2 1 107 SHLL16 Rn EX 1 1 2 1 108 SHLR Rn EX 1 1 2 1 109 SHLR2 Rn EX 1 1 2 1 110 SHLR8 Rn EX 1 1 2 1 Shift instructions 111 SHLR16 Rn EX 1 1 2 1 112 BF disp BR 1 0 to 2 1 1 1 113 BF S disp BR 1 0 to ...

Page 114: ...EX 1 1 2 1 130 PREFI Rn CO 5 5 3 10 3 7 131 SYNCO CO Undefined Undefined 3 4 132 TRAPA imm CO 8 5 1 13 1 5 133 RTE CO 4 1 4 1 4 134 SLEEP CO Undefined Undefined 1 6 135 LDTLB CO 1 1 3 5 136 LDC Rm DBR CO 4 4 4 2 137 LDC Rm SGR CO 4 4 4 2 138 LDC Rm GBR LS 1 1 4 3 139 LDC Rm Rp_BANK LS 1 1 4 1 140 LDC Rm SR CO 4 3 4 4 4 141 LDC Rm SSR LS 1 1 4 1 142 LDC Rm SPC LS 1 1 4 1 143 LDC Rm VBR LS 1 1 4 1 1...

Page 115: ...159 STC SGR Rn LS 1 1 4 9 160 STC GBR Rn LS 1 1 4 9 161 STC Rp_BANK Rn LS 1 1 4 9 162 STC SR Rn CO 1 1 4 10 163 STC SSR Rn LS 1 1 4 9 164 STC SPC Rn LS 1 1 4 9 165 STC VBR Rn LS 1 1 4 9 166 STC L DBR Rn LS 1 1 4 11 167 STC L SGR Rn LS 1 1 4 11 168 STC L GBR Rn LS 1 1 4 11 169 STC L Rp_BANK Rn LS 1 1 4 11 170 STC L SR Rn CO 1 1 4 12 171 STC L SSR Rn LS 1 1 4 11 172 STC L SPC Rn LS 1 1 4 11 173 STC ...

Page 116: ...FPUL LS 1 1 6 10 190 FSTS FPUL FRn LS 1 1 6 11 191 FABS FRn LS 1 1 6 12 192 FADD FRm FRn FE 1 1 6 14 193 FCMP EQ FRm FRn FE 1 1 6 14 194 FCMP GT FRm FRn FE 1 1 6 14 195 FDIV FRm FRn FE 1 14 6 15 196 FLOAT FPUL FRn FE 1 1 6 14 197 FMAC FR0 FRm FRn FE 1 1 6 14 198 FMUL FRm FRn FE 1 1 6 14 199 FNEG FRn LS 1 1 6 12 200 FSQRT FRn FE 1 30 6 15 201 FSUB FRm FRn FE 1 1 6 14 202 FTRC FRm FPUL FE 1 1 6 14 2...

Page 117: ... 6 18 221 FSUB DRm DRn FE 1 1 6 16 Double precision floating point instructions 222 FTRC DRm FPUL FE 1 1 6 16 223 LDS Rm FPUL LS 1 1 6 1 224 LDS Rm FPSCR LS 1 1 6 5 225 LDS L Rm FPUL LS 1 1 6 3 226 LDS L Rm FPSCR LS 1 1 6 7 227 STS FPUL Rn LS 1 1 6 2 228 STS FPSCR Rn LS 1 1 6 6 229 STS L FPUL Rn LS 1 1 6 4 FPU system control instructions 230 STS L FPSCR Rn LS 1 1 6 8 231 FMOV DRm XDn LS 1 1 6 9 23...

Page 118: ...l Category No Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 241 FRCHG FE 1 1 6 14 242 FSCHG FE 1 1 6 14 243 FPCHG FE 1 1 6 14 244 FSRRA FRn FE 1 1 6 21 Graphics acceleration instructions 245 FSCA FPUL DRn FE 1 3 6 22 246 FTRV XMTRX FVn FE 1 4 6 20 ...

Page 119: ...on handling routine in order to support such functions is given the generic name of exception handling The exception handling in this LSI is of three kinds resets general exceptions and interrupts 5 2 Register Descriptions Table 5 1 lists the configuration of registers related exception handling Table 5 1 Register Configuration Register Name Abbr R W P4 Address Area 7 Address Access Size TRAPA exc...

Page 120: ... immediate data imm for the TRAPA instruction TRA is set automatically by hardware when a TRAPA instruction is executed TRA can also be modified by software 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value R R R R R R R R R R R R R R R R R W R W R W TRACODE R W R W R W R R R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0...

Page 121: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Initial value R R R R R R R R R R R R R R R R R W R W EXPCODE R W R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 R R R R R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 12 All 0 R Reserved For details on reading writing this bit...

Page 122: ...6 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value R R R R R R R R R R R R R R R R R W INTCODE R W R W R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 R R R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 14 All 0 R Reserved For details on reading writing this bit see General Precautions on Handling of Pr...

Page 123: ... IC OC memory mapped associative write operations According to the value of EXPMASK functions 1 and 2 can generate a slot illegal instruction exception and 3 can generate a data address error exception Generation of each exception can be disabled by writing 1 to the corresponding bit in EXPMASK However it is recommended that the above functions should not be used when making a program to maintain ...

Page 124: ... Mapped Cache Associative Write Operation 3 2 All 0 R Reserved For details on reading writing these bits see General Precautions on Handling of Product 1 BRDSSLP 1 R W Delay Slot SLEEP Instruction 0 The SLEEP instruction in the delay slot is disabled The SLEEP instruction is taken as a slot illegal instruction 1 The SLEEP instruction in the delay slot is enabled 0 RTEDS 1 R W RTE Delay Slot 0 An i...

Page 125: ...respectively 2 The block bit BL in SR is set to 1 3 The mode bit MD in SR is set to 1 4 The register bank bit RB in SR is set to 1 5 In a reset the FPU disable bit FD in SR is cleared to 0 6 The exception code is written to bits 11 to 0 of the exception event register EXPEVT or interrupt event register INTEVT 7 When the interrupt mode switch bit INTMU in CPUOPM has been 1 the interrupt mask level ...

Page 126: ...struction execution 1 2 0 VBR DBR H 100 H 1E0 Instruction address error 2 1 VBR H 100 H 0E0 Instruction TLB miss exception 2 2 VBR H 400 H 040 Instruction TLB protection violation exception 2 3 VBR H 100 H 0A0 General illegal instruction exception 2 4 VBR H 100 H 180 Slot illegal instruction exception 2 4 VBR H 100 H 1A0 General FPU disable exception 2 4 VBR H 100 H 800 Slot FPU disable exception ...

Page 127: ...after instruction execution 2 10 VBR DBR H 100 H 1E0 Nonmaskable interrupt 3 VBR H 600 H 1C0 Interrupt Completion type General interrupt request 4 VBR H 600 Notes 1 When UBDE in CBCR 1 PC DBR In other cases PC VBR H 100 2 Priority is first assigned by priority level then by priority order within each level the lowest number represents the highest priority 3 Control passes to H A000 0000 in a reset...

Page 128: ...priority order of the different kinds of exceptions reset general exception and interrupt Register settings in the event of an exception are shown only for SSR SPC SGR EXPEVT INTEVT SR and PC However other registers may be set automatically by hardware depending on the exception For details see section 5 6 Description of Exceptions Also see section 5 6 4 Priority Order with Multiple Exceptions for...

Page 129: ...eption code SR MD RB BL 111 SR IMASK received interuupt level PC CBCR UBDE 1 User_Break DBR VBR Offset Interrupt requested General exception requested Reset requested EXPEVT exception code SR MD RB BL FD IMASK 11101111 PC H A000 0000 Note When the exception of the highest priority is an interrupt Whether IMASK is updated or not can be set by software Accepted interrupt level is B 1111 for NMI Figu...

Page 130: ... instruction is accepted before that for a later instruction An example of the order of acceptance for general exceptions is shown in figure 5 2 I1 I1 ID ID E3 WB WB TLB miss data access Pipeline flow Order of detection Instruction n Instruction n 1 General illegal instruction exception instruction n 1 and TLB miss instruction n 2 are detected simultaneously Order of exception handling TLB miss in...

Page 131: ...pending and is accepted after the BL bit has been cleared to 0 by software If a nonmaskable interrupt NMI occurs it can be held pending or accepted according to the setting made by software For further details refer to the hardware manual of the product Thus normally SPC and SSR are saved and then the BL bit in SR is cleared to 0 to enable multiple exception state acceptance 5 5 4 Return from Exce...

Page 132: ...be executed when power is supplied 2 Manual Reset Condition Manual reset request Operations Exception code H 020 is set in EXPEVT initialization of the CPU and on chip peripheral module is carried out and then a branch is made to the branch vector H A0000000 The registers initialized by a power on reset and manual reset are different For details see the register descriptions in the relevant sectio...

Page 133: ...al module initialization is performed in the same way as in a manual reset For details see the register descriptions in the relevant sections 5 Data TLB Multiple Hit Exception Source Multiple UTLB address matches Transition address H A0000000 Transition operations The virtual address 32 bits at which this exception occurred is set in TEA and the corresponding virtual page number 22 bits is set in ...

Page 134: ...e ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 040 for a read access or H 060 for a write access is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0400 To speed up TLB miss processing the offset is separat...

Page 135: ...10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 40 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0400 To speed up TLB miss processing the offset is separate from that of othe...

Page 136: ...al page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 080 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Initial_write_exception TEA EX...

Page 137: ...ible Read write access possible Table 5 5 UTLB Protection Information TLB Extended Mode EPR 5 Read Permission in Privileged Mode 0 Read access possible 1 Read access not possible EPR 4 Write Permission in Privileged Mode 0 Write access possible 1 Write access not possible EPR 2 Read Permission in User Mode 0 Read access possible 1 Read access not possible EPR 1 Write Permission in User Mode 0 Writ...

Page 138: ...tents at this time are saved in SGR Exception code H 0A0 for a read access or H 0C0 for a write access is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Data_TLB_protection_violation_exception TEA EXCEPTION_ADDRESS PTEH VPN PAGE_NUMBER SPC PC SSR SR SGR R15 EXPEVT read_access H 0000 00A0 H 0000 00C0 SR MD 1 SR RB 1 SR BL 1 PC VBR H 0000 0100 ...

Page 139: ... Rn access by ICBI possible 00 Execution of instructions not possible EPR 2 EPR 0 Execution Permission in User Mode 11 01 Execution of instructions possible 10 Instruction fetch not possible Execution of Rn access by ICBI possible 00 Execution of instructions not possible Transition address VBR H 00000100 Transition operations The virtual address 32 bits at which this exception occurred is set in ...

Page 140: ...1 4n 2 or 4n 3 Except MOVLIA Quadword data access from other than a quadword data boundary 8n 1 8n 2 8n 3 8n 4 8n 5 8n 6 or 8n 7 Access to area H 80000000 to H FFFFFFFF in user mode Areas H E0000000 to H E3FFFFFF and H E5000000 to H E5FFFFFF can be accessed in user mode For details see section 7 Memory Management Unit MMU and section 9 On Chip Memory The MMCAW bit in EXPMASK is 0 and the IC OC mem...

Page 141: ...contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0E0 for a read access or H 100 for a write access is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 For details see section 7 Memory Management Unit MMU Data_address_error TEA EXCEPTION_ADDRESS PTEH VPN ...

Page 142: ...ption occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in the SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0E0 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a br...

Page 143: ...tion following the TRAPA instruction are saved in SPC The value of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR The 8 bit immediate value in the TRAPA instruction is multiplied by 4 and the result is set in TRA 9 0 Exception code H 160 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 TRAPA_exception SPC PC 2 SSR SR SGR R1...

Page 144: ...TE LDTLB SLEEP but excluding LDC STC instructions that access GBR Transition address VBR H 00000100 Transition operations The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 180 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Operation is ...

Page 145: ...ess GBR Decoding of a PC relative MOV instruction or MOVA instruction in a delay slot The BRDSSLP bit in EXPMASK is 0 and the SLEEP instruction in the delay slot is executed The RTEDS bit in EXPMASK is 0 and an instruction other than the NOP instruction in the delay slot is executed Transition address VBR H 000 0100 Transition operations The PC contents for the preceding delayed branch instruction...

Page 146: ...e saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 800 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Note FPU instructions are instructions in which the first 4 bits of the instruction code are F but excluding undefined instruction H FFFD and the LDS STS LDS L and STS L instructions corresponding to FPUL and FPSC...

Page 147: ...Transition operations The PC contents for the preceding delayed branch instruction are saved in SPC The SR and R15 contents when this exception occurred are saved in SSR and SGR Exception code H 820 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Slot_fpu_disable_exception SPC PC 2 SSR SR SGR R15 EXPEVT H 0000 0820 SR MD 1 SR RB 1 SR BL 1 PC VBR H 00...

Page 148: ...are set in SPC In the case of a pre execution break the PC contents for the instruction at which the breakpoint is set are set in SPC The SR and R15 contents when the break occurred are saved in SSR and SGR Exception code H 1E0 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 It is also possible to branch to PC DBR For details of PC etc when a data br...

Page 149: ...100 Transition operations The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 120 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 FPU_exception SPC PC SSR SR SGR R15 EXPEVT H 0000 0120 SR MD 1 SR RB 1 SR BL 1 PC VBR H 0000 0100 ...

Page 150: ...rity level When the BL bit in SR is 1 a software setting can specify whether this interrupt is to be masked or accepted When the INTMU bit in CPUOPM is 1 and the NMI interrupt is accessed B 1111 is set to IMASK bit in SR For details see section 10 Interrupt Controller INTC NMI SPC PC SSR SR SGR R15 INTEVT H 0000 01C0 SR MD 1 SR RB 1 SR BL 1 If cond SR IMASK B 1111 PC VBR H 0000 0600 2 General Inte...

Page 151: ...ble pair comprising a delayed branch instruction and delay slot instruction multiple exceptions occur Care is required in these cases as the exception priority order differs from the normal order 1 Instructions that Make Two Accesses to Memory With MAC instructions memory to memory arithmetic logic instructions TAS instructions and MOVUA instructions two data transfers are performed by a single in...

Page 152: ... check is performed for the completion type exception of priority level 2 in the delayed branch instruction 4 A check is performed for the completion type exception of priority level 2 in the delay slot instruction 5 A check is performed for priority level 3 in the delayed branch instruction and priority level 3 in the delay slot instruction There is no priority ranking between these two 6 A check...

Page 153: ...e held pending or accepted according to the setting made by software In sleep or standby mode however an interrupt is accepted even if the BL bit in SR is set to 1 3 SPC when an Exception Occurs A Re execution type general exception The PC value for the instruction at which the exception occurred is set in SPC and the instruction is re executed after returning from the exception handling routine I...

Page 154: ...t of the RTE instruction 5 Changing the SR Register Value and Accepting Exception A When the MD or BL bit in the SR register is changed by the LDC instruction the acceptance of the exception is determined by the changed SR value starting from the next instruction In the completion type exception an exception is accepted after the next instruction has been executed However an interrupt of completio...

Page 155: ...ation modes Flush to Zero and Treat Denormalized Number Six exception sources FPU Error Invalid Operation Divide By Zero Overflow Underflow and Inexact Comprehensive instructions Single precision double precision graphics support and system control In the SH 4A the following three instructions are added on to the instruction set of the SH 4 FSRRA FSCA and FPCHG When the FD bit in SR is set to 1 th...

Page 156: ... 1 and 6 2 31 s e f 30 23 22 0 Figure 6 1 Format of Single Precision Floating Point Number 63 s e f 62 52 51 0 Figure 6 2 Format of Double Precision Floating Point Number The exponent is expressed in biased form as follows e E bias The range of unbiased exponent E is Emin 1 to Emax 1 The two values Emin 1 and Emax 1 are distinguished as follows Emin 1 indicates zero both positive and negative sign...

Page 157: ...loating point number value v is determined as follows If E Emax 1 and f 0 v is a non number NaN irrespective of sign s If E Emax 1 and f 0 v 1 s infinity positive or negative infinity If Emin E Emax v 1 s 2E 1 f normalized number If E Emin 1 and f 0 v 1 s 2Emin 0 f denormalized number If E Emin 1 and f 0 v 1 s 0 positive or negative zero Table 6 2 shows the ranges of the various numbers in hexadec...

Page 158: ... to H 0010 0000 0000 0000 Positive denormalized number H 007F FFFF to H 0000 0001 H 000F FFFF FFFF FFFF to H 0000 0000 0000 0001 Positive zero H 0000 0000 H 0000 0000 0000 0000 Negative zero H 8000 0000 H 8000 0000 0000 0000 Negative denormalized number H 8000 0001 to H 807F FFFF H 8000 0000 0000 0001 to H 800F FFFF FFFF FFFF Negative normalized number H 8080 0000 to H FF7F FFFF H 8010 0000 0000 0...

Page 159: ...egisters FABS and FNEG that generates a floating point value When the EN V bit in FPSCR is 0 the operation result output is a qNaN When the EN V bit in FPSCR is 1 an invalid operation exception will be generated In this case the contents of the operation destination register are unchanged Following three instructions are used as transfer instructions between registers FMOV FRm FRn FLDS FRm FPUL FS...

Page 160: ...on field as a non zero value When the DN bit in FPSCR of the FPU is 1 a denormalized number source operand or operation result is always positive or negative zero in a floating point operation that generates a value an operation other than transfer instructions between registers FNEG or FABS When the DN bit in FPSCR is 0 a denormalized number source operand or operation result is processed as it i...

Page 161: ...SCR FR 0 FR0 to FR15 are allocated to FPR0_BANK0 to FPR15_BANK0 when FPSCR FR 1 FR0 to FR15 are allocated to FPR0_BANK1 to FPR15_BANK1 3 Double precision floating point registers DRi 8 registers A DR register comprises two FR registers DR0 FR0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 FR6 FR7 DR8 FR8 FR9 DR10 FR10 FR11 DR12 FR12 FR13 DR14 FR14 FR15 4 Single precision floating point vector registers FVi 4 re...

Page 162: ...XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 DR0 DR2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 XD0 XMTRX XD2 XD4 XD6 XD8 XD10 XD12 XD14 FPR0 BANK1 FPR1 BANK1 FPR2 BANK1 FPR3 BANK1 FPR4 BANK1 FPR5 BANK1 FPR6 BANK1 FPR7 BANK1 FPR8 BANK1 FPR9 BANK1 FPR10 BANK1 FPR11 BANK1 FPR12 BANK1 FPR13 BANK1 FPR14 BANK1 FPR15 BANK1 XF0 XF1 XF2 XF3 X...

Page 163: ...ter Bank 0 FPR0_BANK0 to FPR15_BANK0 are assigned to FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1 are assigned to XF0 to XF15 1 FPR0_BANK0 to FPR15_BANK0 are assigned to XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1 are assigned to FR0 to FR15 20 SZ 0 R W Transfer Size Mode 0 Data size of FMOV instruction is 32 bits 1 Data size of FMOV instruction is a 32 bit register pair 64 bits For relations between e...

Page 164: ...d Each time an FPU operation instruction is executed the FPU exception cause field is cleared to 0 When an FPU exception occurs the bits corresponding to FPU exception cause field and flag field are set to 1 The FPU exception flag field remains set to 1 until it is cleared to 0 by software For bit allocations of each field see table 6 3 1 0 RM1 RM0 0 1 R W R W Rounding Mode These bits select the r...

Page 165: ...FR 2i 1 4n 4m 4n 3 4m 3 63 0 63 32 31 0 DR 2i FR 2i 1 FR 2i 8n 4 8n 7 8n 3 8n 63 0 63 32 31 0 1 SZ 0 2 SZ 1 PR 0 63 0 63 0 DR 2i FR 2i 1 FR 2i 8n 8n 3 8n 7 8n 4 63 0 63 32 31 0 3 SZ 1 PR 1 63 0 1 2 2 Notes 1 In the case of SZ 0 and PR 0 DR register can not be used 2 The bit location of DR register is used for double precision format when PR 1 In the case of 2 it is used when PR is changed from 0 t...

Page 166: ...e field None Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Flag FPU exception flag field None Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 6 3 3 Floating Point Communication Register FPUL Information is transferred between the FPU and CPU via FPUL FPUL is a 32 bit system register that is accessed from the CPU side by means of LDS and STS instructions For example to convert the integer stored in general register R1 to a single...

Page 167: ... in FPSCR FPSCR RM 1 0 00 Round to Nearest FPSCR RM 1 0 01 Round to Zero 1 Round to Nearest The operation result is rounded to the nearest expressible value If there are two nearest expressible values the one with an LSB of 0 is selected If the unrounded value is 2Emax 2 2 P or more the result will be infinity with the same sign as the unrounded value The values of Emax and P respectively are 127 ...

Page 168: ...ion such as NaN input Division by zero Z Division with a zero divisor Overflow O When the operation result overflows Underflow U When the operation result underflows Inexact exception I When overflow underflow or rounding occurs The FPU exception cause field in FPSCR contains bits corresponding to all of above sources E V Z O U and I and the FPU exception flag and enable fields in FPSCR contain bi...

Page 169: ... assigned as the same exception event The meaning of an exception is determined by software by reading from FPSCR and interpreting the information it contains Also the destination register is not changed by any FPU exception handling operation If the FPU exception sources except for above are generated the bit corresponding to source V Z O U or I is set to 1 and a default value is generated as the...

Page 170: ...of multiplicand significant digits 1 MAX result value 2 23 2 149 The number of significant digits is 24 for a normalized number and 23 for a denormalized number number of leading zeros in the fractional part In a future version of the SH Series the above error is guaranteed but the same result between different processor cores is not guaranteed 1 FIPR FVm FVn m n 0 4 8 12 This instruction is basic...

Page 171: ...xecuting an FTRV instruction If the V bit is set in the FPU exception enable field FPU exception handling will be executed 3 FRCHG This instruction modifies banked registers For example when the FTRV instruction is executed matrix elements must be set in an array in the background bank However to create the actual elements of a translation matrix it is easier to use registers in the foreground ban...

Page 172: ...Point Unit FPU Rev 1 00 Jan 10 2008 Page 142 of 1658 REJ09B0261 0100 This instruction changes the value of the SZ bit in FPSCR enabling fast switching between use and non use of pair single precision data transfer ...

Page 173: ... physical address mapping ranges 29 bit address mode and 32 bit address extended mode are provided In view of flag functions of the MMU TLB compatible mode four paging sizes with four protection bits and TLB extended mode eight paging sizes with six protection bits are provided Selection between 29 bit address mode and 32 bit address extended mode is made by setting the relevant control register b...

Page 174: ...at allows a number of processes to run simultaneously 3 in figure 7 1 Running a number of processes in a TSS did not increase efficiency since each process had to take account of physical memory mapping Efficiency is improved and the load on each process reduced by the use of a virtual memory system 4 in figure 7 1 In this virtual memory system virtual memory is allocated to each process The task ...

Page 175: ...he paging method the unit of translation is a fixed size address space called a page In the following descriptions the address space in virtual memory in this LSI is referred to as virtual address space and the address space in physical memory as physical address space MMU MMU Process 1 Physical Memory 1 0 2 3 4 Physical Memory Physical Memory Physical Memory Virtual Memory Virtual Memory Physical...

Page 176: ...e an address error When the AT bit in MMUCR is set to 1 and the MMU is enabled the P0 P3 and U0 areas can be mapped onto any physical address space in 1 4 64 Kbyte or 1 Mbyte page units in TLB compatible mode and in 1 4 8 64 256 Kbyte 1 4 or 64 Mbyte page units in TLB extended mode By using an 8 bit address space identifier the P0 P3 and U0 areas can be increased to a maximum of 256 Mapping from t...

Page 177: ...using the cache When the MMU is disabled replacing the upper 3 bits of an address with 0s gives the corresponding physical address Whether or not the cache is used is determined by the CCR setting When the cache is used switching between the copy back method and the write through method for write accesses is specified by the WT bit in CCR When the MMU is enabled these areas can be mapped onto any ...

Page 178: ...led clearing the upper 3 bits of an address to 0 gives the corresponding physical address d P4 Area The P4 area is mapped onto the internal resource of this LSI This area except the store queue and on chip memory areas does not allow address translation using the TLB This area cannot be accessed using the cache The P4 area is shown in detail in figure 7 4 H E000 0000 H E400 0000 H F000 0000 H F100...

Page 179: ...tails see section 7 7 2 ITLB Data Array TLB Compatible Mode and section 7 7 3 ITLB Data Array TLB Extended Mode The area from H F400 0000 to H F4FF FFFF is used for direct access to the operand cache address array For details see section 8 6 3 OC Address Array The area from H F500 0000 to H F5FF FFFF is used for direct access to the operand cache data array For details see section 8 6 4 OC Data Ar...

Page 180: ...ation table in external memory contains the physical addresses corresponding to virtual addresses and additional information such as memory protection codes Fast address translation is achieved by caching the contents of the address translation table located in external memory into the TLB In this LSI basically the ITLB is used for instruction accesses and the UTLB for data accesses In the event o...

Page 181: ...lated into different physical addresses depending on the process The only difference between the single virtual memory and multiple virtual memory systems in terms of operation is in the TLB address comparison method see section 7 3 3 Address Translation Method 5 Address Space Identifier ASID In multiple virtual memory mode an 8 bit address space identifier ASID is used to distinguish between mult...

Page 182: ...1F00 0070 32 Instruction re fetch inhibit control register IRMCR R W H FF00 0078 H 1F00 0078 32 Note These P4 addresses are for the P4 area in the virtual address space These area 7 addresses are accessed from area 7 in the physical address space by means of the TLB Table 7 2 Register States in Each Processing State Register Name Abbreviation Power on Reset Manual Reset Sleep Standby Page table en...

Page 183: ...ield in PTEH has been updated execute one of the following three methods before an access including an instruction fetch to the P0 P3 or U0 area that uses the updated ASID value is performed 1 Execute a branch using the RTE instruction In this case the branch destination may be the P0 P3 or U0 area 2 Execute the ICBI instruction for any address including non cacheable area 3 If the R2 bit in IRMCR...

Page 184: ...n The contents of this register are not changed unless a software directive is issued 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 Initial value R R R R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W PPN PPN V SZ1 PR1 PR0 SZ0 C D SH WT R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R W R W R W R W R W R W R W Bit Bit Name Initial...

Page 185: ...E 0 and section 7 4 TLB Functions TLB Extended Mode MMUCR ME 1 Note SZ1 PR1 SZ0 and PR0 bits are valid only in TLB compatible mode 0 WT Undefined R W 7 2 3 Translation Table Base Register TTB TTB is used to store the base address of the currently used page table and so on The contents of TTB are not changed unless a software directive is issued This register can be used freely by software 31 30 29...

Page 186: ...R rewriting should be performed by a program in the P1 or P2 area After MMUCR has been updated execute one of the following three methods before an access including an instruction fetch to the P0 P3 U0 or store queue area is performed 1 Execute a branch using the RTE instruction In this case the branch destination may be the P0 P3 or U0 area 2 Execute the ICBI instruction for any address including...

Page 187: ...event of an ITLB miss The entry to be purged from the ITLB can be confirmed using the LRUI bits LRUI is updated by means of the algorithm shown below x means that updating is not performed 000xxx ITLB entry 0 is used 1xx00x ITLB entry 1 is used x1x1x0 ITLB entry 2 is used xx1x11 ITLB entry 3 is used xxxxxx Other than above When the LRUI bit settings are as shown below the corresponding ITLB entry ...

Page 188: ...unter for indicating the UTLB entry for which replacement is to be performed with an LDTLB instruction This bit is incremented each time the UTLB is accessed If URB 0 URC is cleared to 0 when the condition URC URB is satisfied Also note that if a value is written to URC by software which results in the condition of URC URB incrementing is first performed in excess of URB until URC H 3F URC is not ...

Page 189: ...it Writing 1 to this bit invalidates clears to 0 all valid UTLB ITLB bits This bit is always read as 0 1 0 R Reserved For details on reading from or writing to this bit see description in General Precautions on Handling of Product 0 AT 0 R W Address Translation Enable Bit These bits enable or disable the MMU 0 MMU disabled 1 MMU enabled MMU exceptions are not generated when the AT bit is 0 In the ...

Page 190: ...fied TLB UTLB For details see section 7 4 TLB Functions TLB Extended Mode MMUCR ME 1 3 to 0 All 0 R Reserved For details on reading writing these bits see General Precautions on Handling of Product 7 2 7 Physical Address Space Control Register PASCR PASCR controls the operation in the physical address space 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 191: ...in the cache write through mode these bits specify whether the next bus access from the CPU waits for the end of writing for each area 0 Buffered write The CPU does not wait for the end of writing bus access and starts the next bus access 1 Unbuffered write The CPU waits for the end of writing bus access and starts the next bus access UB 7 Corresponding to the control register area UB 6 Correspond...

Page 192: ...instruction should be executed after all necessary resources have been changed prior to execution of the program which uses changed resources For details on the specific sequence see descriptions in each resource 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value R R R R R R R R R R R R R R R R R R2 R1 LT MT MC R R R W R W R W R W R W R W ...

Page 193: ...e fetch is performed for the next instruction after the LDTLB instruction has been executed 0 Re fetch is performed 1 Re fetch is not performed 1 MT 0 R W Re Fetch Inhibit after Writing Memory Mapped TLB This bit controls whether re fetch is performed for the next instruction after writing memory mapped ITLB UTLB while the AT bit in MMUCR is set to 1 0 Re fetch is performed 1 Re fetch is not perfo...

Page 194: ...configuration The UTLB consists of 64 fully associative type entries Figure 7 7 shows the relationship between the page size and address format PPN 28 10 PPN 28 10 PPN 28 10 SZ 1 0 SZ 1 0 SZ 1 0 SH SH SH C C C PR 1 0 PR 1 0 PR 1 0 ASID 7 0 ASID 7 0 ASID 7 0 VPN 31 10 VPN 31 10 VPN 31 10 V V V Entry 0 Entry 1 Entry 2 D D D WT WT WT PPN 28 10 SZ 1 0 SH C PR 1 0 ASID 7 0 VPN 31 10 V Entry 63 D WT Fig...

Page 195: ... address of the physical page number With a 1 Kbyte page PPN 28 10 are valid With a 4 Kbyte page PPN 28 12 are valid With a 64 Kbyte page PPN 28 16 are valid With a 1 Mbyte page PPN 28 20 are valid The synonym problem must be taken into account when setting the PPN see section 7 5 5 Avoiding Synonym Problems PR 1 0 Protection key data 2 bit data expressing the page access right as a code 00 Can be...

Page 196: ...it Specifies the cache write mode 0 Copy back mode 1 Write through mode 31 1 Kbyte page 10 9 0 Virtual address 31 4 Kbyte page 12 11 0 Virtual address 31 64 Kbyte page 16 15 0 Virtual address 31 1 Mbyte page 20 19 0 Virtual address VPN Offset VPN Offset VPN Offset VPN Offset 28 10 9 0 Physical address 28 12 11 0 Physical address 28 16 15 0 Physical address 28 20 19 0 Physical address PPN Offset PP...

Page 197: ... The ITLB consists of four fully associative type entries PPN 28 10 PPN 28 10 PPN 28 10 PPN 28 10 SZ 1 0 SZ 1 0 SZ 1 0 SZ 1 0 SH SH SH SH C C C C PR PR PR PR ASID 7 0 ASID 7 0 ASID 7 0 ASID 7 0 VPN 31 10 VPN 31 10 VPN 31 10 VPN 31 10 V V V V Entry 0 Entry 1 Entry 2 Entry 3 Notes 1 The D and WT bits are not supported 2 There is only one PR bit corresponding to the upper bit of the PR bits in the UT...

Page 198: ...A is in P2 area VA is in P1 area VA is in P0 U0 or P3 area MMUCR AT 1 SH 0 and MMUCR SV 0 or SR MD 0 VPNs match ASIDs match and V 1 Only one entry matches 1 Privileged Data TLB multiple hit exception Data TLB protection violation exception Data TLB miss exception 0 User VPNs match and V 1 Data TLB protection violation exception Initial page write exception Cache access in copy back mode Cache acce...

Page 199: ...n P2 area VA is in P1 area VA is in P0 U0 or P3 area MMUCR AT 1 SH 0 and MMUCR SV 0 or SR MD 0 VPNs match and V 1 VPNs match ASIDs match and V 1 Only one entry matches SR MD Instruction TLB multiple hit exception 0 User 1 Privileged PR C 1 and CCR ICE 1 Cache access Memory access Non cacheable Instruction TLB protection violation exception Instruction TLB miss exception Hardware ITLB miss handling...

Page 200: ...l page number For 1 Kbyte page Upper 22 bits of virtual address For 4 Kbyte page Upper 20 bits of virtual address For 8 Kbyte page Upper 19 bits of virtual address For 64 Kbyte page Upper 16 bits of virtual address For 256 Kbyte page Upper 14 bits of virtual address For 1 Mbyte page Upper 12 bits of virtual address For 4 Mbyte page Upper 10 bits of virtual address For 64 Mbyte page Upper 6 bits of...

Page 201: ...With a 8 Kbyte page PPN 28 13 are valid With a 64 Kbyte page PPN 28 16 are valid With a 256 Kbyte page PPN 28 18 are valid With a 1 Mbyte page PPN 28 20 are valid With a 4 Mbyte page PPN 28 22 are valid With a 64 Mbyte page PPN 28 26 are valid The synonym problem must be taken into account when setting the PPN see section 7 5 5 Avoiding Synonym Problems EPR Protection key data 6 bit data expressin...

Page 202: ...eability bit Indicates whether a page is cacheable 0 Not cacheable 1 Cacheable When the control register area is mapped this bit must be cleared to 0 D Dirty bit Indicates whether a write has been performed to a page 0 Write has not been performed 1 Write has been performed WT Write through bit Specifies the cache write mode 0 Copy back mode 1 Write through mode ...

Page 203: ...VPN Offset 28 26 25 0 PPN Offset 31 256 Kbyte page 18 17 0 VPN Offset 28 18 17 0 PPN Offset Figure 7 12 Relationship between Page Size and Address Format TLB Extended Mode 7 4 2 Instruction TLB ITLB Configuration Figure 7 13 shows the configuration of the ITLB in TLB extended mode PPN 28 10 PPN 28 10 PPN 28 10 PPN 28 10 ESZ 3 0 ESZ 3 0 ESZ 3 0 ESZ 3 0 SH SH SH SH C C C C EPR 5 EPR 5 EPR 5 EPR 5 EP...

Page 204: ...7 Memory Management Unit MMU Rev 1 00 Jan 10 2008 Page 174 of 1658 REJ09B0261 0100 7 4 3 Address Translation Method Figure 7 14 is a flowchart of memory access using the UTLB in TLB extended mode ...

Page 205: ... in copy back mode EPR 5 EPR 4 Data access to virtual address VA VA is in P4 area VA is in P2 area VA is in P1 area VA is in P0 U0 or P3 area Yes Yes No No No Yes Yes Yes No 1 Privileged R W R W 0 User D EPR 1 0 0 1 1 0 1 1 0 EPR 2 WT C 1 and CCR OCE 1 0 1 1 0 R W W R MMUCR AT 1 Yes No Data TLB multiple hit exception Data TLB miss exception Memory access Non cacheable Internal resource access 1 0 ...

Page 206: ...P2 area VA is in P1 area VA is in P0 U0 or P3 area Yes Yes No No No Yes Yes 1 Privileged Search UTLB 0 User Hardware ITLB miss handling Match MMUCR AT 1 Yes No Instruction TLB miss exception Memory access Non cacheable Internal resource access VPNs match and V 1 1 0 CCR ICE Yes No C 1 and CCR ICE 1 EPR 2 0 and EPR 0 0 EPR 0 No Record in ITLB Yes No Yes No Yes 1 1 0 0 No ICBI or normal instruction ...

Page 207: ... in the ITLB in an instruction access the MMU searches the UTLB If the necessary address translation information is recorded in the UTLB the MMU copies this information into the ITLB in accordance with the LRUI bit setting in MMUCR 7 5 2 MMU Software Management Software processing for the MMU consists of the following 1 Setting of MMU related registers Some registers are also partially updated by ...

Page 208: ... been executed execute one of the following three methods before an access include an instruction fetch the area where TLB is used to translate the address is performed 1 Execute a branch using the RTE instruction In this case the branch destination may be the area where TLB is used to translate the address 2 Execute the ICBI instruction for any address including non cacheable area 3 If the LT bit...

Page 209: ... 0 PR 1 0 ASID 7 0 ASID 7 0 ASID 7 0 VPN 31 10 VPN 31 10 VPN 31 10 V V V Entry 0 Entry 1 Entry 2 D D D WT WT WT PPN 28 10 SZ 1 0 SH C PR 1 0 ASID 7 0 VPN 31 10 V Entry 63 D WT 31 2928 9 8 7 6 5 4 3 2 1 0 V SZ1 PR 1 0 SZ0 C D SH WT PTEL Write UTLB 31 10 9 8 7 0 ASID PTEH 31 26252423 18171615 10 9 8 7 3 2 1 0 LRUI URB URC SV TI AT MMUCR VPN 10 PPN Entry specification SQMD Figure 7 16 Operation of LD...

Page 210: ... PPN PTEA EPR ESZ Entry specification SQMD Figure 7 17 Operation of LDTLB Instruction TLB Extended Mode 7 5 4 Hardware ITLB Miss Handling In an instruction access this LSI searches the ITLB If it cannot find the necessary address translation information ITLB miss occurred the UTLB is searched by hardware and if the necessary address translation information is present it is recorded in the ITLB Thi...

Page 211: ...e virtual address in the case of a 4 Kbyte page are subject to address translation As a result bits 12 to 10 of the physical address after translation may differ from bits 12 to 10 of the virtual address Consequently the following restrictions apply to the writing of address translation information as UTLB entries When address translation information whereby a number of 1 Kbyte page UTLB entries a...

Page 212: ...tches the virtual address to which an instruction access has been made If multiple hits occur when the UTLB is searched by hardware in hardware ITLB miss handling an instruction TLB multiple hit exception will result When an instruction TLB multiple hit exception occurs a reset is executed and cache coherency is not guaranteed 1 Hardware Processing In the event of an instruction TLB multiple hit e...

Page 213: ...he exception in SSR The R15 contents at this time are saved in SGR 6 Sets the MD bit in SR to 1 and switches to privileged mode 7 Sets the BL bit in SR to 1 and masks subsequent exception requests 8 Sets the RB bit in SR to 1 9 Branches to the address obtained by adding offset H 0000 0400 to the contents of VBR and starts the instruction TLB miss exception handling routine 2 Software Processing In...

Page 214: ...ss right specified by the PR or EPR bit The instruction TLB protection violation exception processing carried out by hardware and software is shown below 1 Hardware Processing In the event of an instruction TLB protection violation exception hardware carries out the following processing 1 Sets the VPN of the virtual address at which the exception occurred in PTEH 2 Sets the virtual address at whic...

Page 215: ...ng In the event of a data TLB multiple hit exception hardware carries out the following processing 1 Sets the virtual address at which the exception occurred in TEA 2 Sets exception code H 140 in EXPEVT 3 Branches to the reset handling routine H A000 0000 2 Software Processing Reset Routine The UTLB entries which caused the multiple hit exception are checked in the reset handling routine This exce...

Page 216: ...ould carry out the following processing in order to find and assign the necessary page table entry 1 In TLB compatible mode write to PTEL the values of the PPN PR SZ C D SH V and WT bits in the page table entry stored in the address translation table for external memory In TLB extended mode write to PTEL and PTEA the values of the PPN EPR ESZ C D SH V and WT bits in the page table entry stored in ...

Page 217: ... of a write in EXPEVT OCBP OCBWB read OCBI MOVCA L write 4 Sets the PC value indicating the address of the instruction at which the exception occurred in SPC If the exception occurred at a delay slot sets the PC value indicating the address of the delayed branch instruction in SPC 5 Sets the SR contents at the time of the exception in SSR The R15 contents at this time are saved in SGR 6 Sets the M...

Page 218: ...n in SSR The R15 contents at this time are saved in SGR 6 Sets the MD bit in SR to 1 and switches to privileged mode 7 Sets the BL bit in SR to 1 and masks subsequent exception requests 8 Sets the RB bit in SR to 1 9 Branches to the address obtained by adding offset H 0000 0100 to the contents of VBR and starts the initial page write exception handling routine 2 Software Processing Initial Page Wr...

Page 219: ...f PTEH and PTEL to the TLB In TLB extended mode execute the LDTLB instruction and write the contents of PTEH PTEL PTEA to the UTLB 6 Finally execute the exception handling return instruction RTE terminate the exception handling routine and return control to the normal flow The RTE instruction should be issued at least one instruction after the LDTLB instruction ...

Page 220: ...fetch is performed again for the next instruction after MMUCR has been updated Note that the method 3 may not be guaranteed in the future SuperH Series Therefore it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH Series The ITLB and UTLB are allocated to the P4 area in the virtual address space In TLB compatible mode VPN V and ASID in the ITLB can b...

Page 221: ...9 8 As only longword access is used 0 should be specified for address field bits 1 0 In the data field bits 31 10 indicate VPN bit 8 indicates V and bits 7 0 indicate ASID The following two kinds of operation can be used on the ITLB address array 1 ITLB address array read VPN V and ASID are read into the data field from the ITLB entry corresponding to the entry set in the address field 2 ITLB addr...

Page 222: ...icate PPN bit 8 indicates V bits 7 and 4 indicate SZ bit 6 indicates PR bit 3 indicates C and bit 1 indicates SH The following two kinds of operation can be used on ITLB data array 1 ITLB data array read PPN V SZ PR C and SH are read into the data field from the ITLB entry corresponding to the entry set in the address field 2 ITLB data array write PPN V SZ PR C and SH specified in the data field a...

Page 223: ...data array 2 of the same entry should always be performed In TLB compatible mode MMUCR ME 0 ITLB data array 2 cannot be accessed Operation if they are accessed is not guaranteed 1 ITLB Data Array 1 In TLB extended mode bits 7 6 and 4 in the data field which correspond to the PR and SZ bits in compatible mode are reserved Specify 0 as the write value for these bits Address field Data field PPN V E ...

Page 224: ...fied by bits 9 8 In the data field bits 13 11 10 and 8 indicate EPR 5 3 2 and 0 and bits 7 4 indicate ESZ respectively The following two kinds of operation can be applied to ITLB data array 2 1 ITLB data array 2 read EPR and ESZ are read into the data field from the ITLB entry corresponding to the entry set in the address field 2 ITLB data array 2 write EPR and ESZ specified in the data field are ...

Page 225: ...ing to the entry set in the address field In a read associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0 2 UTLB address array write non associative VPN D V and ASID specified in the data field are written to the UTLB entry corresponding to the entry set in the address field The A bit in the address field should be cleared to 0 3 ...

Page 226: ...ation when writing Information for selecting the entry to be accessed is specified in the address field and PPN V SZ PR C D SH and WT to be written to data array are specified in the data field In the address field bits 31 20 have the value H F70 indicating UTLB data array and the entry is specified by bits 13 8 In the data field bits 28 10 indicate PPN bit 8 indicates V bits 7 and 4 indicate SZ b...

Page 227: ...de the PR and SZ bits of UTLB data array 1 are reserved and 0 should be specified as the write value for these bits In addition when a write to UTLB data array 1 is performed a write to UTLB data array 2 of the same entry should always be performed after that In TLB compatible mode MMUCR ME 0 UTLB data array 2 cannot be accessed Operation if they are accessed is not guaranteed 1 UTLB Data Array 1 ...

Page 228: ... and the entry is specified by bits 13 8 In the data field bits 13 8 indicate EPR and bits 7 4 indicate ESZ respectively The following two kinds of operation can be applied to UTLB data array 2 1 UTLB data array 2 read EPR and ESZ are read into the data field from the UTLB entry corresponding to the entry set in the address field 2 UTLB data array 2 write EPR and ESZ specified in the data field ar...

Page 229: ... Extended mode Figure 7 26 Physical Address Space 32 Bit Address Extended Mode 7 8 1 Overview of 32 Bit Address Extended Mode In 32 bit address extended mode the privileged space mapping buffer PMB is introduced The PMB maps virtual addresses in the P1 or P2 area which are not translated in 29 bit address mode to the 32 bit physical address space In areas which are target for address translation o...

Page 230: ...rding to the TLB conversion information Addresses in the P1 or P2 area are translated according to the PMB mapping information B 10 should be set to the upper 2 bits of virtual page number VPN 31 30 in the PMB in order to indicate P1 or P2 area The operation is not guaranteed when the value except B 10 is set to these bits 3 Regardless of the setting of the AT bit in MMUCR bits 31 to 29 in physica...

Page 231: ...r P2 area SZ Page size bits Specify the page size 00 16 Mbyte page 01 64 Mbyte page 10 128 Mbyte page 11 512 Mbyte page V Validity bit Indicates whether the entry is valid 0 Invalid 1 Valid Cleared to 0 by a power on reset Not affected by a manual reset PPN Physical page number Upper 8 bits of the physical address of the physical page number With a 16 Mbyte page PPN 31 24 are valid With a 64 Mbyte...

Page 232: ...or P2 area which is not recorded in the PMB is made this LSI is reset by the TLB In this case the accessed address in the P1 or P2 area which causes the TLB reset is stored in the TEA and code H 140 in the EXPEVT 3 The SH 4A does not guarantee the operation when multiple hit occurs in the PMB Special care should be taken when the PMB mapping information is recorded by software 4 The PMB does not h...

Page 233: ...he data field as V 2 PMB address array write When memory writing is performed while bits 31 to 20 in the address field are specified as H F61 which indicates the PMB address array and bits 11 to 8 in the address field as an entry and bits 31 to 24 in the data field are specified as VPN and bit 8 in the data field as V data is written to the specified entry 3 PMB data array read When memory reading...

Page 234: ...0 0 1 E 23 24 19 20 8 7 12 11 SZ WT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 7 29 Memory Mapped PMB Data Array 7 8 6 Notes on Using 32 Bit Address Extended Mode When using 32 bit address extended mode note that the items described in this section are extended or changed as follows 1 PASCR The SE bit is added in bit 31 in the control register PASCR The bits 6 to 0 of the UB in the PASCR are invalid N...

Page 235: ...g to the control register area UB 6 0 These bits are invalid in 32 bit address extended mode 2 ITLB The PPN field in the ITLB is extended to bits 31 to 10 3 UTLB The PPN field in the UTLB is extended to bits 31 to 10 The same UB bit as that in the PMB is added in each entry of the UTLB UB Buffered write bit Specifies whether a buffered write is performed 0 Buffered write Subsequent processing proc...

Page 236: ...supported in a boot routine which is allocated in an area where caching and TLB based address translation are not allowed and runs after a power on reset or manual reset 2 After switching the SE bit an area in which the program is allocated becomes the target of the PMB address translation Therefore the area should be recorded in the PMB before switching the SE bit An address which may be accessed...

Page 237: ...e procedures below to modify the PMB taking care not to generate PMB misses and multiple PMB hits The procedure should be set up within the boot routine and should be executed before activation of the caches and TLB CCR ICE 1 CCR OCE 1 and MMUCR AT 1 Do not use routines other than the boot routine to change the value recorded in the PMB 1 When the Program Modifying the PMB is in the P1 or P2 Area ...

Page 238: ...ate the entry remaining in the ITLB by writing 1 to the TI bit in MMUCR 2 In the memory mapped PMB change PMB entries 3 Execute one of the following steps A B and C Do not execute a branch or operand access for the P1 or P2 area before this execution A Perform a branch using the RTE instruction B Execute the ICBI instruction for any address including non cacheable area C If the MT bit in IRMCR is ...

Page 239: ...xception 2 handling routine a When thea TLB miss exception occurs and recording the information of a page with the access right in the UTLB do not record the page in which the exception has occurred in the UTLB using the following two operations Specifies the protection key data that causes a protection violation exception upon re execution of the instruction that has caused the TLB miss exception...

Page 240: ... VBR offset upon occurrence of an exception to the RTE for returning to the original program or to the RTE delay slot 2 MMU related exceptions are instruction TLB miss exception instruction TLB miss protection violation exception data TLB miss exception data TLB protection violation exception and initial page write exception 3 Instruction accesses include the PREFI and ICBI instructions ...

Page 241: ...dex physical address tag Line size 32 bytes 32 bytes Entries 256 entries way 256 entries way Write method Copy back write through selectable Replacement method LRU least recently used algorithm LRU least recently used algorithm Table 8 2 Store Queue Features Item Store Queues Capacity 32 bytes 2 Addresses H E000 0000 to H E3FF FFFF Write Store instruction 1 cycle write Write back Prefetch instruct...

Page 242: ...ion register EXPMASK For details see section 5 Exception Handling 31 5 4 2 LW0 32 bits LW1 32 bits LW2 32 bits LW3 32 bits LW4 32 bits LW5 32 bits LW6 32 bits LW7 32 bits 6 bits MMU 12 5 255 19 bits 1 bit 1 bit Tag U V Address array way 0 to way 3 Data array way 0 to way3 LRU Entry selection Longword LW selection Virtual address 3 8 22 19 0 Write data Read data Hit signal Way 0 to way 3 12 10 0 Co...

Page 243: ...t initialized by a power on or manual reset V bit validity bit Indicates that valid data is stored in the cache line When this bit is 1 the cache line data is valid The V bit is initialized to 0 by a power on reset but retains its value in a manual reset U bit dirty bit The U bit is set to 1 if data is written to the cache line while the cache is being used in copy back mode That is the U bit indi...

Page 244: ...egistered in the cache at each entry address When an entry is registered the LRU bit indicates which of the 4 ways it is to be registered in The LRU mechanism uses 6 bits of each entry and its usage is controlled by hardware The LRU least recently used algorithm is used for way selection and selects the less recently accessed way The LRU bits are initialized to 0 by a power on reset but not by a m...

Page 245: ...ntrol register RAMCR R W H FF00 0074 H 1F00 0074 32 Note These P4 addresses are for the P4 area in the virtual address space These area 7 addresses are accessed from area 7 in the physical address space by means of the TLB Table 8 4 Register States in Each Processing State Register Name Abbreviation Power on Reset Manual Reset Sleep Standby Cache control register CCR H 0000 0000 H 0000 0000 Retain...

Page 246: ...at the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction after CCR has been updated Note that the method 3 may not be guaranteed in the future SuperH Series Therefore it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH Series 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0...

Page 247: ...scription in General Precautions on Handling of Product 3 OCI 0 R W OC Invalidation Bit When 1 is written to this bit the V and U bits of all OC entries are cleared to 0 This bit is always read as 0 2 CB 0 R W Copy Back Bit Indicates the P1 area cache write mode 0 Write through mode 1 Copy back mode 1 WT 0 R W Write Through Mode Indicates the P0 U0 and P3 area cache write mode When address transla...

Page 248: ...0 0 0 0 0 R R R R R R R R R R R R W R W R W R R R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AREA0 Bit Bit Name Initial Value R W Description 31 to 5 All 0 R Reserved For details on reading from or writing to these bits see description in General Precautions on Handling of Product 4 to 2 AREA0 Undefined R W When the MMU is disabled these bits generate physical address bits 28 26...

Page 249: ...0 0 0 0 0 R R R R R R R R R R R R W R W R W R R R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AREA1 Bit Bit Name Initial Value R W Description 31 to 5 All 0 R Reserved For details on reading from or writing to these bits see description in General Precautions on Handling of Product 4 to 2 AREA1 Undefined R W When the MMU is disabled these bits generate physical address bits 28 26...

Page 250: ... the specific instruction does not need to be executed However note that the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction after RAMCR has been updated Note that the method 3 may not be guaranteed in the future SuperH Series Therefore it is recommended that the method 1 or 2 should be used for being compatible with the future S...

Page 251: ...tion For details see section 8 4 3 IC Two Way Mode 6 OC2W 0 R W OC Two Way Mode bit 0 OC is a four way operation 1 OC is a two way operation For details see section 8 3 6 OC Two Way Mode 5 ICWPD 0 R W IC Way Prediction Stop Selects whether the IC way prediction is used 0 Instruction cache performs way prediction 1 Instruction cache does not perform way prediction 4 to 0 All 0 R Reserved For detail...

Page 252: ... virtual address Data reading is performed using the wraparound method in order from the quad word data 8 bytes including the cache missed data When the corresponding data arrives in the cache the read data is returned to the CPU While the remaining data on the cache line is being read the CPU can execute the next processing When reading of one line of data is completed the tag corresponding to th...

Page 253: ...dress space corresponding to the virtual address Data reading is performed using the wraparound method in order from the quad word data 8 bytes including the cache missed data In the prefetch operation the CPU doesn t wait the data arrives While the one cache line of data is being read the CPU can execute the next processing When reading of one line of data is completed the tag corresponding to th...

Page 254: ... 0 Then 1 is written to the U bit The LRU bits are updated to indicate the way is the latest one 4 Cache hit write through A data write in accordance with the access size is performed for the data field on the hit way which is indexed by virtual address bits 4 0 A write is also performed to external memory corresponding to the virtual address Then the LRU bits are updated to indicate the way is th...

Page 255: ...indicate the way is latest one Then the data in the write back buffer is then written back to external memory 7 Cache miss write through A write of the specified access size is performed to the external memory corresponding to the virtual address In this case a write to cache is not performed 8 3 4 Write Back Buffer In order to give priority to data reads to the cache and improve performance this ...

Page 256: ...onsumption can be reduced In this mode only way 0 and way 1 are used even if a memory mapped OC access is made The OC2W bit should be modified by a program in the P2 area At that time if the valid line has already been recorded in the OC data should be written back by software if necessary 1 should be written to the OCI bit in CCR and all entries in the OC should be invalid before modifying the OC...

Page 257: ...dress space corresponding to the virtual address Data reading is performed using the wraparound method in order from the quad word data 8 bytes including the cache missed data and when the corresponding data arrives in the cache the read data is returned to the CPU as an instruction While the remaining one cache line of data is being read the CPU can execute the next processing When reading of one...

Page 258: ...n be reduced In this mode only way 0 and way 1 are used even if a memory mapped IC access is made The IC2W bit should be modified by a program in the P2 area At that time if the valid line has already been recorded in the IC 1 should be written to the ICI bit in CCR and all entries in the IC should be invalid before modifying the IC2W bit 8 4 4 Instruction Cache Way Prediction Operation This LSI i...

Page 259: ... instruction OCBWB Rn Operand cache write back Operand cache allocate instruction MOVCA L R0 Rn Operand cache allocation Instruction cache invalidate instruction ICBI Rn Instruction cache invalidation Operand access synchronization instruction SYNCO Wait for data transfer completion 2 Coherency Control The operand cache can receive PURGE and FLUSH transaction from SuperHyway bus to control the cac...

Page 260: ...B related exceptions do not occur Do not execute this instruction to invalidate the memory mapped array areas and control register areas for which Rn 31 24 is not H F4 and their reserved areas H F0 to H F3 H F5 to H FF Changes in the purge instruction OCBP Rn When Rn is designating an address in a non cacheable area this instruction is executed as NOP in the SH 4A with H 20 valued VER bits in the ...

Page 261: ...incurred as the result of a cache miss If it is known that a cache miss will result from a read or write operation it is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss due to the read or write operation and so improve software performance If a prefetch instruction is executed for data already held in the cache or if the prefetch address...

Page 262: ...it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH Series In privileged mode the OC contents can be read from or written to by a program in the P1 or P2 area by means of a MOV instruction Operation is not guaranteed if access is made from a program in another area The IC and OC are allocated to the P4 area in the virtual address space Only data acce...

Page 263: ...set to 1 the tag in each way stored in the entry specified in the address field is compared with the tag specified in the data field The way numbers of bits 14 13 in the address field are not used If the MMU is enabled at this time comparison is performed after the virtual address specified by data field bits 31 10 has been translated to a physical address using the ITLB If the addresses match and...

Page 264: ...e longword data specification The following two kinds of operation can be used on the IC data array 1 IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the way and entry set in the address field 2 IC data array write The longword data specified in the data field is written fo...

Page 265: ...it and V bit specified in the data field are written to the OC entry corresponding to the way and entry set in the address field The A bit in the address field should be cleared to 0 When a write is performed to a cache line for which the U bit and V bit are both 1 after write back of that cache line the tag U bit and V bit specified in the data field are written 3 OC address array write associati...

Page 266: ...ess field bits 31 24 have the value H F5 indicating the OC data array and the way is specified by bits 14 13 and the entry by bits 12 5 Address field bits 4 2 are used for the longword data specification in the entry As only longword access is used 0 should be specified for address field bits 1 0 The data field is used for the longword data specification The following two kinds of operation can be...

Page 267: ... family products The use of instructions ICBI OCBI OCBP and OCBWB is recommended These instructions handle ITLB misses and notify instruction TLB miss exceptions and data TLB miss exceptions thus providing a sure way of controlling the IC and OC As a transitional measure this LSI generates address errors when this function is used If compatibility with previous products is a crucial consideration ...

Page 268: ...Q1 2 SQ1 3 SQ1 4 SQ1 5 SQ1 6 SQ1 7 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte Figure 8 9 Store Queue Configuration 8 7 2 Writing to SQ A write to the SQs can be performed using a store instruction for addresses H E000 0000 to H E3FF FFFC in the P4 area A longword or quadword access size can be used The meanings of the address bits are as follows 31 26 111000 Store queue specification ...

Page 269: ...same meaning as for normal address translation but the C and WT bits have no meaning with regard to this page When a prefetch instruction is issued for the SQ area address translation is performed and physical address bits 28 10 are generated in accordance with the SZ bit specification For physical address bits 9 5 the address prior to address translation is generated in the same way as when the M...

Page 270: ...ead type exception judgment for transfer from the SQs to external memory using a PREF instruction As a result a TLB miss exception or protection violation exception is generated as required However if SQ access is enabled in privileged mode only by the SQMD bit in MMUCR an address error will occur even if address translation is successful in user mode When MMU is disabled AT 0 in MMUCR Operation i...

Page 271: ...ows 1 The tag bits 28 10 19 bits in the IC and OC are extended to bits 31 10 22 bits 2 An instruction which operates the IC a memory mapped IC access and writing to the ICI bit in CCR should be located in the P1 or P2 area The cacheable bit C bit in the corresponding entry in the PMB should be 0 3 Bits 4 2 3 bits for the AREA0 bit in QACR0 and the AREA1 bit in QACR1 are extended to bits 7 2 6 bits...

Page 272: ...8 Caches Rev 1 00 Jan 10 2008 Page 242 of 1658 REJ09B0261 0100 ...

Page 273: ...ce and the physical address space Table 9 1 OL memory Addresses Page 0A H E500 E000 to H E500 EFFF Page 0B H E500 F000 to H E500 FFFF Page 1A H E501 0000 to H E501 0FFF Page 1B H E501 1000 to H E501 1FFF Ports Each page has three independent read write ports and is connected to the SuperHyway bus the cache RAM internal bus and operand bus The operand bus is used when the OL memory is accessed thro...

Page 274: ... accessed through instruction fetch The cache RAM internal bus is used when the IL memory is accessed through operand access The SuperHyway bus is used for IL memory access from the SuperHyway bus master module Priority In the event of simultaneous accesses to the same page from different buses the access requests are processed according to priority The priority order is SuperHyway bus cache RAM i...

Page 275: ...emory has three independent read write ports and is connected to the operand bus the cache RAM internal bus and the SuperHyway bus The operand bus is used when the U memory is accessed through operand read access The cache RAM internal bus is used when the U memory is accessed through instruction fetch and operand write access The SuperHyway bus is used for U memory access from the SuperHyway bus ...

Page 276: ...ress register 1 LDA1 R W H FF00 005C H 1F00 005C 32 Note The P4 address is the address used when using P4 area in the virtual address space The area 7 address is the address used when accessing from area 7 in the physical address space using the TLB Table 9 5 Register States in Each Processing Mode Name Abbreviation Power On Reset Manual Reset Sleep Standby On chip memory control register RAMCR H ...

Page 277: ...Value R W Description 31to10 All 0 R Reserved For read write in these bits refer to General Precautions on Handling of Product 9 RMD 0 R W On Chip Memory Access Mode Specifies the right of access to the on chip memory from the virtual address space 0 An access in privileged mode is allowed An address error exception occurs in user mode 1 An access in user privileged mode is allowed 8 RP 0 R W On C...

Page 278: ...ransfer to page 0A or 0B of the OL memory 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 Initial value R R R R W R W R W R W R W R W R W L0DADR L0DADR L0DSZ R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 0 0 0 0 Initial value R W R W R W R W R W R W R R R R R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved For read wr...

Page 279: ...nd address is used as the transfer source physical address 1 The L0SADR value is used as the transfer source physical address Settable values 111111 Transfer source physical address is specified in 1 Kbyte units 111110 Transfer source physical address is specified in 2 Kbyte units 111100 Transfer source physical address is specified in 4 Kbyte units 111000 Transfer source physical address is speci...

Page 280: ...R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 0 0 0 0 Initial value R W R W R W R W R W R W R R R R R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved For read write in these bits refer to General Precautions on Handling of Product 28 to 10 L1SADR Undefined R W OL memory Page 1 Block Transfer Source Address When MMUCR AT 0 or RAMCR RP 0 the...

Page 281: ...erand address is used as the transfer source physical address 1 The L1SADR value is used as the transfer source physical address Settable values 111111 Transfer source physical address is specified in 1 Kbyte units 111110 Transfer source physical address is specified in 2 Kbyte units 111100 Transfer source physical address is specified in 4 Kbyte units 111000 Transfer source physical address is sp...

Page 282: ...W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 0 0 0 0 Initial value R W R W R W R W R W R W R R R R R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved For read write in these bits refer to General Precautions on Handling of Product 28 to 10 L0DADR Undefined R W OL memory Page 0 Block Transfer Destination Address When MMUCR AT 0 or RAMCR RP 0 ...

Page 283: ...is used as the transfer destination physical address 1 The L0DADR value is used as the transfer destination physical address Settable values 111111 Transfer destination physical address is specified in 1 Kbyte units 111110 Transfer destination physical address is specified in 2 Kbyte units 111100 Transfer destination physical address is specified in 4 Kbyte units 111000 Transfer destination physic...

Page 284: ...W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 0 0 0 0 Initial value R W R W R W R W R W R W R R R R R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved For read write in these bits refer to General Precautions on Handling of Product 28 to 10 L1DADR Undefined R W OL memory Page 1 Block Transfer Destination Address When MMUCR AT 0 or RAMCR RP 0 ...

Page 285: ...s used as the transfer destination physical address 1 The L1DADR value is used as the transfer destination physical address Settable values 111111 Transfer destination physical address is specified in 1 Kbyte units 111110 Transfer destination physical address is specified in 2 Kbyte units 111100 Transfer destination physical address is specified in 4 Kbyte units 111000 Transfer destination physica...

Page 286: ... is performed via the cache RAM internal bus and one instruction fetch takes more than one cycle 9 3 2 Operand Access from the CPU and Access from the FPU Note Operand access is applied for PC relative access disp pc 1 OL Memory Access from the CPU or FPU is performed via the operand bus for a given virtual address Read access from the operand bus by virtual address takes one cycle if the access i...

Page 287: ... the SuperHyway bus which is a physical address bus The same addresses as for the virtual addresses must be used 9 3 4 OL Memory Block Transfer High speed data transfer can be performed through block transfer between the OL memory and external memory without cache utilization Data can be transferred from the external memory to the OL memory through a prefetch instruction PREF Block transfer from t...

Page 288: ...s conversion The physical address bits 4 0 are fixed to 0 Block transfer is performed from the OL memory to the external memory specified by these physical addresses In PREF or OCBWB instruction execution an MMU exception is checked as read type After the MMU execution check a TLB miss exception or protection error exception occurs if necessary If an exception occurs the block transfer is inhibite...

Page 289: ...ess bits 4 0 are fixed to 0 Block transfer is performed from the external memory specified by these physical addresses to the OL memory When the OCBWB instruction is issued to the OL memory area the physical address bits 28 10 are generated in accordance with the LDA0 or LDA1 specification The physical address bits 9 5 are generated from the virtual address The physical address bits 4 0 are fixed ...

Page 290: ... memory is accessed in user mode it is determined to be an address error exception When MMUCR AT 1 and RAMCR RP 1 MMU exception and address error exception are checked in the on chip memory area which is a part of area P4 as with the area P0 P3 U0 The above descriptions are summarized in table 9 6 Table 9 6 Protective Function Exceptions to Access On Chip Memory MMUCR AT RAMCR RP SR MD RAMCR RMD A...

Page 291: ...ware such that the page corresponding to the address for read access from the operand bus does not change so often 2 IL Memory Access from the instruction bus is performed in one cycle when the access is made successively to the same page but takes multiple cycles a maximum of two wait cycles may be required when the access is made across pages or the previous access was made to memory other than ...

Page 292: ... the U memory execute the following sequence then branch to the rewritten instruction SYNCO ICBI Rn In this case the target for the ICBI instruction can be any address U memory address may be possible within the range where no address error exception occurs and cache hit miss is possible 9 5 4 Sleep Mode 1 OL Memory IL Memory The SuperHyway bus master module such as DMAC cannot access OL memory an...

Page 293: ...requests when the BL bit in SR is set to 1 can be selected Automatically updates the IMASK bit in SR according to the accepted interrupt level Thirty priority levels for interrupts from on chip peripheral modules By setting the ten interrupt priority registers for the on chip peripheral module interrupts any of 30 priority levels can be assigned to the individual requesting sources User mode inter...

Page 294: ...RL7 to IRQ IRL0 GPIO Port E5 to E0 H4 to H1 L7 L6 IRL IRQ 8 12 Peripheral bus Note Other peripheral modules that can output interrupts are TMU SCIF HAC SIOF HSPI MMCIF SSI and FLCTL Legend DMAC DU FLCTL GDTA HAC HSPI H UDI ICR0 ICR1 INTPRI INT2PRI0 to INT2PRI9 INT2GPIC Direct Memory Access Controller Display Unit NAND Flash Memory Controller Graphics Data Translation Accelerator Audio Codec Interf...

Page 295: ...ector includes a noise canceller When the interrupt source holding mode bit ICR0 LVLMODE is cleared to 0 the interrupt source bits for the detected IRL interrupt request are retained in the INTC When ICR0 LVLMODE 1 the interrupt source bits are not retained In the case of ICR0 LVLMODE 0 if the IRL interrupt request masking is set by INTMSK2 after the interrupt source bit is retained the IRL interr...

Page 296: ...tion RTE This instruction restores the contents of PC and SR and returns control to the normal processing routine at the point at which the exception occurred The contents of SGR are not written back to R15 by the RTE instruction 1 The contents of the PC SR and R15 are saved in SPC SSR and SGR respectively 2 The block BL bit in SR is set to 1 3 The mode MD bit in SR is set to 1 4 The register bank...

Page 297: ...ge can be selected for the detection of IRQ input Table 10 1 Interrupt Types Source Number of Sources Max Priority INTEVT Remarks NMI 1 16 H 1C0 H 200 IRL 3 0 LLLL H 0 External interrupts IRL 2 H B00 IRL 7 4 LLLL H 0 High H 220 IRL 3 0 LLLH H 1 H B20 IRL 7 4 LLLH H 1 H 240 IRL 3 0 LLHL H 2 H B40 IRL 7 4 LLHL H 2 H 260 IRL 3 0 LLHH H 3 H B60 IRL 7 4 LLHH H 3 H 280 IRL 3 0 LHLL H 4 Inverse of values...

Page 298: ...pin HHLH H D H CA0 IRL 7 4 pin HHLH H D H 3C0 IRL 3 0 pin HHHL H E Inverse of values on the input pins because the signals are active low Input level H high level L low level see table 10 11 H CC0 IRL 7 4 pin HHHL H E Low 8 Values set in INTPRI H 240 IRQ 0 High IRQ interrupt H 280 IRQ 1 H 2C0 IRQ 2 H 300 IRQ 3 H 340 IRQ 4 H 380 IRQ 5 H 3C0 IRQ 6 H 200 IRQ 7 Low WDT 1 H 560 ITI TMU ch0 1 Values set...

Page 299: ...TXI0 SCIF ch1 4 H 780 ERI1 H 7A0 RXI1 H 7C0 BRI1 H 7E0 TXI1 DMAC 1 7 H 880 DMINT6 H 8A0 DMINT7 H 8C0 DMINT8 H 8E0 DMINT9 H 900 DMINT10 H 920 DMINT11 H 940 DMAE1 channels 6 to 11 HSPI 1 H 960 SPII SCIF ch2 4 H 980 ERI2 RXI2 BRI2 TXI2 SCIF ch3 4 H 9A0 ERI3 RXI3 BRI3 TXI3 SCIF ch4 4 H 9C0 ERI4 RXI4 BRI4 TXI4 SCIF ch5 4 H 9E0 ERI5 RXI5 BRI5 TXI5 PCIC 0 4 H A00 PCISERR PCIC 1 1 H A20 PCIINTA PCIC 2 1 H...

Page 300: ...CI1 FLCTL 4 H F00 FLSTE H F20 FLTEND H F40 FLTRQ0 H F60 FLTRQ1 GPIO 4 H F80 GPIOI0 Port pins E0 to E2 H FA0 GPIOI1 Port pins E3 to E5 H FC0 GPIOI2 Port pins H1 to H4 H FE0 GPIOI3 Port pins L6 and L7 Legend ITI WDT Interval timer interrupt TUNI0 to TUNI5 TMU channels 0 to 5 underflow interrupt TICPI2 TMU channel 2 input capture interrupt DMINT0 to DMINT11 DMAC channels 0 to 11 transfer end interrup...

Page 301: ...interrupt TXI0 TXI1 TXI2 TXI3 TXI4 TXI5 SCIF channels 0 to 5 transmission data empty interrupt FLSTE FLCTL error interrupt FLTEND FLCTL error interrupt FLTRQ0 FLCTL data FIFO transfer request interrupt FLTRQ1 FLCTL control code FIFO transfer request interrupt Note Abbreviations used in the sources of the on chip peripheral module interrupts ...

Page 302: ...ut and port L3 GPIO I O pin and the IRQ IRL4 pin is multiplexed with FD4 FLCTL I O MODE3 mode control input and port L4 GPIO I O pin IRQOUT Interrupt request output pin Output Informs an external device of the generation of an interrupt request The IRQOUT pin is multiplexed with MRESETOUT reset watchdog timer WDT output pin IRQOUT outputs the low level even if the interrupt request is not accepted...

Page 303: ...W H FFD4 0080 H 1FD4 0080 32 Pck Interrupt mask clear register 0 INTMSKCLR0 R W H FFD0 0064 H 1FD0 0064 32 Pck Interrupt mask clear register 1 INTMSKCLR1 R W H FFD0 0068 H 1FD0 0068 32 Pck Interrupt mask clear register 2 INTMSKCLR2 R W H FFD4 0084 H 1FD4 0084 32 Pck NMI flag control register NMIFCR R W 2 H FFD0 00C0 H 1FD0 00C0 32 Pck User interrupt mask level register USERIMASK R W H FFD3 0000 H ...

Page 304: ...ip module interrupt source registers INT2B2 R H FFD4 0048 H 1FD4 0048 32 Pck INT2B3 R H FFD4 004C H 1FD4 004C 32 Pck INT2B4 R H FFD4 0050 H 1FD4 0050 32 Pck INT2B5 R H FFD4 0054 H 1FD4 0054 32 Pck INT2B6 R H FFD4 0058 H 1FD4 0058 32 Pck INT2B7 R H FFD4 005C H 1FD4 005C 32 Pck GPIO interrupt set register INT2GPIC R W H FFD4 0090 H 1FD4 0090 32 Pck Notes 1 The interrupt source registers INTREQ are r...

Page 305: ...0 0000 H FF00 0000 Retained Retained Interrupt mask register 2 INTMSK2 H FF00 0000 H FF00 0000 Retained Retained Interrupt mask clear register 0 INTMSKCLR0 H xx00 0000 H xx00 0000 Retained Retained Interrupt mask clear register 1 INTMSKCLR1 H x000 0000 H x000 0000 Retained Retained Interrupt mask clear register 2 INTMSKCLR2 H xxxx xxxx H xxxx xxxx Retained Retained NMI flag control register NMIFCR...

Page 306: ... H 0000 0000 H 0000 0000 Retained Retained Interrupt mask register INT2MSKR H FFFF FFFF H FFFF FFFF Retained Retained Interrupt mask clear register INT2MSKCR H 0000 0000 H 0000 0000 Retained Retained INT2B0 H xxxx xxxx H xxxx xxxx Retained Retained INT2B1 H xxxx xxxx H xxxx xxxx Retained Retained Module interrupt source registers INT2B2 H xxxx xxxx H xxxx xxxx Retained Retained INT2B3 H xxxx xxxx ...

Page 307: ...15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Name Initial Value R W Description 31 NMIL Undefined R NMI Input Level Indicates the signal level being input on the NMI pin Reading this bit allows the user to know the NMI pin level and writing is invalid 0 Low level is being input on the NMI pin 1 High level is being input on the NMI pin 30 MAI 0 R W...

Page 308: ... the rising edge or the falling edge 0 An interrupt request is detected at the falling edge of NMI input initial value 1 An interrupt request is detected at the rising edge of NMI input 23 IRLM0 1 2 0 R W IRL Pin Mode 0 Selects whether IRQ IRL3 to IRQ IRL0 are used as encoded interrupt requests IRL3 to IRL0 or as four independent interrupts IRQ3 to IRQ0 interrupts 0 IRQ IRL3 to IRQ IRL0 are used a...

Page 309: ...to use INTC after this bit has been set to 1 by the initialization routine For the details of the operation when this bit is set to 0 refer to section 10 4 2 IRQ Interrupts section 10 4 3 IRL Interrupts section 10 7 1 Example of Handing Routine of IRL Interrupts and Level Detection IRQ Interrupts when ICR0 LVLMODE 0 and section 10 7 3 Clearing IRQ and IRL Interrupt Requests 20 to 0 All 0 R Reserve...

Page 310: ... IRQ7S 00 R W IRQn Sense Select Selects whether the corresponding individual pin interrupt signal on the IRQ IRL7 to IRQ IRL0 pins is detected on rising or falling edges or at the high or low level 00 The interrupt request is detected on falling edges of the IRQn input 01 The interrupt request is detected on rising edges of the IRQn input 10 The interrupt request is detected when the IRQn input is...

Page 311: ...pt source that has been sensed or held is cleared When the IRQnS setting is changed form falling edge sense IRQnS is 00 to rising edge sense IRQnS is 01 or changed from rising edge sense IRQnS is 01 to the falling edge sense IRQnSis 00 the IRQ interrupt source that has been sensed before changing the setting is not cleared Likewise when IRQnS setting is changed from low level sense IRQnS is 10 to ...

Page 312: ...e R W Bit Name Initial Value R W Description 31 to 28 IP0 H 0 R W Set the priority of IRQ0 as an individual pin interrupt request 27 to 24 IP1 H 0 R W Set the priority of IRQ1 as an individual pin interrupt request 23 to 20 IP2 H 0 R W Set the priority of IRQ2 as an individual pin interrupt request 19 to 16 IP3 H 0 R W Set the priority of IRQ3 as an individual pin interrupt request 15 to 12 IP4 H ...

Page 313: ... 31 IR0 0 R W 30 IR1 0 R W 29 IR2 0 R W 28 IR3 0 R W 27 IR4 0 R W 26 IR5 0 R W 25 IR6 0 R W 24 IR7 0 R W When read 0 The corresponding IRQ interrupt request has not been detected 1 The corresponding IRQ interrupt request has been detected When written 2 When clearing each bit write a 0 after having read a 1 from it Writing 1 to the bit is ignored When read ICR0 LVLMODE 0 0 The corresponding interr...

Page 314: ...ded IRL interrupt inputs write 1 to IM00 to IM03 or IM04 to IM07 respectively 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 IM07 IM06 IM05 IM04 IM03 IM02 IM00 IM01 R R R R R R R R R W R W R W R W R W R W R W R W Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Name...

Page 315: ...nterrupt source on IRQ5 25 IM06 1 R W Sets masking of individual pin interrupt source on IRQ6 24 IM07 1 R W Sets masking of individual pin interrupt source on IRQ7 When read 0 The interrupts are accepted 1 The interrupts are masked When written 0 No effect 1 Masks the interrupt 23 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 ...

Page 316: ... 29 31 30 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 IM10 IM11 R R R R R R R R R R R R R R R W R W Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Name Initial Value R W Description 31 IM10 1 R W Mask setting for all IRL3 to IRL0 interrupt sources when pins IRQ IRL3 to IRQ IRL0 operate as an encoded interrup...

Page 317: ... is not masked by INTMSK1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM001 IM002 IM003 IM004 IM005 IM006 IM007 IM008 IM009 IM010 IM011 IM012 IM013 IM015 IM014 R R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 ...

Page 318: ...22 IM006 0 R W Masks the interrupt source of IRL3 to IRL0 HLLH H 9 21 IM005 0 R W Masks the interrupt source of IRL3 to IRL0 HLHL H A When read 0 The interrupt is accepted 1 The interrupt is masked When written 0 No effect 1 Masks the interrupt 20 IM004 0 R W Masks the interrupt source of IRL3 to IRL0 HLHH H B 19 IM003 0 R W Masks the interrupt source of IRL3 to IRL0 HHLL H C 18 IM002 0 R W Masks ...

Page 319: ...masked When written 0 No effect 1 Masks the interrupt 11 IM111 0 R W Masks the interrupt source of IRL7 to IRL4 LHLL H 4 10 IM110 0 R W Masks the interrupt source of IRL7 to IRL4 LHLH H 5 9 IM109 0 R W Masks the interrupt source of IRL7 to IRL4 LHHL H 6 8 IM108 0 R W Masks the interrupt source of IRL7 to IRL4 LHHH H 7 7 IM107 0 R W Masks the interrupt source of IRL7 to IRL4 HLLL H 8 6 IM106 0 R W ...

Page 320: ... 2 IM102 0 R W Masks the interrupt source of IRL7 to IRL4 HHLH H D 1 IM101 0 R W Masks the interrupt source of IRL7 to IRL4 HHHL H E When read 0 The interrupt is accepted 1 The interrupt is masked When written 0 No effect 1 Masks the interrupt 0 0 R Reserved This bit is always read as 0 The write value should always be 0 ...

Page 321: ... 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Name Initial Value R W Description 31 IC00 0 R W Clears masking of IRQ0 interrupt 30 IC01 0 R W Clears masking of IRQ1 interrupt 29 IC02 0 R W Clears masking of IRQ2 interrupt 28 IC03 0 R W Clears masking of IRQ3 interrupt 27 IC04 0 R W Clears masking of IRQ4 interrupt 26 IC05 0 R W Clears masking of IRQ5...

Page 322: ... R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Name Initial Value R W Description 31 IC10 0 R W Clears masking of IRL3 to IRL0 interrupt sources when IRL3 to IRL0 operate as an encoded interrupt input 30 IC11 0 R W Clears masking of IRL7 to IRL4 interrupt sources when IRL7 to IRL4 operate as an encoded interrupt ...

Page 323: ...IC111 IC112 IC113 IC115 IC114 R R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Name Initial Value R W Description 31 IC015 0 R W Clears masking of the interrupt source of IRL3 to IRL0 LLLL H 0 30 IC014 0 R W Clears masking of the interrupt source of IRL3 to IRL0 LLLH H 1 29 IC013 0 R W Clears masking of the interrupt source of IRL3 to IRL0 LLHL H 2 28 IC012 0...

Page 324: ...ritten 0 No effect 1 Clears the corresponding interrupt mask enables the interrupt 18 IC002 0 R W Clears masking of the interrupt source of IRL3 to IRL0 HHLH H D 17 IC001 0 R W Clears masking of the interrupt source of IRL3 to IRL0 HHHL H E 16 0 R Reserved This bit is always read as 0 The write value should always be 0 15 IC115 0 R W Clears masking of the interrupt source of IRL7 to IRL4 LLLL H 0 ...

Page 325: ...IRL7 to IRL4 HLLL H 8 When read Undefined values are read When written 0 No effect 1 Clears the corresponding interrupt mask enables the Interrupt 6 IC106 0 R W Clears masking of the interrupt source of IRL7 to IRL4 HLLH H 9 5 IC105 0 R W Clears masking of the interrupt source of IRL7 to IRL4 HLHL H A 4 IC104 0 R W Clears masking of the interrupt source of IRL7 to IRL4 HLHH H B 3 IC103 0 R W Clear...

Page 326: ...to the NMIFL bit before the NMI request is accepted by the CPU the NMI request is not canceled 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 0 NMIFL NMIL R W R R R R R R R R R R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Name Initial Value R W Descrip...

Page 327: ...r an NMI interrupt request signal has been detected This bit is automatically set to 1 when the INTC detects an NMI interrupt request Write 0 to clear the bit Writing 1 to this bit has no effect When read 1 NMI has been detected 0 NMI has not been detected When written 0 Clears the NMI flag 1 No effect 15 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 ...

Page 328: ...ed The interrupts that the level is higher than the level set in the UIMASK bits are accepted under the following conditions The corresponding interrupt mask bit in the interrupt mask register is cleared to 0 the interrupt is enabled The IMASK bit in SR is set lower than its interrupt level The value of the UIMASK bit does not change even if an interrupt is accepted USERIMASK is initialized to H 0...

Page 329: ...in user mode to reduce the processing time USERIMASK is allocated in a different 64 Kbyte space apart from the one where other INTC registers are allocated Access to this register in user mode involves address translation by the MMU In a multitasking OS the memory protection functions of the MMU should be used to control the processes that can access USERIMASK Clear USERIMASK to 0 before completin...

Page 330: ...writable registers that set priority levels 31 to 0 of the on chip peripheral module interrupts These registers are initialized to H 0000 0000 by a reset These registers can set the priority of each interrupt source in 30 levels H 00 and H 01 mask the interrupt request by the 5 bit field 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R R R R W R...

Page 331: ...hannel 1 SCIF channel 2 SCIF channel 3 INT2PRI3 SCIF channel 4 SCIF channel 5 WDT Reserved INT2PRI4 H UDI DMAC 0 DMAC 1 Reserved INT2PRI5 HAC channel 0 HAC channel 1 PCIC 0 PCIC 1 INT2PRI6 PCIC 2 PCIC 3 PCIC 4 PCIC 5 INT2PRI7 SIOF HSPI MMCIF Reserved INT2PRI8 FLCTL GPIO SSI channel 0 SSI channel 1 INT2PRI9 DU GDTA Reserved Reserved Notes The larger the value is the higher the priority is If the va...

Page 332: ...0 and the interrupt sources Table 10 6 Correspondence between Bits in INT2A0 and Interrupt Sources Bit Initial Value R W Source Function Description 31 to 29 All 0 R Reserved These bits are always read as 0 The write value should always be 0 28 Undefined R GDTA GDTA interrupt source indication 27 Undefined R DU DU interrupt source indication 26 Undefined R SSI channel 1 SSI channel 1 interrupt sou...

Page 333: ...t affected by the setting of the interrupt mask register 0 No interrupt 1 An interrupt has occurred Note Interrupt sources can also be identified by directly reading the INTEVT code In this case reading from this register is not required 14 Undefined R PCIC 0 PCISERR interrupt source indication 13 Undefined R HAC channel 1 HAC channel 1 interrupt source indication 12 Undefined R HAC channel 0 HAC ...

Page 334: ...channels 3 to 5 TMU channel 3 to 5 interrupt source indication 0 Undefined R TMU channels 0 to 2 TMU channel 0 to 2 interrupt source indication These bits indicate the interrupt source of each peripheral module that is generating an interrupt INT2A0 is not affected by the setting of the interrupt mask register 0 No interrupt 1 An interrupt has occurred Note Interrupt sources can also be identified...

Page 335: ...generation of interrupt requests SDINT in the H UDI GACISR in the GDTA the same interrupt status information is read from that register and INT2A0 or INT2A1 This means that the time required for reflection in INT2A0 and INT2A1 is guaranteed by hardware When an interrupt source is cleared the time required for reflection in INT2A0 and INT2A1 can be guaranteed by dummy reading SDINT in the H UDI or ...

Page 336: ...eading DMAOR0 or DMAOR1 once after writing to DMAOR0 or DMAOR1 Interrupt sources DMINT0 to DMINT11 Setting of the HE and TE bits in CHCR0 to CHCR11 and output of interrupt request to the INTC take place with different timing For details see section 14 Direct Memory Access Controller DMAC When interrupt sources DMINT0 to DMINT11 corresponding to bits HE and TE in CHCR0 to CHCR11 are cleared the tim...

Page 337: ...its in INT2A1 and the interrupt sources Table 10 8 Correspondence between Bits in INT2A1 and Interrupt Sources Bit Initial Value R W Source Function Description 31 to 29 0 R Reserved These bits are read as 0 and cannot be modified 28 0 R GDTA GDTA interrupt source indication 27 0 R DU DU interrupt source indication 26 0 R SSI channel 1 SSI channel 1 interrupt source indication 25 0 R SSI channel 0...

Page 338: ...1 DMAC channels 6 to 11 and address error interrupt source indication 10 0 R DMAC 0 DMAC channels 0 to 5 and address error interrupt source indication 9 0 R H UDI H UDI interrupt source indication These bits indicate the interrupt source of each peripheral module that is generating an interrupt INT2A1 is affected by the setting of the interrupt mask register 0 No interrupt 1 An interrupt has occur...

Page 339: ...an interrupt INT2A1 is affected by the setting of the interrupt mask register 0 No interrupt 1 An interrupt has occurred Note Interrupt sources can also be identified by directly reading the INTEVT code In this case reading from this register is not required If the interrupt source in an individual module is set or cleared the time required until the state is reflected in INT2A1 is as shown in tab...

Page 340: ...1 1 1 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Table 10 9 shows the correspondence between bits in INT2MSKR and the interrupts that are masked Table 10 9 Correspondence between Bits in INT2MSKR and Interrupts that Are Masked Bit Initial Value R W Source Function Description 31 to 29 All 1 R Reserved These bits are always read as 1 The wr...

Page 341: ...rrupt Masks interrupt to each on chip peripheral module When written 0 Invalid 1 Interrupts are masked When read 0 Not masked 1 Masked 10 1 R W DMAC 0 Masks DMAC channels 0 to 5 interrupts and address error interrupt 9 1 R W H UDI Masks the H UDI interrupt 8 1 R W WDT Masks the WDT interrupt 7 1 R W SCIF channel 5 Masks SCIF channel 5 interrupt 6 1 R W SCIF channel 4 Masks SCIF channel 4 interrupt...

Page 342: ...terrupt masking that are cleared Table 10 10 Correspondence between Bits in INT2MSKCR and Interrupt Masking that Are Cleared Bit Initial Value R W Source Function Description 31 to 29 All 0 R Reserved These bits are always read as 0 The write value should always be 0 28 0 R W GDTA Clears the GDTA interrupt masking 27 0 R W DU Clears the DU interrupt masking 26 0 R W SSI channel 1 Clears the SSI ch...

Page 343: ... R W DMAC 0 Clears DMAC channels 0 to 5 interrupt masking and address error interrupt 9 0 R W H UDI Clears H UDI interrupt masking 8 0 R W WDT Clears the WDT interrupt masking Clears interrupt masking for each on chip peripheral module When written 0 Invalid 1 Clears interrupt masking When read Always 0 7 0 R W SCIF channel 5 Clears SCIF channel 5 interrupt masking 6 0 R W SCIF channel 4 Clears SC...

Page 344: ...gister 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 R R R R R R R R R R R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 R R R R R R R R R R R R R R R R Bit Initial value R W 1 INT2B0 Detailed Interrupt Sources for the TMU Module Bit Name Detailed Source Description TMU 31 to 7 Reserved These bits are read as 0 and cannot be modified 6 TUNI5 TMU channel 5 underflow interr...

Page 345: ...F is made in the interrupt mask register 21 RXI5 SCIF channel 5 receive FIFO data full interrupt or receive data ready interrupt 20 ERI5 SCIF channel 5 receive error interrupt 19 TXI4 SCIF channel 4 transmit FIFO data empty interrupt 18 BRI4 SCIF channel 4 break interrupt or overrun error interrupt 17 RXI4 SCIF channel 4 receive FIFO data full interrupt or receive data ready interrupt 16 ERI4 SCIF...

Page 346: ...s even if the mask setting for SCIF is made in the interrupt mask register 8 ERI2 SCIF channel 2 receive error interrupt 7 TXI1 SCIF channel 1 transmit FIFO data empty interrupt 6 BRI1 SCIF channel 1 break interrupt or overrun error interrupt 5 RXI1 SCIF channel 1 receive FIFO data full interrupt or receive data ready interrupt 4 ERI1 SCIF channel 1 receive error interrupt 3 TXI0 SCIF channel 0 tr...

Page 347: ...ces even if the mask setting for DMAC is made in the interrupt mask register 10 DMINT9 Channel 9 DMA transfer end or half end interrupt 9 DMINT8 Channel 8 DMA transfer end or half end interrupt 8 DMINT7 Channel 7 DMA transfer end or half end interrupt 7 DMINT6 Channel 6 DMA transfer end or half end interrupt 6 DMAE0 Channels 0 to 5 DMA address error interrupt 5 DMINT5 Channel 5 DMA transfer end or...

Page 348: ...terrupt 8 PCIPWD1 PCIC power state D1 state interrupt 7 PCIPWD2 PCIC power state D2 state interrupt PCIC interrupt sources are indicated This register indicates the PCIC interrupt sources even if the mask setting for PCIC is made in the interrupt mask register 6 PCIPWD3 PCIC power state D3 state interrupt 5 PCIERR PCIC error interrupt 4 PCIINTD PCIC INTD interrupt 3 PCIINTC PCIC INTC interrupt 2 P...

Page 349: ...ata response interrupt data transfer end interrupt command response receive end interrupt command transmit end interrupt or data busy end interrupt 0 FSTAT FIFO empty interrupt or FIFO full interrupt 6 INT2B5 Detailed Interrupt Sources for the FLCTL Module Bit Name Detailed Source Description FLCTL 31 to 4 Reserved These bits are read as 0 and cannot be modified 3 FLTRQ1 FLCTL FLECFIFO transfer re...

Page 350: ...de in the interrupt mask register 23 to 20 Reserved These bits are read as 0 and cannot be modified 19 PORTH4I GPIO interrupt from port H pin 4 18 PORTH3I GPIO interrupt from port H pin 3 17 PORTH2I GPIO interrupt from port H pin 2 16 PORTH1I GPIO interrupt from port H pin 1 15 to 11 Reserved These bits are read as 0 and cannot be modified 10 PORTE5I GPIO interrupt from port E pin 5 9 PORTE4I GPIO...

Page 351: ...ailed Source Description GDTA 31 to 3 Reserved These bits are read as 0 and cannot be modified 2 GAERI GDTA error interrupt 1 GAMCI MC transfer end interrupt GDTA interrupt sources are indicated This register indicates the GDTA interrupt sources even if the mask setting for GDTA is made in the interrupt mask register 0 GACLI CL transfer end interrupt ...

Page 352: ...30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R R R R R W R W R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R R R R R R W R W R W R R R R R Bit Initial value R W Table 10 11 shows the correspondence between bits in INT2GPIC and the functions Table 10 11 Correspondence between Bits in INT2GPIC and GPIO Interrupts Bit Name In...

Page 353: ...pin 5 of port E 9 PORTE4E 0 R W Enables interrupt request from pin 4 of port E 8 PORTE3E 0 R W Enables interrupt request from pin 3 of port E 7 to 3 All 0 R W Reserved These bits are always read as 0 The write value should always be 0 2 PORTE2E 0 R W Enables interrupt request from pin 2 of port E 1 PORTE1E 0 R W Enables interrupt request from pin 1 of port E 0 PORTE0E 0 R W Enables interrupt reque...

Page 354: ...ected for up to six bus clock cycles When the INTMU bit in the CPUOPM is set to 1 the interrupt mask level IMASK in SR is automatically set to level 15 When the INTMU bit in CPUOPM is cleared to 0 the IMASK value in SR is not affected by accepting an NMI interrupt 10 4 2 IRQ Interrupts 1 Independence from ICR0 LVLMODE Setting The IRQ interrupt is valid when 1 is written to the IRLM0 and IRLM1 bits...

Page 355: ...n the INTC change the pin state of IRQ interrupts by interrupt routine and withdraw the request Then clear the source retained in INTREQ to 0 For details of clearing see section 10 7 3 Clearing IRQ and IRL Interrupt Requests b ICR0 LVLMODE 1 The INTC does not retain the IRQ interrupt source detected at the level detection 10 4 3 IRL Interrupts 1 Independence from ICR0 LVLMODE Setting The IRL inter...

Page 356: ...h Low Low 11 Level 11 interrupt request Low High Low High 10 Level 10 interrupt request Low High High Low 9 Level 9 interrupt request Low High High High 8 Level 8 interrupt request High Low Low Low 7 Level 7 interrupt request High Low Low High 6 Level 6 interrupt request High Low High Low 5 Level 5 interrupt request High Low High High 4 Level 4 interrupt request High High Low Low 3 Level 3 interru...

Page 357: ...riority is set lower To clear the retained IRL interrupt source change the pin state of IRL interrupts by interrupt routine and withdraw the interrupt request The clear the corresponding interrupt mask bit to 1 To clear the IRL interrupt request by pins IRQ IRL3 to IRQ IRL0 write 1 to the IM10 bit in INTMSK1 To clear the IRL interrupt request by pins IRQ IRL7 to IRQ IRL4 write 1 to the IM11 bit in...

Page 358: ...ned by hardware if the pin state is changed and the interrupt request is withdrawn 10 4 5 Priority of On Chip Peripheral Module Interrupts When any interrupt is generated the on chip peripheral module interrupt outputs the exception code specific to the source to SH 4A Accepting the interrupt Sh 4A indicates the corresponding INTEVT code in INTEVT An interrupt handler can identify the source by re...

Page 359: ...interrupt priority register thus H 02 to H 1F 30 priority levels 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 Figure 10 4 Priority of On Chip Peripheral Module Interrupts 10 4 6 Interrupt Exception Handling and Priority Table 10 13 shows the interrupt source codes for INTEVT and the order of interrupt priority A unique INTEVT code is allocated to each interrupt source The start address of...

Page 360: ...0 INTMSKCLR2 30 Low IRL 3 0 LLHL H 2 H 240 13 INTMSK2 13 INTMSKCLR2 13 High IRL 7 4 LLHL H 2 H B40 INTMSK2 29 INTMSKCLR2 29 Low IRL L Low level input H High level input See table 10 11 IRL 3 0 LLHH H 3 H 260 12 INTMSK2 12 INTMSKCLR2 12 High IRL 7 4 LLHH H 3 H B60 INTMSK2 28 INTMSKCLR2 28 Low IRL 3 0 LHLL H 4 H 280 11 INTMSK2 11 INTMSKCLR2 11 High IRL 7 4 LHLL H 4 H B80 INTMSK2 27 INTMSKCLR2 27 Low...

Page 361: ...LH H 9 H C20 INTMSK2 22 INTMSKCLR2 22 Low IRL L Low level input H High level input See table 10 11 IRL 3 0 HLHL H A H 340 5 INTMSK2 5 INTMSKCLR2 5 High IRL 7 4 HLHL H A H C40 INTMSK2 21 INTMSKCLR2 21 Low IRL 3 0 HLHH H B H 360 4 INTMSK2 4 INTMSKCLR2 4 High IRL 7 4 HLHH H B H C60 INTMSK2 20 INTMSKCLR2 20 Low IRL 3 0 HHLL H C H 380 3 INTMSK2 3 INTMSKCLR2 3 High IRL 7 4 HHLL H C H C80 INTMSK2 19 INTM...

Page 362: ...3 H 300 INTPRI 19 16 INTMSK0 28 INTMSKCLR0 28 INTREQ 28 IRQ 4 H 340 INTPRI 15 12 INTMSK0 27 INTMSKCLR0 27 INTREQ 27 IRQ 5 H 380 INTPRI 11 8 INTMSK0 26 INTMSKCLR0 26 INTREQ 26 IRQ 6 H 3C0 INTPRI 7 4 INTMSK0 25 INTMSKCLR0 25 INTREQ 25 IRQ 7 H 200 INTPRI 3 0 INTMSK0 24 INTMSKCLR0 24 INTREQ 24 WDT ITI H 560 INT2PRI3 12 8 INT2MSKR 8 INT2MSKCR 8 INT2A0 8 INT2A1 8 TMU ch0 TUNI0 H 580 INT2PRI0 28 24 INT2B...

Page 363: ... DMAE ch0 to ch5 H 6E0 INT2B3 6 Low SCIF ch0 ERI0 H 700 INT2B2 0 High RXI0 H 720 INT2PRI2 28 24 INT2MSKR 2 INT2MSKCLR 2 INT2A0 2 INT2A1 2 INT2B2 1 BRI0 H 740 INT2B2 2 TXI0 H 760 INT2B2 3 Low SCIF ch1 ERI1 H 780 INT2B3 4 High RXI1 H 7A0 INT2PRI2 20 16 INT2MSKR 3 INT2MSKCLR 3 INT2A0 3 INT2A1 3 INT2B3 5 BRI1 H 7C0 INT2B3 6 TXI1 H 7E0 INT2B3 7 Low DMAC 1 DMINT6 H 880 INT2B2 7 DMINT7 H 8A0 INT2B2 8 DMI...

Page 364: ...SCIF ch4 ERI4 INT2B1 16 RXI4 H 9C0 INT2PRI3 28 24 INT2MSKR 6 INT2MSKCLR 6 INT2A0 6 INT2A1 6 INT2B1 17 BRI4 INT2B1 18 TXI4 INT2B1 19 SCIF ch5 ERI5 INT2B1 20 RXI5 H 9E0 INT2PRI2 20 16 INT2MSKR 7 INT2MSKCLR 7 INT2A0 7 INT2A1 7 INT2B1 21 BRI5 INT2B1 22 TXI5 INT2B1 23 PCIC 0 PCISERR H A00 INT2PRI5 12 8 INT2MSKR 14 INT2MSKCLR 14 INT2A0 14 INT2A1 14 INT2B3 0 PCIC 1 PCIINTA H A20 INT2PRI5 4 0 INT2MSKR 15 ...

Page 365: ...gh TRAN H D20 INT2B4 1 ERR H D40 INT2PRI6 12 8 INT2MSKR 22 INT2MSKCLR 22 INT2A0 22 INT2A1 22 INT2B4 2 FRDY H D60 INT2B4 3 Low DU DUI H D80 INT2PRI9 28 24 INT2MSKR 27 INT2MSKCLR 27 INT2A0 27 INT2A1 27 GDTA GACLI H DA0 INT2B7 0 High GAMCI H DC0 INT2B7 1 GAERI H DE0 INT2PRI9 20 16 INT2MSKR 28 INT2MSKCLR 28 INT2A0 28 INT2A1 28 INT2B7 2 Low TMU ch3 TUNI3 H E00 INT2PRI1 28 24 INT2MSKR 1 INT2MSKCLR 1 INT...

Page 366: ... FC0 INT2B6 16 GPIOI2 Port H2 INT2B6 17 GPIOI2 Port H3 INT2B6 18 GPIOI2 Port H4 INT2B6 19 GPIOI3 Port L6 H FE0 INT2B6 24 GPIOI3 Port L7 INT2B6 25 Low Low Note ITI Interval timer interrupt TUNI0 to TUNI5 TMU channels 0 to 5 under flow interrupt TICPI2 TMU channel 2 input capture interrupt DMINT0 to DMINT11 Transfer end or half end interrupts for DMAC channel 0 to 11 DMAE0 DMAC address error interru...

Page 367: ...nter PC are saved in SSR and SPC respectively At that time R15 is saved in SGR 7 The BL MD and RB bits in SR are set to 1 8 Execution jumps to the start address of the interrupt exception handling routine the sum of the value set in the vector base register VBR and H 0000 0600 In the exception handling routine the value of INTEVT is branched as an offset This easily enables to branch the exception...

Page 368: ...No No No NMI No Yes No No Yes Is NMI input low Level 15 interrupt No No No Set interrupt source code in INTEVT Save SR in SSR save PC in SPC save R15 in SGR Set SR IMASK to accepted interrupt level Branch to exception handling routine Is SR IMASK level 14 or less Level 14 interrupt Level 1 interrupt NMI Is SR IMASK level 13 or less Is SR IMASK level 0 ICR0 NMIB 1 CPUOPM INTMU 1 Figure 10 5 Flowcha...

Page 369: ...ed to 0 software should be used to set the IMASK bit in SR to the priority level of the accepted interrupt 5 Execute processing as required in response to the interrupt 6 Set the BL bit in SR to 1 7 Release SSR and SPC from the stack 8 Execute the RTE instruction By following the above procedure if further interrupts are generated right after step 4 an interrupt with higher priority than the one c...

Page 370: ...rity determination time 6Bcyc 2Pcyc 8Bcyc 2Pcyc 4Bcyc 2Pcyc 5Pcyc 7Pcyc Wait time until the CPU finishes the current sequence S 1 0 Icyc Interval from the start of interrupt exception handling saving SR and PC until a SuperHyway bus request is issued to fetch the first instruction of the exception handling routine 11Icyc 1Scyc Response time Total S 10 Icyc 1Scyc 5Bcyc 2Pcyc S 10 Icyc 1Scyc 8Bcyc 2...

Page 371: ...ty determination time 1Pcyc 8Bcyc 2Pcyc 1Pcyc 4Pcyc Wait time until the CPU finishes the current sequence S 1 0 Icyc Interval from the start of interrupt exception handling saving SR and PC until a SuperHyway bus request is issued to fetch the first instruction of the exception handling routine 11Icyc 1Scyc Response time Total S 10 Icyc 1Scyc 1Pcyc S 10 Icyc 1Scyc 8Bcyc 2Pcyc S 10 Icyc 1Scyc 1Pcyc...

Page 372: ... from the interrupt enable state to the interrupt disable state Table 10 16 Response Time after Changing the Value of Interrupt Enable Disable Registers Interrupt Enabled Interrupt Disabled Number of States IRL IRQ Peripheral Modules Remarks Item INTMSK1 INTMSK2 INTMSK0 INT2MSKR INT2GPIC Registers that enable disable interrupts Priority determination time 1Pcyc 8Bcyc 2Pcyc 1Pcyc 4Pcyc Note The IRL...

Page 373: ...ddress that has been written to 1 Set the corresponding bit in INTMSK0 1 to 1 2 Set the corresponding bit in INTMSKCLR0 1 to 1 3 Read INTMSK0 1 Start of IRQ level sense or IRL level encoded interrupt handling Wait until the interrupt request signal input on the IRL IRQ pin is negated and the INTC detects the negation at least 8 bus clock cycles are required Figure 10 6 Example of Interrupt Handlin...

Page 374: ...le 10 17 Switching Sequence of IRQ IRL 7 0 Pin Function Sequence Item Procedure 1 IRL interrupt request and IRQ interrupt request masking Write 1 to all bits in INTMSK0 and INTMSK1 except reserved bits 2 Setting IRL IRQ 7 4 pins to IRL7 to IRL4 Write 0 to the PMSEL14 bit in PMSELR Write 0 to the PL4MD1 PL4MD0 PL3MD1 PL3MD0 PL2MD1 PL2MD0 PL1MD1 PL1MD0 bits in PLCR 3 Setting IRQ IRL 7 0 pins to IRL ...

Page 375: ...0 Clearing IRL interrupt requests To clear the IRL interrupt requests from the IRQ IRL 3 0 pins write 1 to the IM10 bit in INTMSK1 To clear the IRL interrupt requests from the IRQ IRL 7 4 pins write 1 to the IM11 bit in INTMSK1 The IRL interrupt request being detected cannot be cleared even if masking is performed on INTMSK2 by the level Clearing IRQ interrupt requests at level detection To clear ...

Page 376: ...10 Interrupt Controller INTC Rev 1 00 Jan 10 2008 Page 346 of 1658 REJ09B0261 0100 ...

Page 377: ...f areas 0 to 6 Bus width of each area can be set by a register Only the area 0 bus width is set by an external pin Wait cycle insertion by the RDY pin Wait cycle insertion can be controlled by a program Type of memory to be connected is specifiable for each area Control signals are output for memory connected to each area Automatic wait cycle insertion to prevent data bus collision in consecutive ...

Page 378: ... 32 bits Byte control SRAM interface SRAM interface with byte control Connectable area 1 and 4 Settable bus width 64 32 and 16 bits PCMCIA interface Little endian only Wait cycle insertion can be controlled by a program Bus sizing function for I O bus width Supports the little endian Connectable area 5 and 6 Settable bus width 16 and 8 bits Prepared only for ATA device accesses ...

Page 379: ...nBCR BCR CSnPCR Memory controller Area controller Wait controller LBSC SuperHyway bus Module bus RDY CS0 to CS6 CE2A to CE2B BS RD R W WE7 to WE0 IORD IOWR REG IOIS16 Legend CSnWCR CSn wait control register n 0 to 6 CSnBCR CSn bus control register n 0 to 6 BCR Bus control register CSnPCR CSn PCMCIA control register n 5 and 6 Figure 11 1 Block Diagram of LBSC ...

Page 380: ...DU and ports D7 to D0 GPIO input output D31 to D24 ports F7 to F0 GPIO input output D23 to D16 ports G7 to G0 GPIO input output BS Bus Cycle Start O Signal that indicates the start of a bus cycle Asserted once for a burst transfer when the MPX interface is set Asserted in every data cycle in other burst transfers CS6 to CS0 Chip Select 6 to 0 O Chip select signals that indicates the area being acc...

Page 381: ... Data Enable 4 O Write strobe signal for D39 to D32 in SRAM interface setting Multiplexed with PCI Port R0 GPIO input output WE5 Data Enable 5 O Write strobe signal for D47 to D40 in SRAM interface setting Multiplexed with PCI Port R1 GPIO input output WE6 Data Enable 6 O Write strobe signal for D55 to D48 in SRAM interface setting Multiplexed with PCI Port R2 GPIO input output WE7 Data Enable 7 O...

Page 382: ...emory Type for Area 0 I Signals for setting area 0 bus width MODE5 MODE6 and MPX interface MODE7 high level selects SRAM and low level selects MPX at a power on reset by the PRESET pin MODE5 Multiplexed with SIOF_MCLK SIOF input MODE6 Multiplexed with SIOF_SYNC SIOF input output MODE7 Multiplexed with SCIF3_RXD SCIF input and FALE FLCTL output MODE8 Endian Switching I Signal for setting endian at ...

Page 383: ...cknowledge Signal O Data acknowledge in DMAC channel 1 Multiplexed with Port K0 GPIO input output DACK2 3 DMAC2 Acknowledge Signal O Data acknowledge in DMAC channel 2 Multiplexed with SCIF2_TXD SCIF output MMCCMD MMCIF input output SIOF_TXD SIOF output and Port K5 GPIO input output DACK3 3 DMAC3 Acknowledge Signal O Data acknowledge in DMAC channel 3 Multiplexed with SCIF2_SCK SCIF input output M...

Page 384: ...d and CS6 is asserted when areas 6 is accessed When the PCMCIA interface is selected for area 5 or 6 CE2A or CE2B is asserted along with CS5 or CS6 according to the accessed bytes H 0000 0000 H 8000 0000 H A000 0000 H C000 0000 H E000 0000 H FFFF FFFF H E400 0000 H 0000 0000 H 0400 0000 H 0800 0000 H 0C00 0000 H 1000 0000 H 1400 0000 H 1800 0000 H 1FFF FFFF H 1C00 0000 Area 0 CS0 Area 1 CS1 Area 2...

Page 385: ...6 32 64 2 Burst ROM 8 16 32 64 2 MPX 32 64 2 8 16 32 bits 32 bytes 2 H 0800 0000 to H 0BFF FFFF 64 Mbytes DDR2 SDRAM 3 16 32 8 16 32 bits 32 bytes SRAM 8 16 32 64 2 Burst ROM 8 16 32 64 2 MPX 32 64 2 8 16 32 bits 32 bytes 3 H 0C00 0000 to H 0FFF FFFF 64 Mbytes DDR2 SDRAM 3 16 32 8 16 32 bits 32 bytes SRAM 8 16 32 64 2 Burst ROM 8 16 32 64 2 MPX 32 64 2 Byte control SRAM 16 32 64 2 8 16 32 bits 32 ...

Page 386: ...ed the bus width should be 8 or 16 bits 6 Do not access the reserved area If the reserved area is accessed correct operation is not be guaranteed 7 If the LBSC is requested to perform 8 or 16 byte access by the bus master the LBSC performs accesses two or four times respectively with 32 bit access size Area 0 H 0000 0000 Area 1 H 0400 0000 Area 2 H 0800 0000 Area 3 H 0C00 0000 Area 4 H 1000 0000 A...

Page 387: ...s used set MODE12 and MODE11 to 1 and 0 respectively The relationship between MODE12 and MODE11 and bus mode is shown below MODE12 MODE11 Bus Mode D 63 32 and WE 7 4 0 0 PCI host 0 1 PCI normal 1 0 LBSC 1 1 DU When the SRAM or ROM interface is used in areas 0 to 6 a bus width of 8 16 32 or 64 bits can be selected by the CSn bus control register CSnBCR When the burst ROM interface is used a bus wid...

Page 388: ...2 1 are supported Both the IC memory card interface and the I O card interface are supported in areas 5 and 6 in the external memory space The PCMCIA interface is supported only in little endian mode Table 11 3 PCMCIA Interface Features Item Features Access Random access Data bus 8 16 bits Memory type Masked ROM OTPROM EPROM flash memory SRAM ATA device Common memory capacity Max 64 Mbytes Attribu...

Page 389: ...ddress A11 I Address A11 11 A9 I Address A9 I Address A9 12 A8 I Address A8 I Address A8 13 A13 I Address A13 I Address A13 14 A14 I Address A14 I Address A14 15 WE I Write enable WE I Write enable WE1 16 READY O Ready IREQ O Interrupt request Sensed on port 17 VCC Operating power supply VCC Operating power supply 18 VPP1 VPP Programming power supply VPP1 VPP Programming peripheral power supply 19...

Page 390: ...4 41 D15 I O Data D15 I O Data D15 42 CE2 I Card enable CE2 I Card enable CE2A or CE2B 43 RFSH VS1 I Refresh request RFSH VS1 I Refresh request Output from port 44 RSRVD Reserved IORD I I O read IORD 45 RSRVD Reserved IOWR I I O write IOWR 46 A17 I Address A17 I Address A17 47 A18 I Address A18 I Address A18 48 A19 I Address A19 I Address A19 49 A20 I Address A20 I Address A20 50 A21 I Address A21...

Page 391: ...detection SPKR O Digital voice signal Sensed on port 63 BVD1 O Battery voltage detection STSCHG O Card status change Sensed on port 64 D8 I O Data D8 I O Data D8 65 D9 I O Data D9 I O Data D9 66 D10 I O Data D10 I O Data D10 67 CD2 O Card detection CD2 O Card detection Sensed on port 68 GND Ground GND Ground Notes 1 WP is not supported 2 Be careful of the polarity I O means input output in PCMCIA ...

Page 392: ... R W H FF80 2020 H 1F80 2020 32 Bck CS4 Bus Control Register CS4BCR R W H FF80 2040 H 1F80 2040 32 Bck CS5 Bus Control Register CS5BCR R W H FF80 2050 H 1F80 2050 32 Bck CS6 Bus Control Register CS6BCR R W H FF80 2060 H 1F80 2060 32 Bck CS0 Wait Control Register CS0WCR R W H FF80 2008 H 1F80 2008 32 Bck CS1 Wait Control Register CS1WCR R W H FF80 2018 H 1F80 2018 32 Bck CS2 Wait Control Register C...

Page 393: ...tained Retained Retained CS4 Bus Control Register CS4BCR H 7777 77F0 Retained Retained Retained CS5 Bus Control Register CS5BCR H 7777 77F0 Retained Retained Retained CS6 Bus Control Register CS6BCR H 7777 77F0 Retained Retained Retained CS0 Wait Control Register CS0WCR H 7777 770F Retained Retained Retained CS1 Wait Control Register CS1WCR H 7777 770F Retained Retained Retained CS2 Wait Control R...

Page 394: ... reset or a manual reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AREASEL R W R W R W R R R R R R R R R R R R R BIt Initial value R W Code for writing H A5A5 Bit Bit Name Initial Value R W Description 31 t...

Page 395: ...ace area 4 H 1000 0000 to H 13FF FFFF as the PCI space and the other areas as the local bus space 100 Sets areas 2 to 5 H 0800 0000 to H 17FF FFFF as the DDR SDRAM space 101 Sets areas 2 to 5 H 0800 0000 to H 17FF FFFF as the local bus space 110 Sets area 4 H 1000 0000 to H 13FF FFFF as the PCI space and the other areas as the local bus space 111 Setting prohibited This register should be written ...

Page 396: ... R1 R0 Writing to MMSELR MOV L R0 R2 MOV L R0 R2 SYNCO The instruction to write to this register should be allocated to the uncacheable area P2 and to the area that is not affected by writing to this register This register should be written before enabling the instruction cache operand cache and MMU address translation and should not be rewritten until after a power on reset or manual reset is exe...

Page 397: ...e external pins MODE8 and MODE9 respectively Bit Bit Name Initial Value R W Description 31 ENDIAN x R Endian Flag The value on the external pin MODE8 that sets the endian mode is sampled and reflected in this bit at a power on reset by the PRESET pin This bit determines the endian for all spaces 0 Indicates that a low level is on the MODE8 pin at a power on reset and the LSI has been configured fo...

Page 398: ...0 R W Control Output Pin Pull Up Resistor Control Specifies the pull up resistor state A25 to A0 BS CSn RD WE R W CE2A and CE2B when the control output pins are high impedance This bit is initialized at a power on reset 0 Pull up resistors for control output pins A25 to A0 BS CSn RD WE R W CE2A and CE2B are on 1 Pull up resistors for control output pins A25 to A0 BS CSn RD WE R W CE2A and CE2B are...

Page 399: ...cifies the priority of burst mode transfers by DMA channels 0 to 5 When this bit is cleared to 0 the priority is as follows bus release DMAC burst mode CPU DMAC PCIC When this bit is set to 1 the bus is not released until completion of the DMAC burst transfer This bit is initialized at a power on reset 0 DMAC burst mode transfer priority setting is off 1 DMAC burst mode transfer priority setting i...

Page 400: ...REQ2 ASYNC 4 DREQ1 ASYNC 3 DREQ0 ASYNC 2 IOIS16 ASYNC 1 BREQ ASYNC 0 RDY When asynchronous input is set ASYNCn 1 the sampling timing is one cycle before the synchronous input setting see figure 11 4 The timing shown in this section other sections and section 32 Electrical Characteristics is that with synchronous input setting ASYNCn 0 Note that the setup hold time must be satisfied when synchronou...

Page 401: ...s as specified with CSnBCR when the data buses may collide In the idle cycles CSn RD WEn CE2A CE2B BS and R W are set to high and the data bus is not driven CSnBCR is initialized to H 7777 77F0 at a power on reset but is not initialized by a manual reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 IWRRD IWRWS IWRWD IWW R W R W R W R R W R W R W R R W R W R W R R...

Page 402: ... cycles inserted 101 5 idle cycles inserted 110 6 idle cycles inserted 111 7 idle cycles inserted 27 0 R Reserved This bit is always read as 0 The write value should always be 0 26 to 24 IWRWD 111 R W Idle Cycles between Read Write in Different Spaces These bits specify the number of idle cycles to be inserted after the access of the memory connected to the space The target cycles are read write c...

Page 403: ...ed 010 2 idle cycles inserted 011 3 idle cycles inserted 100 4 idle cycles inserted 101 5 idle cycles inserted 110 6 idle cycles inserted 111 7 idle cycles inserted 19 0 R Reserved This bit is always read as 0 The write value should always be 0 18 to 16 IWRRD 111 R W Idle Cycles between Read Read in Different Spaces These bits specify the number of idle cycles to be inserted after the memory conne...

Page 404: ...space For details see section 11 5 8 Wait Cycles between Access Cycles 000 No idle cycle inserted 001 1 idle cycle inserted 010 2 idle cycles inserted 011 3 idle cycles inserted 100 4 idle cycles inserted 101 5 idle cycles inserted 110 6 idle cycles inserted 111 7 idle cycles inserted 11 10 BST 01 R W Burst Number These bits specify the number of bursts when the burst ROM interface is used The MPX...

Page 405: ...ely 01 8 bits 10 16 bits 11 32 bits Note The SZ bits in CS0BCR are read only When area 0 is set to the MPX interface by the MODE7 pin the SZ bits in CS0BCR should be set to 00 or 11 7 RDSPL 1 R W RD Hold Cycle Specifies the number of cycles to be inserted in the hold time for the read data sample timing of RD When setting this bit to 1 specify the number of RD negation CSn negation delay cycles se...

Page 406: ...cles inserted RDY pin enabled 110 6 idle cycles inserted RDY pin enabled 111 7 idle cycles inserted RDY pin enabled 3 MPX 0 R W MPX Interface Setting Selects the type of the MPX interface 0 Memory type set by bits TYPE2 to TYPE0 is selected 1 MPX interface is selected Note The MPX bit in CS0BCR is read only 2 to 0 TYPE 000 R W Memory Type Setting These bits specify the type of memory connected to ...

Page 407: ... reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 RDH RDS ADH ADS R W R W R W R R W R W R W R R W R W R W R R W R W R R W BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 1 IW 3 0 BSH WTH WTS R W R W R W R W R W R W R W R R W R W R W R W R W R W R R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 0 ...

Page 408: ... cycles inserted 101 5 cycles inserted 110 6 cycles inserted 111 7 cycles inserted 23 0 R Reserved This bit is always read as 0 The write value should always be 0 22 to 20 RDS 111 R W RD Setup Cycle CSn Assertion RD Assertion Delay Cycle These bits specify the number of cycles to be inserted as the time from CSn assertion to RD assertion Only valid only when the SRAM interface byte control SRAM in...

Page 409: ...100 4 cycles inserted 4 cycles delayed 101 5 cycles inserted 5 cycles delayed 110 6 cycles inserted 6 cycles delayed 111 7 cycles inserted 7 cycles delayed 15 0 R Reserved This bit is always read as 0 The write value should always be 0 14 to 12 WTS 111 R W WE Setup Cycle CSn Assertion WE Assertion Delay Cycle These bits specify the number of cycles to be inserted as the time from CSn assertion to ...

Page 410: ...d 011 3 cycles inserted 3 5 cycles delayed 100 4 cycles inserted 4 5 cycles delayed 101 5 cycles inserted 5 5 cycles delayed 110 6 cycles inserted 6 5 cycles delayed 111 7 cycles inserted 7 5 cycles delayed 7 0 R Reserved This bit is always read as 0 The write value should always be 0 6 to 4 BSH 000 R W BS Hold Cycle These bits specify the number of cycles to extend BS assertion The extension of t...

Page 411: ...serted 1011 13 cycles inserted 0100 4 cycles inserted 1100 15 cycles inserted 0101 5 cycles inserted 1101 17 cycles inserted 0110 6 cycles inserted 1110 21 cycles inserted 0111 7 cycles inserted 1111 25 cycles inserted When MPX interface is selected the wait cycles are inserted as follows according to the IW 2 0 setting The IW 3 setting is invalid The external wait cycles can be inserted by the RD...

Page 412: ...and WE assertion for the first half of area 5 and 6 are set by the IW bits in CSnWCR CSnPCR is initialized to H 7700 0000 by a power on reset but it is not initialized by a manual reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 PCIW PCWA PCWB SAB SAA R W R W R W R W R W R W R W R W R W R W R W R R W R W R R W BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 ...

Page 413: ...it attribute memory 23 22 PCWA 00 R W PCMCIA Wait A These bits specify the number of wait cycles for low speed PCMCIA which is added to the number set by the IW bits in CSnWCR The bit settings are selected when the access area of PCMCIA interface is the first half 00 No wait cycle inserted 01 15 wait cycles inserted 10 30 wait cycles inserted 11 50 wait cycles inserted 21 20 PCWB 00 R W PCMCIA Wai...

Page 414: ...f PCMCIA interface is the first half the number of wait cycles set by the IW bit in CSnWCR is selected 0000 No cycle inserted 0001 1 cycle inserted 0010 2 cycles inserted 0011 3 cycles inserted 0100 4 cycles inserted 0101 5 cycles inserted 0110 6 cycles inserted 0111 7 cycles inserted 1000 8 cycles inserted 1001 9 cycles inserted 1010 11 cycles inserted 1011 13 cycles inserted 1100 15 cycles inser...

Page 415: ...rted 101 9 wait cycles inserted 110 12 wait cycles inserted 111 15 wait cycles inserted 11 0 R Reserved This bit is always read as 0 The write value should always be 0 10 to 8 TEDB 000 R W OE WE Assert Delay B These bits set the delay time from address output to OE WE assertion when the second half area is accessed with the connected PCMCIA interface 000 No wait cycle inserted 001 1 wait cycle ins...

Page 416: ... cycles inserted 100 6 wait cycles inserted 101 9 wait cycles inserted 110 12 wait cycles inserted 111 15 wait cycles inserted 3 0 R Reserved This bit is always read as 0 The write value should always be 0 2 to 0 TEHB 000 R W OE WE Negation Address Delay B These bits set the delay time from OE WE negation to address hold when the second half area is accessed with the connected PCMCIA interface 000...

Page 417: ...access size multiple bus cycles are automatically generated to reach the access size In this case access is performed by incrementing the addresses corresponding to the bus width For example when a longword access is performed in the area with an 8 bit width with the SRAM interface each address is incremented by one and accesses are performed four times In the 32 byte transfer a total of 32 byte d...

Page 418: ...ata 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 32 Bytes 8n 1 Data 63 to 56 Data 55 to 48 Data 47 to 40 Data 39 to 32 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 8n 8 2 Data 127 to 120 Data 119 to 112 Data 111 to 104 Data 103 to 96 Data 95 to 88 Data 87 to 80 Data 79 to 72 Data 71 to 64 8n 16 3 Data 191 to 184 Data 183 to 176 Data 175 to 168 Data 167 to 160 Data 159 to 152 Data 151 to...

Page 419: ...ted Asserted Asserted Asserted Longword 8n 4 1 Asserted Asserted Asserted Asserted 32 Bytes 8n 1 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted 8n 8 2 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted 8n 16 3 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted 8n 24 4 Asserted Asserted Asserted Asserted Asserted Asserted Asserted A...

Page 420: ... to 8 Data 7 to 0 Asserted Asserted Asserted Asserted 32 Bytes 8n 1 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Asserted Asserted Asserted Asserted 8n 4 2 Data 63 to 56 Data 55 to 48 Data 47 to 40 Data 39 to 32 Asserted Asserted Asserted Asserted 8n 8 3 Data 95 to 88 Data 87 to 80 Data 79 to 72 Data 71 to 64 Asserted Asserted Asserted Asserted 8n 28 8 Data 255 to 248 Data 247 to 240 Data ...

Page 421: ... to 24 Data 23 to 16 Asserted Asserted Longword 4n 2 2 Data 15 to 8 Data 7 to 0 Asserted Asserted 32 Bytes 8n 1 Data 15 to 8 Data 7 to 0 Asserted Asserted 8n 2 2 Data 31 to 24 Data 23 to 16 Asserted Asserted 8n 4 3 Data 47 to 40 Data 39 to 32 Asserted Asserted 8n 30 16 Data 255 to 248 Data 247 to 240 Asserted Asserted Note This table shows an example when the access start address is on the 32 byte...

Page 422: ... 7 to 0 Asserted 4n 1 Data 31 to 24 Asserted 4n 1 2 Data 23 to 16 Asserted 4n 2 3 Data 15 to 8 Asserted Longword 4n 3 4 Data 7 to 0 Asserted 32 Bytes 8n 1 Data 7 to 0 Asserted 8n 1 2 Data 15 to 8 Asserted 8n 2 3 Data 23 to 16 Asserted 8n 31 32 Data 255 to 248 Asserted Note This table shows an example when the access start address is on the 32 byte boundary When the start address is not on the 32 b...

Page 423: ... Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 32 Bytes 8n 1 Data 63 to 56 Data 55 to 48 Data 47 to 40 Data 39 to 32 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 8n 8 2 Data 127 to 120 Data 119 to 112 Data 111 to 104 Data 103 to 96 Data 95 to 88 Data 87 to 80 Data 79 to 72 Data 71 to 64 8n 16 3 Data 191 to 184 Data 183 to 176 Data 175 to 168 Data 167 to 160 Data 159 to 152 Data 151 ...

Page 424: ...erted Asserted Asserted Asserted Longword 8n 4 1 Asserted Asserted Asserted Asserted 32 Bytes 8n 1 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted 8n 8 2 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted 8n 16 3 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted 8n 24 4 Asserted Asserted Asserted Asserted Asserted Asserted Asserted...

Page 425: ...15 to 8 Data 7 to 0 Asserted Asserted Asserted Asserted 32 Bytes 8n 1 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Asserted Asserted Asserted Asserted 8n 4 2 Data 63 to 56 Data 55 to 48 Data 47 to 40 Data 39 to 32 Asserted Asserted Asserted Asserted 8n 8 3 Data 95 to 88 Data 87 to 80 Data 79 to 72 Data 71 to 64 Asserted Asserted Asserted Asserted 8n 28 8 Data 255 to 248 Data 247 to 240 Dat...

Page 426: ...15 to 8 Data 7 to 0 Asserted Asserted Longword 4n 2 2 Data 31 to 24 Data 23 to 16 Asserted Asserted 32 Bytes 8n 1 Data 15 to 8 Data 7 to 0 Asserted Asserted 8n 2 2 Data 31 to 24 Data 23 to 16 Asserted Asserted 8n 4 3 Data 47 to 40 Data 39 to 32 Asserted Asserted 8n 30 16 Data 255 to 248 Data 247 to 240 Asserted Asserted Note This table shows an example when the access start address is on the 32 by...

Page 427: ...a 15 to 8 Asserted 4n 1 Data 7 to 0 Asserted 4n 1 2 Data 15 to 8 Asserted 4n 2 3 Data 23 to 16 Asserted Longword 4n 3 4 Data 31 to 24 Asserted 32 Bytes 8n 1 Data 7 to 0 Asserted 8n 1 2 Data 15 to 8 Asserted 8n 2 3 Data 23 to 16 Asserted 8n 31 32 Data 255 to 248 Asserted Note This table shows an example when the access start address is on the 32 byte boundary When the start address is not on the 32...

Page 428: ...al is ignored When the burst ROM interface is used the number of transfer cycles for a burst cycle is selected in the range from 2 to 9 according to the number of wait cycles The setup hold cycle of the address the assert delay cycle of the read write strobe signals for CS0 assertion and the CS0 negate delay cycle for the read write strobe signals negation can be set in the range from 0 to 7 cycle...

Page 429: ... is the SRAM MPX or burst ROM interface When the SRAM interface is used a bus width of 8 16 32 64 bits is selectable by bits SZ in CS2BCR When the MPX interface is used a bus width of 32 or 64 bits should be selected by bits SZ in CS2BCR When area 2 is accessed the CS2 signal is asserted In the case where the SRAM interface is set the RD signal which can be used as OE and write control signals WE0...

Page 430: ...nserted the RDY signal is ignored The setup hold time of the address the assert delay cycle of the read write strobe signals for CS3 assertion and the CS3 negate delay cycle for the read write strobe signals negation can be set in the range from 0 to 7 cycles by CS3WCR The BS hold cycles can be set to 1 or 2 when the RDS bits in CS3WCR are not 000 in reading and the WTS bits in CS3WCR are not 000 ...

Page 431: ... or 16 bits with SZ in CS5BCR For details see section 11 3 2 Memory Bus Width While the SRAM interface is used the CS5 signal is asserted when area 5 is accessed The RD signal which can be used as OE and write control signals WE0 to WE7 are also asserted While the PCMCIA interface is used the CE1A and CE2A signals the RD signal which can be used as OE the WE0 WE1 WE2 and WE3 signals which can be u...

Page 432: ... can be used as OE and the WE0 WE1 WE2 and WE3 signals which can be used as REG WE IORD and IOWR respectively are asserted For the number of bus cycles 0 to 25 wait cycles inserted by CS6WCR can be selected When the burst ROM interface is used the number of a burst pitch is selectable in the range from 0 to 7 with the BW bits in CS6BCR Any number of wait cycles can be inserted in each bus cycle th...

Page 433: ...negation period in accesses at minimum pitch In reading an access size is not specified The output of an access address on the address pins A25 to A0 is correct however since the access size is not specified 32 bit data is always output when a 32 bit device is in use and 16 bit data is output when a 16 bit device is in use During writing only the WE signal corresponding to the byte to be written i...

Page 434: ...LBSC Rev 1 00 Jan 10 2008 Page 404 of 1658 REJ09B0261 0100 T1 CLKOUT A25 to A0 CSn R W RD D31 to D0 In reading WEn D31 to D0 In writing BS T2 RDY DACKn In this example DACKn is high active Figure 11 5 Basic Timing of SRAM Interface ...

Page 435: ...amples of connections to SRAM with 32 16 and 8 bit data width respectively A16 A0 CS OE I O7 I O0 WE A18 A2 CSn RD D31 D24 WE3 D23 D16 WE2 D15 D8 WE1 D7 D0 WE0 SH7785 128K 8 bits SRAM A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE Figure 11 6 Example of 32 Bit Data Width SRAM Connection ...

Page 436: ...er LBSC Rev 1 00 Jan 10 2008 Page 406 of 1658 REJ09B0261 0100 A16 A0 CS OE I O7 I O0 WE A17 A1 CSn RD D15 D8 WE1 D7 D0 WE0 SH7785 128K 8 bits SRAM A16 A0 CS OE I O7 I O0 WE Figure 11 7 Example of 16 Bit Data Width SRAM Connection ...

Page 437: ...ycle Control Wait cycle insertion for the SRAM interface can be controlled by CSnWCR If the IW bits in CSnWCR are set to a value other than 0 a software wait is inserted in accordance with the wait control bits For details see section 11 4 4 CSn Wait Control Register CSnWCR The specified number of Tw cycles is inserted as wait cycles in accordance with the CSnWCR setting The wait cycle insertion t...

Page 438: ... 1658 REJ09B0261 0100 T1 CLKOUT A25 to A0 CSn R W RD D31 to D0 In reading WEn D31 to D0 In writing BS Tw T2 RDY DACKn In this example DACKn is active high The circle indicates the sampling timing Sampling Timing Figure 11 9 SRAM Interface Wait Timing Software Wait Only ...

Page 439: ...d at the transition from the Tw state to the T2 state Therefore the assertion of the RDY signal has no effect in the T1 cycle or in the first Tw cycle The RDY signal is sampled on the rising edge of the clock T1 CLKOUT A25 to A0 CSn R W RD In reading D31 to D0 In reading WEn In writing D31 to D0 In writing BS Tw Twe T2 RDY DACKn In this example DACKn is active high The circles indicate the samplin...

Page 440: ...trobe Write Strobe Timing When the SRAM interface is used the strobe signal negation timing in reading can be specified with the RDSPL bit in CSnBCR For details of settings see section 11 4 3 CSn Bus Control Register CSnBCR The RDSPL bit should be cleared to 0 when a byte control SRAM is specified ...

Page 441: ...wait CSnWCR IW 0100 TH1 TH2 RD negation CSn negation delay cycle CSnWCR RDH 010 WEn D31 D0 ADS 000 BS TS1 CSn assertion WEn assertion delay cycle CSnWCR WTS 001 TAS1 Address setup wait CSnWCR BSH 001 TAH1 Address hold wait CSnWCR ADH 001 Tw Access wait CSnWCR IW 0100 TH1 TH2 WE negation CSn negation delay cycle CSnWCR WTH 010 CLKOUT CLKOUT D31 D0 ADS 001 to 111 Notes 1 When CSnBCR RDSPL is set to ...

Page 442: ...BST0 in CSnBCR n 0 to 6 Similarly when 16 bit ROM is used 4 8 or 16 times can be set when 32 bit ROM is used 4 or 8 times can be set The RDY signal is always sampled when the wait cycle is set to 1 or more Even when no wait is specified in the burst ROM settings the second and subsequent accesses are performed with two cycles as shown in figure 11 13 Writing to this interface is performed in the s...

Page 443: ...Bus State Controller LBSC Rev 1 00 Jan 10 2008 Page 413 of 1658 REJ09B0261 0100 T1 TB1 TB2 TB1 TB2 TB1 TB2 T2 CLKOUT A25 to A5 A4 to A0 CSn R W RD D31 to D0 In reading BS RDY Figure 11 12 Burst ROM Basic Timing ...

Page 444: ...te Controller LBSC Rev 1 00 Jan 10 2008 Page 414 of 1658 REJ09B0261 0100 T1 Twe TB2 TB1 Tw TB2 Tw Tw TB1 TB2 Tw T2 TB1 CLKOUT A25 to A5 A4 to A0 CSn R W RD D31 to D0 In reading BS RDY Figure 11 13 Burst ROM Wait Timing ...

Page 445: ...15 of 1658 REJ09B0261 0100 2 TAS1 TS1 TB2 TB1 TB2 TB1 TB1 T1 TB2 T2 TAH1 TH1 CLKOUT A25 to A5 A4 to A0 CSn R W RD D31 to D0 In reading BS RDY DACKn 1 Notes 1 In this example DACKn is active high 2 When RDSPL in CSnBCR is set to 1 Figure 11 14 Burst ROM Wait Timing ...

Page 446: ...the IW bit in CSnWCR and the PCWB TEDB and TEHB bits in CSnPCR are selected The PCWA B1 and PCWA B bits can be used to set the number of wait cycles to be inserted in a low speed bus cycle as 0 15 30 or 50 This value is added to the number of inserted wait cycles specified by the IW bit in CSnWCR or PCIW bit in CSnPCR The setup time of the address of the RD and WE1 signals CSn CE2A CE2B and REG ca...

Page 447: ...egister CHCR is external request burst mode level detection overrun 0 DACK output to the correspondent PCMCIA connected area Set the DACKBST bit in BCR of the corresponding DMA transfer channel to 1 so that the corresponding DACK signal is asserted from the beginning to the end of the DMA transfer cycle Even if the corresponding DREQ signal is negated during the transfer the DACK signal is not neg...

Page 448: ...Invalid Upper write data Odd 16 Read 8 Even H L L Invalid Read data Odd L H H Read data Invalid 16 Even L L L Upper read data Lower read data Odd Write 8 Even H L L Invalid Write data Odd L H H Write data Invalid 16 Even L L L Upper write data Lower write data Odd Read 8 Even L H L L Invalid Read data Odd L L H H Read data Invalid Dynamic Bus Sizing 2 16 Even L L L L Upper read data Lower read dat...

Page 449: ...per read data Lower read data Read does not output DACK Odd 8 Even L H L Invalid Write data Odd 16 Even H L L Upper write data Lower write data Write does not output DACK Odd 8 Even H H L Invalid Read data Odd H H L Read data Invalid 16 Even H H H Upper read data Lower read data Read outputs DACK Odd 8 Even H H L Invalid Write data Odd H H L Write data Invalid Write outputs DACK 16 Even H H H Uppe...

Page 450: ...WE PGM IORD IOWR IOIS6 WAIT A25 to A0 D15 to D0 PC card memory I O CD1 CD2 CE1 CE2 OE WE PGM WAIT A25 to A0 SH7785 D15 to D0 R W CE2B CE2A RD WE1 CE1B CS6 CE1A CS5 ICIORD ICIOWR RDY IOIS16 G DIR D7 to D0 D15 to D8 G DIR G G G DIR G DIR D7 to D0 Card detection circuit Card detection circuit D15 to D8 REG REG REG Figure 11 16 Example of PCMCIA Interface ...

Page 451: ...e basic timing for the PCMCIA memory card interface and figure 11 18 shows the wait timing for the PCMCIA memory card interface CLKOUT Tpcm1 Tpcm2 A25 to A0 CExx R W D15 to D0 In reading D15 to D0 In writing RD In reading WE1 In writing BS REG DACKn DA In this example DACKn is active high Figure 11 17 Basic Timing for PCMCIA Memory Card Interface ...

Page 452: ...8 REJ09B0261 0100 CLKOUT Tpcm0 A25 to A0 R W CExx REG RD In reading D15 to D0 In reading D15 to D0 In writing WE1 In writing BS RDY Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w DACKn In this example DACKn is active high Figure 11 18 Wait Timing for PCMCIA Memory Card Interface ...

Page 453: ... performed using the IOIS16 pin With the 16 bit bus width selected if the IOIS16 signal is high during the word size I O bus cycle the I O port is recognized as eight bits in bus width In this case a data access for only eight bits is performed in the I O bus cycle being executed and this is automatically followed by a data access for the remaining eight bits Dynamic bus sizing is also performed f...

Page 454: ...8 Page 424 of 1658 REJ09B0261 0100 CLKOUT Tpci1 Tpci2 A25 to A0 R W CExx ICIORD In reading D15 to D0 In reading ICIOWR In writing D15 to D0 In writing BS REG DACKn In this example DACKn is active high Figure 11 19 Basic Timing for PCMCIA I O Card Interface ...

Page 455: ...09B0261 0100 CLKOUT A25 to A0 R W CExx ICIORD In reading ICIOWR In writing D15 to D0 In reading D15 to D0 In writing BS RDY IOIS16 Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w REG DACKn In this example DACKn is active high Figure 11 20 Wait Timing for PCMCIA I O Card Interface ...

Page 456: ...pci0 Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci2 Tpci1w Tpci2w CLKOUT A25 to A1 A0 R W IORD WE2 In reading IOWR WE3 In writing D15 to D0 In writing D15 to D0 In reading BS IOIS16 DACKn CExx REG RDY In this example DACKn is active high Figure 11 21 Dynamic Bus Sizing Timing for PCMCIA I O Card Interface ...

Page 457: ...re a negation cycle is not generated in the case of minimum pitch access The FRAME signal is asserted at the rising edge in Tm1 and negated at the start of the last data transfer cycle in the data phase Therefore an external device for the MPX interface must internally store the address information and access size output in the address phase and perform data input output for the data phase For det...

Page 458: ...CLK CS BS FRAME WE I O63 to I O0 RDY Figure 11 23 Example of 64 Bit Data Width MPX Connection The MPX interface timing is shown below When the MPX interface is used for area 0 the bus size should be set to 64 or 32 bits by MODE5 and MODE6 When the MPX interface is used for areas 1 to 6 the bus size should be set to 32 or 64 bits by CSnBCR Waits can be inserted by CSnWCR and the RDY pin In reading ...

Page 459: ...er LBSC Rev 1 00 Jan 10 2008 Page 429 of 1658 REJ09B0261 0100 Tm1 Tm1 CLKOUT RD FRAME CSn R W D63 to D0 BS Tmd1w Tmd1 RDY DACK A D0 A Figure 11 24 MPX Interface Timing 1 Single Read Cycle IW 0000 No External Wait 64 Bit Bus Width ...

Page 460: ...658 REJ09B0261 0100 Tm1 CLKOUT A RD FRAME CSn R W D63 to D0 BS Tmd1w Tmd1w Tmd1 RDY DACKn D0 In this example DACKn is active high The circles indicate the sampling timing Figure 11 25 MPX Interface Timing 2 Single Read IW 0000 One External Wait Inserted 64 Bit Bus Width ...

Page 461: ...431 of 1658 REJ09B0261 0100 Tm1 CLKOUT A RD FRAME CSn R W D63 to D0 BS Tmd1 RDY DACKn D0 In this example DACKn is active high The circle indicates the sampling timing Figure 11 26 MPX Interface Timing 3 Single Write Cycle IW 0000 No External Wait 64 Bit Bus Width ...

Page 462: ...008 Page 432 of 1658 REJ09B0261 0100 Tm1 CLKOUT A RD FRAME CSn R W D63 to D0 BS Tmd1w Tmd1w Tmd1 RDY DACKn D0 In this example DACKn is active high Figure 11 27 MPX Interface Timing 4 Single Write Cycle IW 0001 One External Wait Inserted 64 Bit Bus Width ...

Page 463: ...f 1658 REJ09B0261 0100 Tm1 CLKOUT RD FRAME CSn R W D63 to D0 BS Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 RDY DACKn D1 D2 D3 D0 A In this example DACKn is active high Figure 11 28 MPX Interface Timing 5 Burst Read Cycle IW 0000 No External Wait 64 Bit Bus Width 32 Byte Data Transfer ...

Page 464: ...EJ09B0261 0100 Tm1 CLKOUT A RD FRAME CSn R W D63 to D0 BS Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 RDY DACKn D3 D1 D2 D0 In this example DACKn is active high Figure 11 29 MPX Interface Timing 6 Burst Read Cycle IW 0000 External Wait Control 64 Bit Bus Width 32 Byte Data Transfer ...

Page 465: ...435 of 1658 REJ09B0261 0100 Tm1 CLKOUT A RD FRAME CSn R W D63 to D0 BS Tmd1 Tmd2 Tmd3 Tmd4 RDY DACKn D0 D1 D2 D3 In this example DACKn is active high Figure 11 30 MPX Interface Timing 7 Burst Write Cycle IW 0000 No External Wait 64 Bit Width 32 Byte Data Transfer ...

Page 466: ...J09B0261 0100 D2 D1 Tm1 CLKOUT A RD FRAME CSn R W D63 to D0 BS Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 RDY DACKn D0 D3 In this example DACKn is active high Figure 11 31 MPX Interface Timing 8 Burst Write Cycle IW 0001 External Wait Control 32 Bit Bus Width 32 Byte Data Transfer ...

Page 467: ...1 0100 Tm1 CLKOUT RD FRAME CSn R W D31 to D0 BS Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 RDY DACKn A In this example DACKn is active high D2 D3 D1 D4 D6 D7 D8 D5 Figure 11 32 MPX Interface Timing 9 Burst Read Cycle IW 0000 No External Wait 32 Bit Bus Width 32 Byte Data Transfer ...

Page 468: ...0261 0100 Tm1 CLKOUT A RD FRAME CSn R W D31 to D0 BS Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 RDY DACKn D7 D8 D2 D3 D1 In this example DACKn is active high Figure 11 33 MPX Interface Timing 10 Burst Read Cycle IW 0000 External Wait Control 32 Bit Bus Width 32 Byte Data Transfer ...

Page 469: ...261 0100 Tm1 CLKOUT A RD FRAME CSn R W D31 to D0 BS Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 RDY DACKn D1 D2 D3 D4 D5 D6 D7 D8 In this example DACKn is active high Figure 11 34 MPX Interface Timing 11 Burst Write Cycle IW 0000 No External Wait 32 Bit Bus Width 32 Byte Data Transfer ...

Page 470: ...0261 0100 D3 D2 Tm1 CLKOUT A RD FRAME CSn R W D31 to D0 BS Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 RDY DACKn D1 D7 D8 In this example DACKn is active high Figure 11 35 MPX Interface Timing 12 Burst Write Cycle IW 0001 External Wait Control 32 Bit Bus Width 32 Byte Data Transfer ...

Page 471: ...rted Assertion is synchronized with the falling edge of the CLKOUT clock in the same way as for the WEn signal while negation is synchronized with the rising edge of the CLKOUT clock in the same way as for the RD signal In 32 byte transfer a total of 32 bytes are transferred continuously according to the set bus width The first access is performed on the data for which there was an access request ...

Page 472: ...785 64K 16 bits SRAM D47 to D32 WE5 WE4 D31 to D16 WE3 WE2 D15 to D0 WE1 WE0 A15 to A0 CS OE WE I O15 to I O0 UB LB A15 to A0 CS OE WE I O15 to I O0 UB LB A15 to A0 CS OE WE I O15 to O0 UB LB A15 to A0 CS OE WE I O15 to I O0 UB LB D63 to D48 WE7 WE6 Figure 11 37 Example of Byte Control SRAM with 64 Bit Data Width ...

Page 473: ...er LBSC Rev 1 00 Jan 10 2008 Page 443 of 1658 REJ09B0261 0100 T1 T2 CLKOUT A25 to A0 CSn R W RD D31 to D0 In reading BS DACKn RDY WEn In this example DACKn is active high Figure 11 38 Basic Read Cycle of Byte Control SRAM No Wait ...

Page 474: ...nWCR AHS 001 Tw Access wait CSnWCR IW 0100 TH1 TH2 RD negation CSn negation delay cycle CSnWCR RDH 010 WEn D63 to D0 ADS 000 BS TS1 CSn assertion WEn assertion delay cycle CSnWCR WTS 001 TAS1 Address setup wait CSnWCR BSH 001 TAH1 Address hold wait CSnWCR ADH 001 Tw Access wait CSnWCR IW 0100 TH1 TH2 WE negation CSn negation delay cycle CSnWCR WTH 010 CLKOUT CLKOUT D63 to D0 ADS 001 to 111 Notes 1...

Page 475: ...an 10 2008 Page 445 of 1658 REJ09B0261 0100 T1 Tw Twe T2 CLKOUT A25 to A0 CSn R W RD D31 to D0 In reading BS DACKn RDY WEn In this example DACKn is active high Figure 11 40 Wait State Timing of Byte Control SRAM One Internal Wait One External Wait ...

Page 476: ...cle if there is a possibility that a bus collision occurs when the next access is started As an example of wait cycle insertion idle cycles are inserted between the access cycles as shown in section 11 4 3 CSn Bus Control Register CSnBCR By using bits IWW IWRWD IWRWS IWRRD and IWRRS in CSnBCR at least the specified number of cycles can be inserted as idle cycles When bus arbitration is performed t...

Page 477: ... of 1658 REJ09B0261 0100 T1 CLKOUT CSm CSn A25 to A0 BS R W RD D31 to D0 T2 Twait T1 T2 Twait T1 T2 Reading area m space CSnBCR IWRRD 001 CSnBCR IWRWS 001 Reading area n space Writing area n space Figure 11 41 Wait Cycles between Access Cycles Access Size Is 4 Bytes ...

Page 478: ...n of connected devices when the bus is transferred between master and slave all bus control signals are negated before the bus is released In addition when the bus mastership is received bus control signals begin driving the bus from the negated state Since the same signals are driven by the master and slave that exchange the bus output buffer collisions can be avoided Bus transfer is executed bet...

Page 479: ...W RD WEn D31 to D0 write BREQ BACK BS A25 to A0 CSn R W RD WEn BS D31 to D0 write Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Negated within 2 cycles Must be asserted for 2 cycles or more Must be negated within 2 cycles Slave mode device access Master access Slave access Master access Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Figure 11 42 Arbitration Sequence ...

Page 480: ...bus use permission signal is asserted in synchronization with the rising edge of the clock The address bus and data bus are put in a high impedance state in synchronous with the rising edge of the clock next to the BACK assertion At the same time the bus control signals BS CSn WEn RD R W CE2A and CE2B enters a high impedance state These bus control signals are negated no later than one cycle befor...

Page 481: ...signal is put in high impedance If the processor in slave mode starts access two or more cycles of BSACK signal assertion are required 11 5 12 Cooperation between Master and Slave To control system resources without contradiction by the master and slave their respective roles must be clearly defined as well as in the standby state implementing power down mode The design of the SH7785 provides for ...

Page 482: ...rning any setting should be correspondent to the system 11 5 15 Pins Multiplexed with Other Modules Functions Some pins used by the LBSC are multiplexed with general input output port GPIO and functions used in other peripheral modules The pins to be used by the LBSC should start access after setting these pins to the LBSC functions with GPIO register For example when PCMCIA interface is used the ...

Page 483: ...B 001 16 bytes 16 B 000 B 000 B 111 to B 001 8 32 bytes 32 B 000 B 111 to B 001 Byte 1 Undividable Word 1 Undividable Longword 2 B 000 B 111 to B 001 16 bytes 8 B 000 B 000 B 111 to B 001 16 32 bytes 16 B 000 B 111 to B 001 Byte 1 Undividable Word 1 Undividable Longword 1 Undividable 16 bytes 4 B 000 B 000 B 111 to B 001 32 32 bytes 8 B 000 B 111 to B 001 64 Byte 1 Undividable Word 1 Undividable L...

Page 484: ...Byte 1 Undividable Word 2 Undividable 1 Longword 4 Undividable 1 16 bytes 16 B 000 B 111 to B 001 2 8 32 bytes 32 Undividable 1 16 Byte 1 Undividable Word 1 Undividable Longword 2 Undividable 1 16 bytes 8 B 000 B 111 to B 001 2 32 bytes 16 Undividable 1 Notes means an arbitrary setting value When transfer is done in a single bus cycle DACKn is not divided up because DACKn is output once in DMA1 tr...

Page 485: ...e Bus Cycle Number IWRRD or IWRRS in CSnBCR IWRRD or IWRRS in CSnBCR Byte 1 Undividable Word 1 Undividable Longword 1 Undividable 16 bytes 4 Must be divided 32 32 bytes 1 Undividable 64 Byte 1 Undividable Word 1 Undividable Longword 1 Undividable 16 bytes 4 Must be divided 32 bytes 1 Undividable Note means an arbitrary setting value When transfer is done in a single bus cycle DACKn is not divided ...

Page 486: ...r IWW in CSnBCR IW1 and IW0 in CSnWCR IWW in CSnBCR Byte 1 Undividable Word 1 Undividable Longword 1 Undividable 16 bytes 4 B 000 B 11 to B 01 B 111 to B 001 32 32 bytes 1 Undividable 64 Byte 1 Undividable Word 1 Undividable Longword 1 Undividable 16 bytes 4 B 000 B 11 to B 01 B 111 to B 001 32 bytes 1 Undividable Note means an arbitrary setting value When transfer is done in a single bus cycle DA...

Page 487: ...signal DQS DQS Note RDQS is not supported Supports self refresh Supports power supply backup mode Supported DDR2 SDRAM addresses bit widths total capacity are as follows For details refer to tables 12 12 through 12 19 When using 8 bank products please refer to section 12 5 8 Important Information Regarding Use of 8 Bank DDR2 SDRAM Products DDR2 SDRAM data bus width 32 bits Two 256 Mbits 16M 16 bit...

Page 488: ...total capacity 512 Mbits One 512 Mbits 32M 16 bits connected in parallel total capacity 512 Mbits Two 512 Mbits 64M 8 bits connected in parallel total capacity 1 Gbit One 1 Gbit 64M 16 bits connected in parallel total capacity 1 Gbit Two 1 Gbit 128M 8 bits connected in parallel total capacity 2 Gbits One 2 Gbits 128M 16 bits connected in parallel total capacity 2 Gbits Two 2 Gbits 256M 8 bits conn...

Page 489: ...R2 SDRAM DBSC2 MCK0 MCK0 MCK1 MCK1 MBKPRST MVREF Notes Request queue Write data queue Response queue Control unit Registers DDRPAD Stores the access request of the SuperHyway bus Stores the write data sent from the SuperHyway bus Stores the read data to be sent back to the SuperHyway bus Controls each block depending on the request sent from the request queue Store timing parameters and SDRAM conf...

Page 490: ...ip select output signal MWE Write enable Output Write enable output signal MRAS Row address strobe Output Row address strobe output signal MCAS Column address strobe Output Column address strobe output signal MA14 to MA0 Addresses Output Address output signals MBA2 MBA1 MBA0 Bank active Output Bank address output signal MDQ31 to MDQ0 Data I O Data I O signals MDQS3 to MDQS0 I O data strobe I O Dat...

Page 491: ...nits 256M 8 bits are used with the external data bus width set to 32 bits Command related signals MCKE MWE MCS MRAS MCAS MA14 MA0 MBA2 MBA0 are connected in common to four DDR2 SDRAM units Data signals MDQ31 to MDQ0 MDQS3 to MDQS0 MDQS3 to MDQS0 and MDM3 to MDM0 are connected to memory in 8 bit units Clocks MCK1 and MCK1 are connected to DDR2 SDRAM corresponding to the data signal upper sides MDQ3...

Page 492: ... Connected 2 Connected 3 Memory 2 Connected 1 Connected 2 Connected 4 Memory 3 Connected 1 Connected 2 Connected 5 Memory 4 Connected 1 Connected 2 Connected 6 Notes 1 SDRAM pins should be connected as shown below Memory 1 and 2 Pins SH7785 Pins Memory 3 and 4 Pins SH7785 Pins CK MCK1 CK MCK0 CK MCK1 CK MCK0 2 SDRAM pins should be connected as shown below Memory 1 to 4 Pins SH7785 Pins Memory 1 to...

Page 493: ...wn below Memory 1 Pins SH7785 Pins DQS MDQS3 DQS MDQS3 DM MDM3 DQ7 MDQ31 DQ6 MDQ30 DQ5 MDQ29 DQ4 MDQ28 DQ3 MDQ27 DQ2 MDQ26 DQ1 MDQ25 DQ0 MDQ24 4 SDRAM pins should be connected as shown below Memory 2 Pins SH7785 Pins DQS MDQS2 DQS MDQS2 DM MDM2 DQ7 MDQ23 DQ6 MDQ22 DQ5 MDQ21 DQ4 MDQ20 DQ3 MDQ19 DQ2 MDQ18 DQ1 MDQ17 DQ0 MDQ16 ...

Page 494: ...s shown below Memory 3 Pins SH7785 Pins DQS MDQS1 DQS MDQS1 DM MDM1 DQ7 MDQ15 DQ6 MDQ14 DQ5 MDQ13 DQ4 MDQ12 DQ3 MDQ11 DQ2 MDQ10 DQ1 MDQ9 DQ0 MDQ8 6 SDRAM pins should be connected as shown below Memory 4 Pins SH7785 Pins DQS MDQS0 DQS MDQS0 DM MDM0 DQ7 MDQ7 DQ6 MDQ6 DQ5 MDQ5 DQ4 MDQ4 DQ3 MDQ3 DQ2 MDQ2 DQ1 MDQ1 DQ0 MDQ0 ...

Page 495: ...is 32 bits with a little endian the second access falling edge of DQS includes valid data if a byte access of address 8n 0 1 2 3 occurs Tables 12 5 to 12 8 show the correspondence with data on the external data bus for each access size During 16 byte and 32 byte accesses quad word 8 bytes access is combined and the SDRAM command is issued the necessary number of times according to the size to acce...

Page 496: ...th MDQS 1 0 32 bit width MDQ 31 0 16 bit width MDQ 15 0 32 bit width MDM 3 0 16 bit width MDM 1 0 Invalid Invalid Invalid Invalid READ bank A Invalid Invalid Invalid SDRAM command Invalid Invalid Invalid Invalid Invalid Invalid WRITE bank A Write data Read data Valid Valid Valid Valid Valid Valid Example of CL 3 High level 1st 2nd3rd 4th 1st 2nd3rd 4th Figure 12 2 Burst Access Operation ...

Page 497: ...Valid Invalid Invalid Invalid Longword access address 8n 0 Invalid Valid Invalid Invalid Longword access address 8n 4 Valid Invalid Invalid Invalid Quadword access address 8n 0 Valid Valid Invalid Invalid 2 Big Endian First Access Second Access Third Access Fourth Access Byte access address 8n 0 1 2 3 Valid Invalid Invalid Invalid Byte access address 8n 4 5 6 7 Invalid Valid Invalid Invalid Word a...

Page 498: ...address 8n 2 3 Invalid Invalid Valid Invalid Byte access address 8n 4 5 Invalid Valid Invalid Invalid Byte access address 8n 6 7 Valid Invalid Invalid Invalid Word access address 8n 0 Invalid Invalid Invalid Valid Word access address 8n 2 Invalid Invalid Valid Invalid Word access address 8n 4 Invalid Valid Invalid Invalid Word access address 8n 6 Valid Invalid Invalid Invalid Longword access addre...

Page 499: ...ss 8n 4 5 Invalid Invalid Valid Invalid Byte access address 8n 6 7 Invalid Invalid Invalid Valid Word access address 8n 0 Valid Invalid Invalid Invalid Word access address 8n 2 Invalid Valid Invalid Invalid Word access address 8n 4 Invalid Invalid Valid Invalid Word access address 8n 6 Invalid Invalid Invalid Valid Longword access address 8n 0 Valid Valid Invalid Invalid Longword access address 8n...

Page 500: ...0 Address 0 Data 7 to 0 Address 1 Data 7 to 0 Address 2 Data 7 to 0 Address 3 Data 7 to 0 Address 4 Data 7 to 0 Address 5 Data 7 to 0 Address 6 Data 7 to 0 Byte Address 7 Data 7 to 0 Address 0 Data 15 to 8 Data 7 to 0 Address 2 Data 15 to 8 Data 7 to 0 Address 4 Data 15 to 8 Data 7 to 0 Word Address 6 Data 15 to 8 Data 7 to 0 Longword Address 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 ...

Page 501: ...39 to 32 Address 0 Second access Address 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Table 12 6 Data Alignment for Access in Big Endian when External Data Bus Width Is Set to 32 Bits Access Size Address MDQ31 to MDQ24 MDQ23 to MDQ16 MDQ15 to MDQ8 MDQ7 to MDQ0 Byte Address 0 Data 7 to 0 Address 1 Data 7 to 0 Address 2 Data 7 to 0 Address 3 Data 7 to 0 Address 4 Data 7 to 0 Address 5 Data...

Page 502: ...ata 15 to 8 Data 7 to 0 Address 4 Data 15 to 8 Data 7 to 0 Address 6 Data 15 to 8 Data 7 to 0 Longword Address 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Address 4 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Quadword Address 0 First access Address 0 Data 63 to 56 Data 55 to 48 Data 47 to 40 Data 39 to 32 Address 0 Second access Address 4 Data 31 to 24 Data 23 to 16 Data 15 to ...

Page 503: ...6 Bits Access Size Address MDQ15 to MDQ8 MDQ7 to MDQ0 Byte Address 0 Data 7 to 0 Address 1 Data 7 to 0 Address 2 Data 7 to 0 Address 3 Data 7 to 0 Address 4 Data 7 to 0 Address 5 Data 7 to 0 Address 6 Data 7 to 0 Address 7 Data 7 to 0 Word Address 0 Data 15 to 8 Data 7 to 0 Address 2 Data 15 to 8 Data 7 to 0 Address 4 Data 15 to 8 Data 7 to 0 Address 6 Data 15 to 8 Data 7 to 0 ...

Page 504: ...nd access Address 0 Data 15 to 8 Data 7 to 0 Address 4 First access Address 6 Data 31 to 24 Data 23 to 16 Address 4 Second access Address 4 Data 15 to 8 Data 7 to 0 Quadword Address 0 First access Address 6 Data 63 to 56 Data 55 to 48 Address 0 Second access Address 4 Data 47 to 40 Data 39 to 32 Address 0 Third access Address 2 Data 31 to 24 Data 23 to 16 Address 0 Fourth access Address 0 Data 15 ...

Page 505: ... Bits Access Size Address MDQ15 to MDQ8 MDQ7 to MDQ0 Byte Address 0 Data 7 to 0 Address 1 Data 7 to 0 Address 2 Data 7 to 0 Address 3 Data 7 to 0 Address 4 Data 7 to 0 Address 5 Data 7 to 0 Address 6 Data 7 to 0 Address 7 Data 7 to 0 Word Address 0 Data 15 to 8 Data 7 to 0 Address 2 Data 15 to 8 Data 7 to 0 Address 4 Data 15 to 8 Data 7 to 0 Address 6 Data 15 to 8 Data 7 to 0 ...

Page 506: ...nd access Address 2 Data 15 to 8 Data 7 to 0 Address 4 First access Address 4 Data 31 to 24 Data 23 to 16 Address 4 Second access Address 6 Data 15 to 8 Data 7 to 0 Quadword Address 0 First access Address 0 Data 63 to 56 Data 55 to 48 Address 0 Second access Address 2 Data 47 to 40 Data 39 to 32 Address 0 Third access Address 4 Data 31 to 24 Data 23 to 16 Address 0 Fourth access Address 6 Data 15 ...

Page 507: ...s 3rd access 4th access 32n 0 32n 8 32n 16 32n 24 32 byte read access a total of four commands are issued 32n 0 32n 8 32n 16 32n 24 32n 16 32n 24 32n 0 32n 8 32n 16 32n 24 32n 0 32n 8 Address 32n 0 Address 32n 8 Address 32n 16 Address 32n 24 1st access 2nd access 3rd access 4th access 32n 0 32n 8 32n 16 32n 24 32 byte write access a total of four commands are issued 32n 0 32n 8 32n 16 32n 24 32n 1...

Page 508: ...e read access a total of two commands are issued 1st access 2nd access 32 byte write access a total of two commands are issued Address 32n 0 Address 32n 8 Address 32n 16 Address 32n 24 Address 32n 0 Address 32n 8 Address 32n 16 Address 32n 24 16n 0 16n 8 32n 0 32n 16 32n 0 32n 16 32n 16 32n 0 32n 16 32n 0 32n 0 32n 16 32n 0 32n 16 32n 16 32n 0 32n 16 32n 0 Figure 12 4 Addresses Generated upon 16 3...

Page 509: ... bit width is 32 bits and the longword size 32 bits should be used for register access If registers are accessed with sizes other than the longword size correct operation cannot be guaranteed The DBSC2 register area is in P4 addresses from H FE80 0000 to H FEFF FFFF and in area 7 addresses from H FE800000 to H FEFFFFFA If an address other than the register addresses indicated in table 12 9 is acce...

Page 510: ...g register 0 DBTR0 R W H FE80 0030 H 1E80 0030 32 DDRck SDRAM timing register 1 DBTR1 R W H FE80 0034 H 1E80 0034 32 DDRck SDRAM timing register 2 DBTR2 R W H FE80 0038 H 1E80 0038 32 DDRck SDRAM refresh control register 0 DBRFCNT0 R W H FE80 0040 H 1E80 0040 32 DDRck SDRAM refresh control register 1 DBRFCNT1 R W H FE80 0044 H 1E80 0044 32 DDRck SDRAM refresh control register 2 DBRFCNT2 R W H FE80...

Page 511: ...d Retained SDRAM timing register 0 DBTR0 H 0203 0501 Retained Retained SDRAM timing register 1 DBTR1 H 0001 0001 Retained Retained SDRAM timing register 2 DBTR2 H 0104 0303 Retained Retained SDRAM refresh control register 0 DBRFCNT0 H 0000 0000 Retained Retained SDRAM refresh control register 1 DBRFCNT1 H 0000 0200 Retained Retained SDRAM refresh control register 2 DBRFCNT2 H 1000 0080 Retained Re...

Page 512: ...R R R R R R BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 ENDN R R R R R R R R R R R R R R R R BIt Initial value R W Note Initial value is specified by external pin MODE8 Bit Bit Name Initial Value R W Description 31 to 9 All 0 R Reserved These bits are always read as 0 8 ENDN R Endian Display Bit Displays the endian of the DBSC2 set by external pin MO...

Page 513: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACEN R W R R R R R R R R R R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 Operation when a value other than 0 is written is not guaranteed 0 ACEN 0 R W SDRAM Access Enable Bit By setting this bit data accessing of SDRAM is enabled When set to 0 ac...

Page 514: ...ys read as 000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD0 CMD1 CMD2 R W R W R W R R R R R R R R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 3 All 0 R Reserved These bits are always read as 0 The wr...

Page 515: ...ntervals are values set in the SDRAM timing register described below When read these bits are always read as 000 Once writing is performed to enable the MCKE signal it remains enabled During self refresh control the MCKE goes to low level but on cancellation MCKE automatically returns to high level For details on the MCKE signal operation refer to section 12 5 13 Regarding MCKE Signal Operation 00...

Page 516: ...alue R W Description 31 to 24 All 0 R Reserved These bits are always read as 0 The write value should always be 0 Operation when a value other than 0 is written is not guaranteed 23 to 16 SPLIT7 to SPLIT0 1001 1010 R W Memory Configuration Select Bits These bits select the memory configuration to be used These are used in combination with the BASFT and the BWIDTH bits For details on address multip...

Page 517: ...ress downward 3 bits 7 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 Operation when a value other than 0 is written is not guaranteed 1 0 BWIDTH1 and BWIDTH0 01 R W SDRAM Bus Width Setting Bits These bits set the external data bus width 00 Setting prohibited If specified correct operation cannot be guaranteed 01 16 bits 10 32 bits 11 Setting prohibited If...

Page 518: ...value R W Bit Bit Name Initial Value R W Description 31 to 27 All 0 R Reserved These bits are always read as 0 The write value should always be 0 Operation when a value other than 0 is written is not guaranteed 26 to 24 CL2 to CL0 010 R W CAS Latency Setting Bits These bits set the CAS latency These bits should be set according to the DDR2 SDRAM specifications The number of cycles is the number of...

Page 519: ...E minimum period constraint for the same bank These bits should be set according to the DDR2 SDRAM specifications The number of cycles is the number of DDR clock cycles 0000 Setting prohibit If specified correct operation cannot be guaranteed 0010 Setting prohibit If specified correct operation cannot be guaranteed 0011 4 cycles 0100 5 cycles 1110 15 cycles 1111 Setting prohibit If specified corre...

Page 520: ...he number of DDR clock cycles 000 0000 Setting prohibit If specified correct operation cannot be guaranteed 000 0100 Setting prohibit If specified correct operation cannot be guaranteed 000 0101 6 cycles 000 0110 7 cycles 100 0001 66 cycles 100 0010 Setting prohibit If specified correct operation cannot be guaranteed 111 1111 Setting prohibit If specified correct operation cannot be guaranteed 7 t...

Page 521: ...bit If specified correct operation cannot be guaranteed 001 2 cycles 010 3 cycles 011 4 cycles 100 5 cycles 101 Setting prohibit If specified correct operation cannot be guaranteed 111 Setting prohibit If specified correct operation cannot be guaranteed Notes 1 AL Additive Latency supported by the DBSC2 is only 0 2 Writing to this register should be performed only when the following conditions are...

Page 522: ...l value R W Bit Bit Name Initial Value R W Description 31 to 19 All 0 R Reserved These bits are always read as 0 The write value should always be 0 Operation when a value other than 0 is written is not guaranteed 18 to 16 TRP2 to TRP0 001 R W tRP PRE ACT REF period Setting Bits These bits set the PRE ACT minimum period constraint for the same bank These bits should be set according to the DDR2 SDR...

Page 523: ... These bits set the ACT ACT minimum period constraint for the different banks These bits should be set according to the DDR2 SDRAM specifications The number of cycles is the number of DDR clock cycles 000 1 cycle 001 2 cycles 010 3 cycles 011 4 cycles 100 Setting prohibit If specified correct operation cannot be guaranteed 111 Setting prohibit If specified correct operation cannot be guaranteed 7 ...

Page 524: ...DR clock cycles 000 Setting prohibit If specified correct operation cannot be guaranteed 001 2 cycles 010 3 cycles 011 4 cycles 100 5 cycles 101 Setting prohibit If specified correct operation cannot be guaranteed 111 Setting prohibit If specified correct operation cannot be guaranteed Note Writing to this register should be performed only when the following conditions are met When SDRAM access is...

Page 525: ... W Bit Bit Name Initial Value R W Description 31 to 26 All 0 R Reserved These bits are always read as 0 The write value should always be 0 Operation when a value other than 0 is written is not guaranteed 25 24 TRTP1 and TRTP0 01 R W tRTP READ PRE command minimum time Setting Bits These bits set the READ PRE command minimum time constraint for the same bank These bits should be set according to the...

Page 526: ...ations The number of cycles is the number of DDR clock cycles 00000 Setting prohibit If specified correct operation cannot be guaranteed 00011 Setting prohibit If specified correct operation cannot be guaranteed 00100 5 cycles 00101 6 cycles 10010 19 cycles 10011 Setting prohibit If specified correct operation cannot be guaranteed 11111 Setting prohibit If specified correct operation cannot be gua...

Page 527: ...umber of cycles is the number of DDR clock cycles 0000 Setting prohibit If specified correct operation cannot be guaranteed 0010 Setting prohibit If specified correct operation cannot be guaranteed 0011 4 cycles 0100 5 cycles 1000 9 cycles 1001 Setting prohibit If specified correct operation cannot be guaranteed 1111 Setting prohibit If specified correct operation cannot be guaranteed 7 to 4 All 0...

Page 528: ...g prohibit If specified correct operation cannot be guaranteed 0010 Setting prohibit If specified correct operation cannot be guaranteed 0011 4 cycles 0100 5 cycles 1010 11 cycles 1011 Setting prohibit If specified correct operation cannot be guaranteed 1111 Setting prohibit If specified correct operation cannot be guaranteed Note Writing to this register should be performed only when the followin...

Page 529: ...R W Bit Bit Name Initial Value R W Description 31 to 17 All 0 R Reserved These bits are always read as 0 The write value should always be 0 Operation when a value other than 0 is written is not guaranteed 16 ARFEN 0 R W Auto Refresh Enable Bit Enables or disables automatic issue of auto refresh The auto refresh command is issued periodically according to the settings of DBRFCNT1 2 For details on t...

Page 530: ...gister 1 DBRFCNT1 The SDRAM refresh control register 1 DBRFCNT1 is a readable writable register It is initialized only upon power on reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 TREFI0 TREFI1 TREFI2 TREFI3 TREFI4 TREFI5 TREFI6 TREFI7 T...

Page 531: ...nterval count register The number of cycles is the number of DDR clock cycles 0 0000 0000 0000 Setting prohibited If specified correct operation cannot be guaranteed 0 0000 0011 1111 Setting prohibited If specified correct operation cannot be guaranteed 0 0000 0100 0000 65 cycles 0 0000 0100 0001 66 cycles 1 1111 1111 1111 8192 cycles Note Writing to this register should be performed only when the...

Page 532: ...me Initial Value R W Description 31 0 R Reserved This bit is always read as 0 The write value should always be 0 Operation when a value other than 0 is written is not guaranteed 30 to 16 LV1TH14 to LV1TH0 001 0000 0000 0000 R W Level 1 Threshold Setting Bits These bits set the threshold cycles for executing auto refresh when there is a vacancy in access requests received via the SuperHyway bus The...

Page 533: ...h is given priority over the next request Notes 1 The TREFI bit value of the DBRFCNT1 register and the LV1TH bit of this register are added and the result used as the maximum value of the auto refresh counter that is the maximum interval for refresh commands when periodically issuing auto refresh signals Specify the LV1TH bit value so that the maximum interval is within the maximum value of the AC...

Page 534: ...ription 31 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 Operation when a value other than 0 is written is not guaranteed 0 RFUDF 0 R W Refresh Counter Underflow Bit Set to 1 to indicate that the refresh counter has underflows when the refresh counter changes from 1 to 0 This bit is cleared to 0 by writing 0 to it Underflow may occur because the LV0TH bit...

Page 535: ... R R R R R R W R R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 9 All 0 R Reserved These bits are always read as 0 The write value should always be 0 Operation when a value other than 0 is written is not guaranteed 8 DLLRST 0 R W DLL Reset Bit Resets the DLL within DDRPAD The FREQ bits should be used to set the frequency when this bit is 0 If the FREQ bit is cha...

Page 536: ...up to 300 MHz DDR2 600 001 Reserved 010 200 MHz DDR2 400 100 to 111 Setting prohibited If specified correct operation cannot be guaranteed Note This register is used for initialization when canceling self refresh and when canceling power supply backup For details refer to section 12 5 3 Initialization Sequence section 12 5 4 Self Refresh Operation and 2 Recovery from SDRAM Power Supply Backup Mode...

Page 537: ...itial value R W Bit Bit Name Initial Value R W Description 31 to 25 All 0 R Reserved These bits are always read as 0 The write value should always be 0 Operation when a value other than 0 is written is not guaranteed 24 DDRSIG 0 R W Write Preamble Time Setting Bit Sets the preamble time of the DQS signal to be output when data is written to the DDR2 SDRAM The number of cycles is the number of DDR ...

Page 538: ...it should be set to the same value as the value set for DIC of EMRS 1 in the DDR2 SDRAM 0 Normal 1 Weak 15 to 13 All 0 R Reserved These bits are always read as 0 The write value should always be 0 If a value other than 0 is written correct operation cannot be guaranteed 12 11 ODTEN1 and ODTEN0 00 R W ODT Output Mode Switch These bits switch the ODT output mode For details on the note when the ODTE...

Page 539: ...g ODT Control Signal Output to SDRAM 0 Asserts the ODT pin to high for 3 cycles for one write command 1 Asserts the ODT pin to high for 4 cycles for one write command 9 8 T_ODT1 and T_ODT0 00 R W ODT Resistance Value Setting These bits set the resistance value of the ODT resistance within DDRPAD turned on for DDR2 SDRAM reading They should be set to the same value as the Rtt set in EMRS 1 of DDR2 ...

Page 540: ...Name Initial Value R W Description 31 to 19 Undefined W Reserved These bits are always read as 0 The write value should always be 0 If a value other than 0 is written correct operation cannot be guaranteed 18 to 16 BA2 to BA0 Undefined W SDRAM Mode Register and Extended Mode Register Setting Bits Bank address pins MBA2 MBA1 and MBA0 correspond to bit 18 bit 17 and bit 16 respectively 15 Undefined ...

Page 541: ...en the mode register setting MRS extended mode register setting EMRS command is issued for the DDR2 SDRAM Upon command execution settings should be made such that the burst length is 4 the mode is sequential access mode and the additive latency AL is 0 the DQS is enable and the RDQS is disable Further settings should be made such that the CAS latency CL write recovery WR is equal to the correspond...

Page 542: ...y the DBSC2 MCKE Function Symbol n 1 n MCS MRAS MCAS MWE MA 14 11 MA10 AP MBA 2 0 MA 9 0 Device deslect DSEL H H H X X X X X X X Read READ H H L H L H V L V V Write WRITE H H L H L L V L V V Bank activate ACT H H L L H H V V V V Precharge select bank PRE H H L L H L X L V X Precharge all banks PALL H H L L H L X H X X Auto refresh REF H H L L L H X X X X Self refresh entry from IDLE SLFRSH H L L L...

Page 543: ...ted When issuing the read command in the first cycle data is read with a burst length of 4 two DDR clock cycles so that it is necessary to wait until the third cycle to issue the second read command When access ends the DBSC2 leaves the bank open without using a precharge PRE command The bank is closed when 1 the following request is for the same bank with a different row address 2 there is an aut...

Page 544: ...onding to the following request queue page miss processing Only the PRE ACT command is issued in advance so there is no change in the read write order A PRE ACT command is issued in advance only when the following request 1 results in a page miss and moreover 2 entails access of a bank different from that of the request currently being processed Figure 12 6 shows an example of execution of precedi...

Page 545: ...CT command cannot be issued for the third read 8 byte request and as a result issuance of the PRE command corresponding to the fourth read 16 byte request is selected At time 4 it is possible to execute request processing for the first read 16 byte request and an ACT command is issued to the DDR2 SDRAM Thereafter the processing described above is repeated Request No 1 2 3 4 SDRAM command Request R...

Page 546: ... DBCONF the SDRAM timing register 0 DBTR0 the SDRAM timing register 1 DBTR1 and the SDRAM timing register 2 DBTR2 4 DLL settings are entered by writing them to the DDRPAD frequency setting register DBFREQ A Set DLLRST 0 B Set the frequency of DDRPAD in the FREQ bit C After DLLRST has been set to 1 the time interval of 100 μs that the DLL needs in order to stabilize is applied through the software ...

Page 547: ...issued and the OCD calibration mode exit command is issued 15 A 1 access enabled is set in the ACEN bit in the SDRAM operation enable register DBEN 16 Enter settings in the SDRAM refresh control register 1 DBRFCNT1 and the SDRAM refresh control register 2 DBRFCNT2 and set the auto refresh interval and other parameters 17 Set the ARFEN bit in DBRFCNT0 to 1 automatic issue of auto refresh enabled No...

Page 548: ... sure that the processing described in items 2 through 6 will not be disrupted by interrupts etc to assure the auto refresh interval 2 Set the SRFEN bit in DBRFCNT0 to 0 to cancel self refresh mode 3 Use the software to wait until access to the SDRAM is enabled The value for this time period must be at least as long as the time until the non read command is issued following cancellation of the sel...

Page 549: ...BSC2 or change the frequency Use the following procedure to cancel self refresh mode 1 Re start the clock supply and wait until the clock is being stably supplied to the DBSC2 2 Writing to the DDRPAD frequency setting register DBFREQ enters the DLL settings A Set DLLRST 0 B Set the DDRPAD frequency in the FREQ bit C After DLLRST 1 has been set use the software to wait the time necessary for the DL...

Page 550: ...est empty cycles Level 2 Refreshing is not done The threshold values for level 0 and level 1 are set using the LV0TH bit in the SDRAM refresh control register 2 DBRFCNT2 and the threshold values for level 1 and level 2 are set using the LV1TH bit The refresh timing is controlled using a 14 bit refresh counter The refresh counter counts down based on the DDR clock until a refresh is carried out Whe...

Page 551: ...shing is done during request empty cycles The counter value increments by the amount of the average refresh interval Figure 12 7 Relation between Auto Refresh Operation and Threshold Values 12 5 6 Regarding Address Multiplexing Memory of various sizes can be connected through the settings of the SDRAM configuration register DBCONF The BWIDTH bits are used to set the external data bus width and the...

Page 552: ...12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 ROW A12 A11 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 32M 16b COL A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 ROW A12 A11 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 64M 8b COL A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 ROW A11 A12 A13 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 64M 16b COL A11 A12 A13 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 ROW A1...

Page 553: ... A13 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 ROW A12 A13 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 32M 16b COL A12 A13 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 ROW A12 A13 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 64M 8b COL A12 A13 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 ROW A14 A12 A13 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 64M 16b COL A14 A12 A13 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 ROW ...

Page 554: ...11 A10 A12 A9 A8 A7 A6 A5 A4 A3 A2 A1 ROW A11 A10 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 32M 16b COL A11 A10 A12 A9 A8 A7 A6 A5 A4 A3 A2 A1 ROW A11 A10 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 64M 8b COL A11 A10 A12 A9 A8 A7 A6 A5 A4 A3 A2 A1 ROW A10 A11 A12 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 64M 16b COL A10 A11 A12 A13 A9 A8 A7 A6 A5 A4 A3 A2 A1 ROW A1...

Page 555: ... A12 A13 A10 A9 A8 A7 A6 A5 A4 A3 A2 ROW A11 A12 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 32M 16b COL A11 A12 A13 A10 A9 A8 A7 A6 A5 A4 A3 A2 ROW A11 A12 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 64M 8b COL A11 A12 A13 A10 A9 A8 A7 A6 A5 A4 A3 A2 ROW A13 A11 A12 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 64M 16b COL A13 A11 A12 A14 A10 A9 A8 A7 A6 A5 A4 A3 A2 ROW ...

Page 556: ... A10 A9 A12 A11 A8 A7 A6 A5 A4 A3 A2 A1 ROW A10 A9 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 32M 16b COL A10 A9 A12 A11 A8 A7 A6 A5 A4 A3 A2 A1 ROW A10 A9 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 64M 8b COL A10 A9 A12 A11 A8 A7 A6 A5 A4 A3 A2 A1 ROW A9 A10 A11 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 64M 16b COL A9 A10 A11 A13 A12 A8 A7 A6 A5 A4 A3 A2 A1 ROW A9 ...

Page 557: ...A11 A13 A12 A9 A8 A7 A6 A5 A4 A3 A2 ROW A10 A11 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 32M 16b COL A10 A11 A13 A12 A9 A8 A7 A6 A5 A4 A3 A2 ROW A10 A11 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 64M 8b COL A10 A11 A13 A12 A9 A8 A7 A6 A5 A4 A3 A2 ROW A12 A10 A11 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 64M 16b COL A12 A10 A11 A14 A13 A9 A8 A7 A6 A5 A4 A3 A2 ROW A...

Page 558: ...OL A9 A8 A12 A11 A10 A7 A6 A5 A4 A3 A2 A1 ROW A9 A8 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 32M 16b COL A9 A8 A12 A11 A10 A7 A6 A5 A4 A3 A2 A1 ROW A9 A8 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 64M 8b COL A9 A8 A12 A11 A10 A7 A6 A5 A4 A3 A2 A1 ROW A8 A9 A10 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 64M 16b COL A8 A9 A10 A13 A12 A11 A7 A6 A5 A4 A3 A2 A1 ROW A8 A...

Page 559: ... A10 A13 A12 A11 A8 A7 A6 A5 A4 A3 A2 ROW A9 A10 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 32M 16b COL A9 A10 A13 A12 A11 A8 A7 A6 A5 A4 A3 A2 ROW A9 A10 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 64M 8b COL A9 A10 A13 A12 A11 A8 A7 A6 A5 A4 A3 A2 ROW A11 A9 A10 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 64M 16b COL A11 A9 A10 A14 A13 A12 A8 A7 A6 A5 A4 A3 A2 ROW A1...

Page 560: ...asic SDRAM Access In this section waveforms at the various pins during basic SDRAM access including reading writing auto refresh and self refresh operations are explained For the relation between writing and the ODT control signal output refer to section 12 5 9 Important Information Regarding ODT Control Signal Output to SDRAM Figure 12 8 shows waveforms for 1 2 4 8 16 byte reading when the bus wi...

Page 561: ...valid Example of CL 3 Valid Valid Valid Valid Valid Valid High level READ Read data Figure 12 8 Waveforms for 1 2 4 8 16 Byte Reading When the Bus Width Is Set to 32 Bits Figure 12 9 shows waveforms for 32 byte reading when the bus width is set to 32 bits In this case the READ command is issued twice In this example read access processing is executed for bank A after the ACT command is issued but ...

Page 562: ...lid Valid Invalid Valid Valid Valid Valid Valid Valid High level Example of CL 3 Read data Figure 12 9 Waveforms for 32 Byte Reading When the Bus Width Is Set to 32 Bits Figure 12 10 shows waveforms for 1 2 4 8 16 byte writing when the bus width is set to 32 bits In this case single writing is performed in which the WRITE command is issued once In this example write access processing is executed f...

Page 563: ...valid Valid Valid Valid Valid Valid Valid High level Example of CL 3 Write data WRITE Figure 12 10 Waveforms for 1 2 4 8 16 Byte Writing When the Bus Width Is Set to 32 Bits Figure 12 11 shows waveforms for 32 byte writing when the bus width is set to 32 bits In this case the WRITE command is issued twice In this example write access processing is executed for bank A after the ACT command is issue...

Page 564: ...d Valid Valid Write data bank A WRITE WRITE Valid Valid Valid High level Figure 12 11 Waveforms for 32 Byte Writing When the Bus Width Is Set to 32 Bits Figure 12 12 shows waveforms during auto refresh operation resulting from settings of the SDRAM refresh control registers 0 1 and 2 The DBSC2 issues a REF command automatically after the PALL command is issued when at least one DDR2 SDRAM bank is ...

Page 565: ...Self Refresh Operation When performing processing according to the sequence in section 12 5 4 Self Refresh Operation commands to be issued to the SDRAM are those shown in figure 12 13 Before the transition to self refresh the PALL command is issued in software Then software is used to issue the REF command and the SLFRSH self refresh entry from IDLE command is issued The SDRAM continues in self re...

Page 566: ... Figure 12 13 Self Refresh Operation 2 Regarding Timing Constraints Figure 12 14 shows the relation between the settings of CL tRAS tRCD and tRP and the issuing of commands Figure 12 15 shows the relation to tRRD and tRTP figure 12 16 shows the relation to tWR figure 12 17 shows the relation to tRC figure 12 18 shows the relation to READ WRITE figure 12 19 shows the relation to WRITE READ and figu...

Page 567: ...mands until each of the constraints is satisfied MCK0 MCK1 MA 14 11 MA 9 0 MBA 2 0 MCKE MCS MRAS MCAS MWE MA 10 PRE bank A ACT bank A Valid Valid Valid Invalid READ bank A tRCD Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid MDQS 3 0 MDQ 31 0 MDM 3 0 Invalid Invalid Invalid Invalid Invalid PRE bank A SDRAM command Valid Valid Valid Valid Valid High level CL 3 cycles 3 cycles tRAS 9...

Page 568: ...d Valid Valid Valid Valid Valid Valid Valid High level Figure 12 15 tRRD and tRTP Figure 12 15 shows a case in which the pages for both of banks A and B are closed the page for bank C is open and a page hit has occurred When the tRRD time constraint has been satisfied starting from issue of the ACT command for bank A the ACT command for bank B is issued Because time tRCD has elapsed from the issue...

Page 569: ...lid Invalid SDRAM command ACT bank A Valid Valid Valid Invalid Invalid Invalid WRITE bank A Example of CL 3 WRITE Write data tWR 3 cycles Valid Valid Valid Valid Valid Valid Valid High level Figure 12 16 tWR Figure 12 16 shows a case in which after a write request access occurs requiring that bank B be closed After the issue of a WRITE command it is necessary to wait for time tWR or longer after o...

Page 570: ...tRC Figure 12 17 shows an example of performing auto refresh after read access of bank A the page for which had been closed After issuing an ACT command and READ command for bank A and performing data reading a PALL command must be used to close all banks in order to perform auto refresh In order to issue the PALL command the tRAS time constraint must be satisfied and issuing of the PALL command i...

Page 571: ...d READ any bank Invalid Invalid Invalid SDRAM command Invalid Invalid Write data Read data Valid Valid Valid Valid Valid Valid Example of CL 3 RDWR 4 cycles High level Figure 12 18 READ WRITE Minimum Time Figure 12 18 is an example of a case in which after issuing a READ command a WRITE command is issued In order to issue the WRITE command after issuing the READ command the DBSC2 waits for a minim...

Page 572: ...alid Invalid Invalid SDRAM command Invalid Invalid WRITE any bank Write data Read data WRRD 7 cycles Valid Valid Valid Valid Valid Valid Example of CL 3 High level Figure 12 19 WRITE READ Minimum Time Figure 12 19 is an example of a case in which after issuing a WRITE command a READ command is issued In order to issue the READ command after issuing the WRITE command the DBSC2 waits for a minimum t...

Page 573: ... MDQS 3 0 MDQ 31 0 MDM 3 0 Invalid Invalid Invalid Invalid REF SDRAM command READ any bank Invalid Invalid Invalid 6 cycles Valid Valid Valid Valid Valid Valid High level Figure 12 20 tRFC Figure 12 20 is an example of a case in which after issuing a REF command a READ request is issued In order to issue the ACT commend after issuing the REF command the DBSC2 waits for a time stipulated by tRFC ...

Page 574: ...or the bank corresponding to BA2 BA1 BA0 1 0 0 to open the page and accesses the memory Because the DBSC2 executes the above control if a program which is activated simultaneously is placed in an address area such that BA2 BA1 BA0 1 X Y and 0 X Y frequent page misses may result 12 5 9 Important Information Regarding ODT Control Signal Output to SDRAM The following should be noted when having the D...

Page 575: ...nal MODT to the SDRAM can be asserted at the same timing as the issue of the WRITE command If CL is 5 or greater MODT is asserted after the issue of the WRITE command However if CL is 3 or less MODT needs to be asserted before the issue of the WRITE command which is not supported by this LSI Resistor ON tAOND 2 cycles 3 cycles for product with CL 4 High level tAOFD 2 5 cycles Figure 12 21 ODT Cont...

Page 576: ...xtended for 1 cycle tAOFD 2 5 cycles If the interval from the READ command to the WRITE command is 4 cycles read data exists on the data bus when Rtt is turned on Therefore the interval should be 5 cycles Resistor ON 4 cycles for product with CL 5 High level Figure 12 22 Important Information on One Cycle Extension of ODT Control Signal 12 5 10 DDR2 SDRAM Power Supply Backup Function The SDRAM pow...

Page 577: ...is turned off To cancel the power supply backup state perform a power on reset As a result the DBSC2 registers are initialized and so the self refresh control circuit is also initialized In order to put the SDRAM into the self refresh state before power on reset when the internal CKE signal is indefinite and also during power on reset the MBKPRST signal must be held at low level Power on reset cau...

Page 578: ...resh disabled 4 Use the CMD bits in the SDRAM command control register DBCMDCNT to issue a PALL precharge all banks command 5 Use the CMD bits in DBCMDCNT to issue a REF auto refresh command 6 Set the SRFEN bit in DBRFCNT0 to 1 to make a transition to self refresh 7 Check that the SRFEN bit is 1 by reading the SDRAM refresh control register DBRFCNT0 8 Use a general purpose port or other means to c...

Page 579: ...d 10 Set the ACEN bit in the SDRAM operation enable register DBEN to 1 access enabled 11 Set the SDRAM refresh control registers 1 and 2 DBRFCNT1 and DBRFCNT2 12 Set the ARFEN bit in the SDRAM refresh control register 0 DBRFCNT0 to 1 automatic issue of auto refresh enabled Thereafter normal access is possible 12 5 11 Method for Securing Time Required for Initialization Self Refresh Cancellation et...

Page 580: ...CKE signal is output at a high level in this way the DBSC2 does not output a low level MCKE signal except when causing a transition to self refresh state Once the CMD bits in DBCMDCNT are set to 011 no matter what value is subsequently written to CMD the MCKE signal is never output at low level After the transition to self refresh state when 0 is written to SRFEN in DBRFCNT0 to release the self re...

Page 581: ...ation is performed by the external PCI bus arbiter 13 1 Features The PCIC has the following features Conforms to the subset of the PCI Local Bus Specification Revision 2 2 Operates at 33 or 66 MHz 32 bit data bus PCI master and target functions Conforms to the subset of the PCI Power Management Revision 1 1 Supports the host mode and normal mode PCI arbiter in host mode Supports four external mast...

Page 582: ...rnal interrupt output INTA in normal mode Both big endian and little endian are supported in SH7785 the PCI bus operates in little endian mode Note The following PCI functions are not supported Supports cache without the SBO and SDONE pins Address wraparound mechanism PCI JTAG this LSI supports JTAG Dual address cycles Interrupt acknowledge cycles Start of fast back to back transfer it is supporte...

Page 583: ...CICLK input Figure 13 1 Block Diagram of PCIC The PCIC comprises two blocks the PCI bus interface block and SuperHyway bus interface block The PCI bus interface block comprises the PCI configuration register local register PCI master controller and PCI target controller The SuperHyway bus interface converts the access from the PCI bus interface into the access to the SuperHyway bus and converts th...

Page 584: ...e of command and byte enable during the address phase and the data phases respectively PAR PAR TRI PCI Parity Generates checks even parity between AD 31 0 to C BE 3 0 PCICLK DCLKIN CLK IN PCI Clock Provides timing for all transactions on the PCI bus PCIFRAME VSYNC FRAME STRI PCI Frame Driven by the current initiator and indicates the start and duration of a transaction TRDY DISP TRDY STRI PCI Targ...

Page 585: ...n host mode DREQ3 INTC INTC IN Interrupt C Indicates that a PCI device is requesting PCI interrupts Only in host mode DREQ2 INTB INTB IN Interrupt B Indicates that a PCI device is requesting PCI interrupts Only in host mode INTA INTA O D Interrupt A Indicates that a PCI device is requesting PCI interrupts in host mode This signal is output so that the PCIC can request interrupts in normal mode REQ...

Page 586: ...on MODE12 MODE11 IN PCI Operating Mode Select 00 PCI host mode or PCI host bridge operation by PCICLK 01 PCI normal mode or non PCI host bridge operation by PCICLK 10 Local bus 64 bit mode the PCI disabled 11 DU mode the PCI disabled Legend TRI Tri state STRI Sustained tri state OD Open Drain IN Only input OUT Only output ...

Page 587: ...er PCISTATUS R W R W H FE04 0006 H 1E04 0006 PCIclk 32 16 8 PCI revision ID register PCIRID R R H FE04 0008 H 1E04 0008 PCIclk 32 16 8 PCI program interface register PCIPIF R W R H FE04 0009 H 1E04 0009 PCIclk 32 16 8 PCI sub class code register PCISUB R W R H FE04 000A H 1E04 000A PCIclk 32 16 8 PCI base class code register PCIBCC R W R H FE04 000B H 1E04 000B PCIclk 32 16 8 PCI cache line size r...

Page 588: ...PCIPCDD R W R H FE04 0047 H 1E04 0047 PCIclk 32 16 8 PCI local register space physical address H FE04 0100 to H FE04 03FF PCI control register PCICR R W R H FE04 0100 H 1E04 0100 PCIclk 32 16 8 PCI local space register 0 PCILSR0 R W R H FE04 0104 H 1E04 0104 PCIclk 32 16 8 PCI local space register 1 PCILSR1 R W R H FE04 0108 H 1E04 0108 PCIclk 32 16 8 PCI local address register 0 PCILAR0 R W R H F...

Page 589: ... 32 16 8 PCI memory bank mask register 2 PCIMBMR2 R W H FE04 01F4 H 1E04 01F4 PCIclk 32 16 8 PCI I O bank register PCIIOBR R W H FE04 01F8 H 1E04 01F8 PCIclk 32 16 8 PCI I O bank master register PCIIOBMR R W H FE04 01FC H 1E04 01FC PCIclk 32 16 8 PCI cache snoop control register 0 PCICSCR0 R W H FE04 0210 H 1E04 0210 PCIclk 32 16 8 PCI cache snoop control register 1 PCICSCR1 R W H FE04 0214 H 1E04...

Page 590: ... PCILTM H 00 Retained Retained PCI header type register PCIHDR H 00 Retained Retained PCI BIST register PCIBIST H 00 Retained Retained PCI I O base address register PCIIBAR H 0000 0001 Retained Retained PCI Memory base address register 0 PCIMBAR0 H 0000 0000 Retained Retained PCI Memory base address register 1 PCIMBAR1 H 0000 0000 Retained Retained PCI subsystem vendor ID register PCISVID H 0000 R...

Page 591: ...d Retained PCI arbiter bus master error information register PCIBMIR H 0000 00xx Retained Retained PCI PIO address register PCIPAR H 80xx xxxx Retained Retained PCI power management interrupt register PCIPINT H 0000 0000 Retained Retained PCI power management interrupt mask register PCIPINTM H 0000 0000 Retained Retained PCI memory bank register 0 PCIMBR0 H 0000 0000 Retained Retained PCI memory b...

Page 592: ...0 0 0 0 0 0 ENBL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 1 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 0 ENBL 0 SH R W PCI PCI Enable Bit Enables validates the PCIC When this bit is 0 the PCIC is disabled and the access from the CPU to the PCIC or from the external PCI device to the PCIC...

Page 593: ...R R Bit Initial value SH R W R R R R R R R R R R R R R R R R PCI R W Bit Bit Name Initial Value R W Description 15 to 0 VID H 1912 SH R PCI R PCI Vender ID These bits indicate the vender ID that is allocated by PCI SIG Renesas Technology s vendor ID is H 1912 2 PCI Device ID Register PCIDID This field defines the PCI device ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 D...

Page 594: ...ts are always read as 0 The write value should always be 0 9 FBBE 0 SH R PCI R PCI Fast Back to Back Enable Specifies whether fast back to back control is performed on the different devices or not when the PCIC is a master 0 Enables fast back to back control for the same target 1 Enables fast back to back control for different targets not supported 8 SERRE 0 SH R W PCI R W SERR Output Control Cont...

Page 595: ...date command can be executed not supported 3 SC 0 SH R PCI R Special Cycle Control This bit indicates whether special cycles are supported when the PCIC is a target 0 Special cycles ignored 1 Special cycles monitored not supported 2 BM 0 SH R W PCI R W PCI Bus Master Control Controls a bus master 0 Bus master disabled 1 Bus master enabled 1 MS 0 SH R W PCI R W PCI Memory Space Control This bit con...

Page 596: ...al value SH R W R R R R R R R R R WC R R R WC R WC R WC R WC R WC PCI R W Bit Bit Name Initial Value R W Description 15 DPE 0 SH R WC PCI R WC Parity Error Detect Status Indicates that a parity error was detected in read data when the PCIC is a master or in write data when the PCIC is a target This bit is set regardless of the value of parity error response bit 0 Device did not detect parity error...

Page 597: ... target abort 10 9 DEVSEL 01 SH R PCI R DEVSEL Timing Status This bit indicate the response timing status of DEVSEL when the PCIC is a target 00 Fast not support 01 Medium 10 Slow not support 11 Reserved 8 MDPE 0 SH R WC PCI R WC Data Parity Error This bit indicates that the PCIC asserted PERR or detected the assertion of PERR when the PCIC is a master This bit is set to 1 only when the parity res...

Page 598: ...ded function Indicates whether the PCI power management is supported 0 Power management not supported 1 Power management supported 3 to 0 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 5 PCI Revision ID Register PCIRID PCIRID specifies a revision identifier specific to a PCI device 0 1 2 3 4 5 6 7 x x x x x x x x RID R R R R R R R R Bit Initial value S...

Page 599: ... value of this bit is updated The value is not updated after initialization PCICR CFINT 1 6 to 4 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 3 PIS 0 SH R W PCI R PCI Programmable Indicator Secondary If this bit is written during register initialization PCICR CFINT 0 in the PCIC the value of this bit is updated The value is not updated after initiali...

Page 600: ...alue is not updated after initialization PCICR CFINT 1 7 PCI Sub Class Code Register PCISUB This field defines the sub class code For details of the code value see appendix D in PCI Local Bus Specification Revision 2 2 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 SUB R W R W R W R W R W R W R W R W Bit Initial value SH R W R R R R R R R R PCI R W Bit Bit Name Initial Value R W Description 7 to 0 SUB H 00 SH R ...

Page 601: ... W R W Bit Initial value SH R W R R R R R R R R PCI R W Bit Bit Name Initial Value R W Description 7 to 0 BCC H xx SH R W PCI R Base Class Code These bits indicate the base class code The initial value is H xx 9 PCI Cache Line Size Register PCICLS 0 1 2 3 4 5 6 7 0 0 0 0 0 1 0 0 CLS R R R R R R R R Bit Initial value SH R W R R R R R R R R PCI R W Bit Bit Name Initial Value R W Description 7 to 0 C...

Page 602: ...ycle when the PCIC is a master 11 PCI Header Type Register PCIHDR R R R R R R R R PCI R W 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 HDR MFE R R R R R R R R Bit Initial value SH R W Bit Bit Name Initial Value R W Description 7 MFE 0 SH R PCI R Multiple Function Enable HEAD7 Indicates whether the device is multi function or single function 0 Single function device 1 The device has two to eight multifunction d...

Page 603: ...7 0 0 0 0 0 0 0 0 BISTC R R R R R R R R Bit Initial value SH R W Bit Bit Name Initial Value R W Description 7 BISTC 0 SH R PCI R This bit is used for the BIST function control and status 0 Function not available 1 Function available not supported 6 to 0 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 ...

Page 604: ...25 26 27 28 29 31 30 IOB1 upper 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value SH R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W PCI R W Bit Bit Name Initial Value R W Description 31 to 8 IOB1 upper H 000000 SH R W PCI R W I O Space Base Address upper 24 bits These bits specify the upper 24 bits of the base add...

Page 605: ...0 0 0 0 R R R R R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value SH R W R R R R R W R W R W R W R W R W R W R W R W R W R W R W PCI R W Bit Bit Name Initial Value R W Description 31 to 20 MBA1 H 000 SH R W PCI R W Memory Space 0 Base Address upper 12 bits These bits specify the upper 12 bits of memory base address for the local address space 0 the address space in the internal bus...

Page 606: ...ch can be performed in local address space 0 0 Prefetch disabled 1 Prefetch enabled not supported 2 1 LAT 00 SH R PCI R Memory Type These bits indicate the memory type of local address space 0 00 Base address can be set to 32 bit width and 32 bit space 01 Reserved 10 Base address is set to 64 bit width Not supported 11 Reserved 0 ASI 0 SH R PCI R Address Space Indicator Indicates whether the base ...

Page 607: ...0 0 0 0 R R R R R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value SH R W R R R R R W R W R W R W R W R W R W R W R W R W R W R W PCI R W Bit Bit Name Initial Value R W Description 31 to 20 MBA1 H 000 SH R W PCI R W Memory Space 1 Base Address upper 12 bits These bits specify the upper 12 bits of memory base address for the local address space 1 the address space in the internal bus...

Page 608: ...fetch can be performed in local address space 1 0 Prefetch disabled 1 Prefetch enabled not supported 2 1 LAT 00 SH R PCI R Memory Type These bits indicate the memory type of local address space 1 00 Base address can be set to 32 bit width and 32 bit space 01 Reserved 10 Base address is set to 64 bit width Not supported 11 Reserved 0 ASI 0 SH R PCI R Address Space Indicator Indicates whether the ba...

Page 609: ...he initialization CFINIT 0 in PCICR in the PCIC The value is not updated when these bits are written after initialization CFINIT 1 in PCICR 17 PCI Subsystem ID Register PCISID See description of each register in PCI Local Bus Specification Revision 2 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 SID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initi...

Page 610: ...SH R PCI R Capabilities Pointer These bits indicate the offset of the expansion function power management ID register 19 PCI Interrupt Line Register PCIINTLINE 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 INTLINE R W R W R W R W R W R W R W R W Bit Initial value SH R W R W R W R W R W R W R W R W R W PCI R W Bit Bit Name Initial Value R W Description 7 to 0 INTLINE H 00 SH R W PCI R W PCI Interrupt Line These ...

Page 611: ... is used as connection destination when the PCIC outputs interrupt requests The initial value is H 01 H 00 PCI interrupt pins not used H 01 INTA used H 02 INTB used H 03 INTC used H 04 INTD used H 05 to H FF Reserved 21 Minimum Grant Register PCIMINGNT This register is not programmable 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 MINGNT R R R R R R R R Bit Initial value SH R W R R R R R R R R PCI R W Bit Bit N...

Page 612: ...I R Maximum Latency Specification MILAT7 to MILAT0 These bits specify the maximum time from requesting the bus mastership by the PCI master device to acquiring bus not supported 23 PCI Capability Identifier Register PCICID 0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 0 CID R R R R R R R R Bit Initial value SH R W R R R R R R R R PCI R W Bit Bit Name Initial Value R W Description 7 to 0 CID H 01 SH R PCI R Extens...

Page 613: ...cates the location of the next item in the list of extension function 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 NIP R R R R R R R R Bit Initial value SH R W R R R R R R R R PCI R W Bit Bit Name Initial Value R W Description 7 to 0 NIP H 00 SH R PCI R Next Item Pointer H 00 Indicates that power management function is listed as the last item ...

Page 614: ...lue R W Description 15 to 11 PMCS 00000 SH R PCI R PME SUPPORT This 5 bit field indicates the power state that asserts PME by using this power management function When these bits are 0 these bits indicate that this function cannot assert PME at that power state not supported Bit11 xxxx1 PME can be asserted from D0 Bit12 xxx1x PME can be asserted from D1 Bit13 xx1xx PME can be asserted from D2 Bit1...

Page 615: ... the proper initialization is not required 4 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 3 PMEC 1 SH R W PCI R PCI PME Clock Specifies whether the clock is required to support PME 0 The clock is not required to support PME Note The PCIC in this LSI dose not have the PME pin 2 to 0 PMV 010 SH R W PCI R Version Indicates the version of the power managemen...

Page 616: ...al value SH R W R W R W R R R R R R R R R R R R R R PCI R W Bit Bit Name Initial Value R W Description 15 PMES 0 SH R PCI R PME Status Indicates the state of the PME signal not supported Note The PCIC in this LSI dose not has the PME pin 14 13 DSC 00 SH R PCI R Data Scale These bits specify the scaling value of data field not supported 12 to 9 DSL 0000 SH R PCI R Data Select These bits specify the...

Page 617: ...e Initial Value R W Description 1 0 PS 00 SH R W PCI R W Power State These bits specify the power state If an unsupported state is specified a state transition is not made However the register is written normally and no error is indicated 00 D0 state 01 D1 state 10 D2 state 11 D3 hot state ...

Page 618: ...does not use the power state field in PCI_PMCSR of the bridge to control the power or clock of the secondary bus of the bridge 6 B2B3N 0 SH R PCI R The state of this bit determines the action to be taken as a result of programming that sets the power management function to the D3 hot state 0 Indicates that the power supplied to the secondary will be stopped B3 when the bridge function is set to th...

Page 619: ...pation For details see section 3 PCI Power Management Interface in PCI Bus Power Management Interface Specification Revision 1 1 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 PCDD R W R W R W R W R W R W R W R W Bit Initial value SH R W R R R R R R R R PCI R W Bit Bit Name Initial Value R W Description 7 to 0 PCDD H 00 SH R W PCI R This register is used to notify the state dependent data requested by the PCIPMC...

Page 620: ... 0 Bit Initial value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 x x 0 0 0 0 0 0 0 0 0 0 RST CTL CFINT IOCS R x BMAM TBS PFE FTO PFCS Bit Initial value Bit Bit Name Initial Value R W Description 31 to 24 H 00 SH R W PCI R Reserved These bits should be set to H A5 write H A5 to these bits only before bits 11 to 8 6 and 2 to 0 are written These bits are always read as 0 23 to 12 All 0 SH R PCI R Res...

Page 621: ...swapped when the PCI bus is accessed 0 No swap 1 Byte data is swapped For details see section 13 4 3 5 Endian or section 13 4 4 6 Endian 7 0 SH R PCI R Reserved This bit is always read as 0 The write value should always be 0 6 BMAM 0 SH R W PCI R Bus Master Arbitration Controls the PCI bus arbitration mode of the PCIC when the PCIC is in host mode This bit is ignored when the PCIC is in normal mod...

Page 622: ...te by setting this bit to 1 The PCIRST pin is output at low level at a power on reset 0 Negates PCIRST output at high level 1 Asserts PCIRST output at low level 0 CFINIT 0 SH R W PCI R PCIC Internal Register Initialization Control This bit should be set to 1 after the PCIC internal registers are initialized Setting this bit enables accesses from the PCI bus During initialization in host mode the b...

Page 623: ...itial value Bit Bit Name Initial Value R W Description 31 to 29 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 28 to 20 LSR 0 0000 0000 SH R W PCI R Size of Local Address Spaces 0 9 bits These bits specify the size of the local address space 0 address space for this LSI internal bus in byte units Specified size Mbytes 1 should be set to these bits When...

Page 624: ...l Space Register 1 PCILSR1 See section 13 4 4 1 Accessing Memory Space in This LSI SH R W PCI R W R R R R R W R W R W R W R W R W R W R W R W R R R R R R R R R R R R R R R R R R R SH R W PCI R W 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSR Bit Initial value R W R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBA R...

Page 625: ...to 0 1 Mbyte space is secured initial value B 0 0000 0000 1 Mbyte B 0 0000 0001 2 Mbytes B 0 0000 0011 4 Mbytes B 0 0000 0111 8 Mbytes B 0 0000 1111 16 Mbytes B 0 0001 1111 32 Mbytes B 0 0011 1111 64 Mbytes B 0 0111 1111 128 Mbytes B 0 1111 1111 256 Mbytes B 1 1111 1111 512 Mbytes Other than above Setting prohibited 19 to 1 All 0 SH R PCI R Reserved These bits are always read as 0 The write value ...

Page 626: ...fy bits 31 to 20 for the start address of the local address space 0 internal bus space in this LSI As shown below the valid bits of LAR change depending on the local address space size specified by the LSR bit in PCILSR0 PCILSR0 LSR 28 20 B 0 0000 0000 Bits 31 20 are valid PCILSR0 LSR 28 20 B 0 0000 0001 Bits 31 21 are valid PCILSR0 LSR 28 20 B 0 0000 0011 Bits 31 22 are valid PCILSR0 LSR 28 20 B ...

Page 627: ...ify bits 31 to 20 for the start address of the local address space 1 this LSI internal bus space As shown below the valid bits of LAR change depending on the local address space size specified by the LSR bit in PCILSR1 PCILSR1 LSR 28 20 B 0 0000 0000 Bits 31 20 are valid PCILSR1 LSR 28 20 B 0 0000 0001 Bits 31 21 are valid PCILSR1 LSR 28 20 B 0 0000 0011 Bits 31 22 are valid PCILSR1 LSR 28 20 B 0 ...

Page 628: ... R R R R R R R R R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 15 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 14 TTADI 0 SH R WC PCI R Target Target Abort Interrupt Indicates that the PCIC has terminated a transaction with...

Page 629: ...r Interrupt Indicates that the PCIC attempted to operate as a master PIO or DMA transfer although bit 2 BM in PCICMD is cleared to 0 and operation as a bus master is disabled 0 A master function disable error interrupt was not generated 1 A master function disable error interrupt was generated When TTADI bit is write to 0 target target abort interrupt is cleared When write to 1 it is not available...

Page 630: ... is a target Note A data parity error in target write is detected only when bit 6 PER in PCICMD is set to 1 0 A data parity error interrupt was not generated in target write 1 A data parity error interrupt was generated in target write When TTADI bit is write to 0 target target abort interrupt is cleared When write to 1 it is not available 4 PEDITR 0 SH R WC PCI R PERR Detection Interrupt in Targe...

Page 631: ...hat transaction was terminated by a master abort when the PCIC is a master 0 A master abort interrupt was not generated when the PCIC is a master 1 A master abort interrupt was generated when the PCIC is a master When TTADI bit is write to 0 target target abort interrupt is cleared When write to 1 it is not available 1 MWPDI 0 SH R WC PCI R Master Write PERR Detection Interrupt Indicates that the ...

Page 632: ... PCIC detected a parity error during data read from the target when the PCIC is a master Note A master read data parity error is detected only when bit 6 PER in PCICMD is set to 1 0 A master read data parity error interrupt was not generated 1 A master read data parity error interrupt was generated When TTADI bit is write to 0 target target abort interrupt is cleared When write to 1 it is not avai...

Page 633: ... 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 15 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 14 TTADIM 0 SH R W PCI R Target Target Abort Interrupt Mask 0 TTADI disabled masked 1 TTADI enabled not masked 13 to 10 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should a...

Page 634: ...R PERR Detection Interrupt Mask for Target Read 0 PEDITR disabled masked 1 PEDITR enabled not masked 3 TADIMM 0 SH R W PCI R Target Abort Interrupt Mask for Master 0 TADIM disabled masked 1 TADIM enabled not masked 2 MADIMM 0 SH R W PCI R Master Abort Interrupt Mask for Master 0 MADIM disabled masked 1 MADIM enabled not masked 1 MWPDIM 0 SH R W PCI R Master Write Data Parity Error Interrupt Mask 0...

Page 635: ...rupt is detected SH R W PCI R W SH R W PCI R W 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R x x x x x x x x x AIR x x x x x x x R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R x x x x x x x x x AIR x x x x x x x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W ...

Page 636: ...R R R R R R R R R R R R R R R x x x x 0 0 0 0 0 0 0 0 0 0 0 0 ECL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 MTEM x SH R PCI R Master Error Indicates that an error occurred during a master read or a master write transfer 0 No master error 1 Master error occurred 30 to 27 All 0 SH R PCI R Reserved These bits are always read as 0 The write v...

Page 637: ... 0 0 0 0 0 WD PEI RD PEI MAI TAI MB TOI TB TOI MBI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 14 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 13 MBI 0 SH R WC PCI R Master Broken Interrupt An interrupt is detected when the master that received the bus mastership did not start transaction P...

Page 638: ... A target abort interrupt was not generated 1 A target abort interrupt was generated 2 MAI 0 SH R WC PCI R Master Abort Interrupt Indicates that a transaction was terminated by a master abort when a device other than the PCIC is a bus master 0 A master abort interrupt was not generated 1 A master abort interrupt was generated 1 RDPEI 0 SH R WC PCI R Read Parity Error Interrupt PERR assertion was d...

Page 639: ...IM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 14 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 13 MBIM 0 SH R WC PCI R Master Broken Interrupt Mask 0 MBI disabled masked 1 MBI enabled not masked 12 TBTOIM 0 SH R WC PCI R Target Bus Time Out Interrupt Mask 0 TBTOI disabled masked 1 TBTOI ena...

Page 640: ...ter Information Register PCIBMIR In host mode this register records when the interrupt is generated by PCIAINT When multiple interrupts occur only the first source is registered When an interrupt is disabled the source is registered in the corresponding bit and no interrupt occurs SH R W PCI R W SH R W PCI R W 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value R R R R R R R R R R R ...

Page 641: ... occurred when the device 2 REQ2 is a bus master 0 No device 2 bus master error occurred 1 A device 2 bus master error occurred 2 REQ1BME x SH R PCI R REQ1 Error Indicates that an error occurred when the device 1 REQ1 is a bus master 0 No device 1 bus master error occurred 1 A device 1 bus master error occurred 1 REQ0BME x SH R PCI R REQ0 Error Indicates that an error occurred when the device 0 RE...

Page 642: ...W R W R W R W R W R W R W R W R W R W R W 0 0 x x x x x x x x x x x x x x CRA FN DN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 CCIE 1 SH R PCI Configuration Cycle Issue Enable 0 Indicates that configuration cycle issue is disable 1 30 to 24 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 23 to 16 ...

Page 643: ...ore all bits from 31 to 16 of the AD signals are driven low Device No IDSEL Device No IDSEL H 0 AD 16 High H 8 AD 24 High H 1 AD 17 High H 9 AD 25 High H 2 AD 18 High H A AD 26 High H 3 AD 19 High H B AD 27 High H 4 AD 20 High H C AD 28 High H 5 AD 21 High H D AD 29 High H 6 AD 22 High H E AD 30 High H 7 AD 23 High H F AD 31 High 10 to 8 FN xxx SH R W PCI Function Number These bits specify a funct...

Page 644: ...ways be 0 3 PMD3H 0 SH R WC PCI PCI Power Management D3H D3hot Status Transition Interrupt Indicates that an interrupt to request a transition to the PCI bus power down mode was generated 0 No D3H D3hot status transition interrupt was generated 1 A D3H D3hot status transition interrupt was generated 2 PMD2 0 SH R WC PCI PCI Power Management D2 Status Transition Interrupt Indicates that an interrup...

Page 645: ... SH R W PCI R W 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMD 0M PMD 1M PMD 2M PMD 3HM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 4 All 0 SH R PCI Reserved These bits are always ...

Page 646: ...ad or write to the PCI memory space 0 by the CPU or DMAC See section 13 4 3 2 Accessing PCI Memory Space SH R W PCI R W SH R W PCI R W 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value R R R W R W R R R R R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMSBA0 R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 1...

Page 647: ... R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSBAM0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 24 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 23 to 18 MSBAM0 000000 SH R W PCI PCI Memory Space 0 Bank Address Mask ...

Page 648: ...7 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value R R R W R W R R R R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMSBA1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 18 PMSBA1 All 0 SH R W PCI PCI Memory Space 1 Bank Address 14 bits The...

Page 649: ...0 0 0 0 0 0 0 R R R W R W R W R W R W R W R W R W R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSBAM1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 26 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 25 to 18 MSBAM1 All 0 SH R W PCI PCI Memory Space 1 Bank Address Mask 8 bits 00 0000 00 256 kbytes 0...

Page 650: ...7 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value R R R W R W R R R R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMSBA2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 18 PMSBA2 All 0 SH R W PCI PCI Memory Space 2 Bank Address 14 bits The...

Page 651: ... R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSBAM2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 29 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 28 to 18 MSBAM2 All 0 SH R W PCI PCI Memory Space 2 Bank Address Mask 11 bits 0 0000 0000 00 256 kbytes 0 0000 0000 01 512 kbytes 0 0000 0000 11 1 Mbyte 0 ...

Page 652: ...8 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value R R R W R W R R R R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOSBA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 18 PIOSBA All 0 SH R W PCI PCI I O Space Bank Address 14 bits These bits ...

Page 653: ...it Initial value R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R W R W R W R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOBAM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 21 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 20 to 18 IOBAM All 0 SH R W PCI PCI I O Spac...

Page 654: ...R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 5 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 4 to 2 RANGE All 0 SH R W PCI Address Range to be Compared These bits specify the address range of PCICSAR0 to be compared 000 Compared with PCICSAR...

Page 655: ...are issued 11 PCICSAR0 is compared If the address matches PCICSAR0 in the range snoop commands are issued If not snoop commands are not issued 25 PCI Cache Snoop Control Register 1 PCICSCR1 An external device can access memory of this LSI via the PCIC When an PCI device accesses a cacheable area the PCIC can issue cache snoop commands to the on chip caches This register can specify the function th...

Page 656: ...ytes 101 Compared with PCICSAR1 CADR 31 26 64 Mbytes 110 Compared with PCICSAR1 CADR 31 27 128 Mbytes 111 Compared with PCICSAR1 CADR 31 28 256 Mbytes Valid only when PCICSCR1 SNPMD 10 or 11 1 0 SNPMD All 0 SH R W PCI Snoop Mode for PCICSAR1 These bits specify whether PCICSAR1 is compared with the SuperHyway bus address requested by an external device or not When PCICSAR1 is specified to be compar...

Page 657: ... 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W CADR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W CADR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W ...

Page 658: ... 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W CADR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W CADR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W ...

Page 659: ...9 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value PDR PDR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value x x x x x x x x x x x x x x x x R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W x x x x x x x x x x x x x x x x R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 0 PDR H xxxx xxxx SH R W PCI PCI PIO Da...

Page 660: ...0110 Memory read Yes Yes 0111 Memory write Yes Yes 1000 Reserved 1001 Reserved 1010 Configuration read Yes 1 Yes 1011 Configuration write Yes 1 Yes 1100 Memory read multiple No Partially yes 3 1101 Dual address cycle No No 1110 Memory read line No Partially yes 3 1111 Memory write and invalidate No Partially yes 4 Legend Yes Supported Partially yes Supported with conditions No Not supported Not re...

Page 661: ...d 0 and read or write accesses to each register and the PCI bus is not executed To initialize the PCIC follow the procedures below 1 Set the ENBL bit in PCIECR to 1 2 Initialize the PCI configuration register and PCI local register in the PCIC while the CFINIT bit is cleared to 0 3 Set the CFINT bit in PCICR to 1 On completion of initialization of the registers set the CFINIT bit to 1 Then arbitra...

Page 662: ...y 32 bit address extended mode 1 H C000 0000 to H DFFF FFFF 512 Mbytes PCI memory space 0 H FD00 0000 to H FDFF FFFF H FD00 0000 to H FDFF FFFF 16 Mbytes Control register space H FE00 0000 to H FE03 FFFF H FE00 0000 to H FE03 FFFF 256 Kbytes PCIC internal register H FE04 0000 to H FE07 FFFF H FE04 0000 to H FE07 FFFF 256 Kbytes Reserved H FE08 0000 to H FE1F FFFF H FE08 0000 to H FE1F FFFF 1 5 Mby...

Page 663: ... allocate address space ranging from 16 Mbytes to 512 Mbytes PCI addresses can be allocated to by software Burst transfers are supported for memory transfers Consecutive 32 byte burst accesses from the CPU or DMAC result in a burst transfer of 32 bytes or more 64 bytes 96 bytes etc on the PCI bus The PCI memory spaces are allocated from H FD00 0000 to H FDFF FFFF for PCI memory space 0 16 Mbytes H...

Page 664: ... 31 24 23 18 17 0 31 24 23 18 17 0 31 24 23 18 17 0 Figure 13 3 Access from SuperHyway Bus to PCI Memory PCI Bus PCI Memory Space 0 For PCI memory space 1 accesses the middle eight bits 25 18 are controlled by PCIMBMR1 PCIMBMR1 25 18 B 11 1111 11 PCI address 25 18 SuperHyway bus address 25 18 PCIMBMR1 25 18 B 00 0000 00 PCI address 25 18 PCIMBR1 25 18 The upper six bits 31 26 of a SuperHyway bus a...

Page 665: ...address 28 18 SuperHyway bus address 28 18 PCIMBMR2 28 18 B 0 0000 0000 00 PCI address 28 18 PCIMBR2 28 18 The upper three bits 31 29 of a SuperHyway bus address are replaced with bits 31 to 29 in PCIMBR2 SHwy bus address PCI address PCIMBMR2 PCIMBR2 mask 31 29 28 18 17 0 31 29 28 18 17 0 31 29 28 18 17 0 31 29 28 18 17 0 Figure 13 5 Access from SuperHyway Bus to PCI Memory PCI Bus PCI Memory Spac...

Page 666: ...000 PCI address 20 18 PCIIOBR 20 18 The upper eleven bits 31 21 of a SuperHyway bus address are replaced with bits 31 to 21 in PCIIOBR SHwy bus address PCI address PCIIOBMR PCIIOBR mask 31 21 20 18 17 0 31 21 20 18 17 0 31 21 20 18 17 0 31 21 20 18 17 0 Figure 13 6 Access from SuperHyway Bus to PCI I O Space PCI Bus 4 Accessing Internal Registers of This LSI All internal registers that is PCIECR P...

Page 667: ...endian A B C D A B C A B C D A B A B C PCI_Addr 2 1 PCI_Addr 2 0 31 0 SHwy data PCI bus data 2 Big endian A B C D A B C D A B C PCI_Addr 2 0 PCI_Addr 2 1 Note PCIAddr 2 PCI bus AD 2 D Buffer data Buffer data D C D MSB LSB A B C D A B C D D Figure 13 7 Endian Conversion from SuperHyway Bus to PCI Bus Non Byte Swapping TBS 0 ...

Page 668: ...ndian A B C D A B C A B C D A B C D D A B C D PCI_Addr 2 1 PCI_Addr 2 0 MSB 31 0 LSB SHwy data PCI bus data 2 Big endian D C B A D C B A A B C D A B C D A B C PCI_Addr 2 1 PCI_Addr 2 0 Note PCIAddr 2 PCI bus AD 2 D Buffer data Buffer data Figure 13 8 Endian Conversion from SuperHyway Bus to PCI Local Bus Byte Swapping TBS 1 ...

Page 669: ...B B B C C C C D D D D A B A B B A A B C D C D D C C D C D A B C D D C C D A B A B B A Size Byte Word long word Address 4n 0 4n 1 4n 2 4n 3 4n 0 4n 2 4n 0 SHwy bus PCI bus Big endian CPU Data Data without swapping Data with swapping Little endian CPU Figure 13 9 Data Alignments for SuperHyway Bus and PCI Bus ...

Page 670: ... mode and normal mode 1 Accessing Memory Space in This LSI Accesses to the PCIC in this LSI by an external PCI bus master are described below I O space SHwy bus address space 4GB PCI bus address space 4GB H 00000000 Local address space 0 base 0 Memory base 1 I O base PCI I O space Memory base 0 H FE000000 H FE3FFFFF H FFFFFFFF H 00000000 H FFFFFFFF Local address space 1 base 1 Figure 13 10 Memory ...

Page 671: ...translation from the PCI bus to the SuperHyway bus in this LSI PCIMBAR indicates the start address of the PCI bus memory space used by an external PCI device PCILAR indicates the start address of the local address space for this LSI PCILSR indicates the size of the address space used by an external PCI device For PCIMBAR and PCILAR the upper address bits that are higher than the memory size set in...

Page 672: ... Bus Address Translation 2 Accessing PCIC I O Space The PCI I O address space should be allocated as 256 bytes The lower eight bits 7 0 are sent to the internal bus without translation When bits 31 to 8 of a PCI address match bits 31 to 8 of PCIIBAR the upper 24 bits are replaced with H FE04 01 and a PCI local register is accessed PCI address PCI address SHwy bus address 31 8 7 0 31 8 7 0 31 8 7 0...

Page 673: ...l register space should not be read or written from the PCI bus using a memory read write command 4 Access to SH7785 Memory Space See Section 13 4 4 1 Accessing Memory Space in This LSI Areas 0 to 6 CS0 to CS6 on the SH7785 memory map DDR2 SDRAM space and URAM ILRAM OLRAM in the SH 4A core can be accessed On chip IO Space The on chip I O space should not be read or written from the PCI bus using a...

Page 674: ... byte swapping The endian format is specified by the TBS bit in PCICR 31 MSB LSB 0 PCI bus data SHwy data 1 Little endian A B C D A B C A B C D A B C D A B C PCI_Addr 2 1 PCI_Addr 2 0 31 MSB LSB 0 PCI bus data SHwy data A B C D A B C D A B C D A B C D A B C PCI_Addr 2 0 PCI_Addr 2 1 2 Big endian Note PCIAddr 2 PCI bus AD 2 D D Buffer data Buffer data D Figure 13 13 Endian Conversion from PCI Bus t...

Page 675: ... endian A B C D A B C A B C D A B C A B C D PCI_Addr 2 1 PCI_Addr 2 0 31 MSB LSB 0 PCI bus data SHwy data D C B A D C B A D C B A D C B A A B C PCI_Addr 2 0 PCI_Addr 2 1 2 Big endian Note PCIAddr 2 PCI bus AD 2 D D D Buffer data Buffer data Figure 13 14 Endian Conversion from PCI Bus to SuperHyway Bus Byte Swapping TBS 1 ...

Page 676: ...B B B C C C C D D D D A B A B B A A B C D C D D C C D C D A B C D D C C D A B A B B A Size Byte Word Long word Address 4n 0 4n 1 4n 2 4n 3 4n 0 4n 2 4n 0 PCI bus SHwy bus Big endian CPU Data Data without swapping Data with swapping Little endian CPU Figure 13 15 Data Alignments for SuperHyway Bus and PCI Bus ...

Page 677: ...speed and CPU performance Do not use the prefetch function when using this function Do not set the PFE bit in PCICR to 1 Do not use this function when the CPU is in the sleep state If a cache hit occurs when the CPU is in the sleep state an error occurs on the SuperHyway bus and memory read write is not performed Specify the SNPMD bit snoop mode in PCICSCR to 00 to turn off the snoop function befo...

Page 678: ...rs 0 to 3 Similarly GNT0 GNTIN GNT1 GNT2 and GNT3 function as the GNT outputs to external masters 0 to 3 Arbitration for five masters including the PCIC can be performed 2 Configuration Space Access The PCIC supports configuration mechanism 1 The PCI PIO address register PCIPAR and PCI PIO data register PCIPDR correspond to the configuration address register and configuration data register respect...

Page 679: ...y two devices or more the bus arbiter accepts the request of the highest priority device The PCI bus arbiter supports two modes to determine the device priority 1 fixed priority and 2 pseudo round robin The mode is selected by the BMAM bit in PCICR In the following description the device n indicates a PCI device that uses REQn a Fixed Priority When the BMAM bit in PCICR is cleared to 0 the priorit...

Page 680: ...errupt to the host device on the PCI bus The INTA pin can be set to be asserted or negated by the IOCS bit in PCICR Table 13 6 Interrupt Priority Signal Interrupt Source INTEVT Priority PCISERR SERR assertion detected in host mode H A00 High PCIINTA PCI interrupt A INTA assertion detected in host mode H A20 PCIINTB PCI interrupt B INTB assertion detected in host mode H A40 PCIINTC PCI interrupt C ...

Page 681: ...and the master that starts the next transfer are different high impedance state is generated for one clock cycle or more before the address phase The GNT0 GNTIN pin is used for the GNT input to the PCIC and the REQ0 REQOUT pin is used for the REQ output from the PCIC 13 4 7 Power Management The PCIC has PCI power management configuration registers supporting subsets in version 1 1 The following sh...

Page 682: ... transition from the power state D0 D1 D2 to D3 are supported An interrupt mask can be set for each interrupt The power state D0 interrupt is not generated at a power on reset When the PCIC operates in normal mode and accepts a power down interrupt from an external host device note the following With the PCI power management function the PCI bus clock is stopped 16 clocks or more after the host de...

Page 683: ... a single read cycle in host mode Figure 13 21 shows an example of a burst write cycle in normal mode Figure 13 22 is an example of a burst read cycle in normal mode Note that the response speed of DEVSEL and TRDY differs according to the connected target device In PIO transfer a single read write cycle should be used The configuration transfers can be issued only in host mode PCICLK AD 31 0 PAR C...

Page 684: ...61 0100 PCICLK AD 31 0 PAR C BE 3 0 PCIFRAME IRDY DEVSEL TRDY IDSEL REQ GNT Addr D0 AP DP0 Com BE0 LOCK Legend Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable Figure 13 20 Master Read Cycle in Host Mode Single ...

Page 685: ...AP DP0 Com BE0 D1 DPn 1 DPn BE1 BEn Dn PCICLK AD 31 0 PAR C BE 3 0 PCIFRAME IRDY DEVSEL TRDY IDSEL REQOUT GNTIN Legend Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command LOCK BEn nth data byte enable Figure 13 21 Master Write Cycle in Normal Mode Burst ...

Page 686: ... AP DP0 Com BE0 D1 DPn 1 DPn BE1 BEn Dn PCICLK AD 31 0 PAR C BE 3 0 PCIFRAME IRDY DEVSEL TRDY IDSEL REQOUT GNTIN Legend Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command LOCK BEn nth data byte enable Figure 13 22 Master Read Cycle in Normal Mode Burst ...

Page 687: ...the data contents are guaranteed when data written to the target is target read immediately after it was written Only single transfers are supported for target accesses to the configuration space and I O space If a burst access request is issued the external master is disconnected when the first transfer is complete Note that the DEVSEL response speed is fixed to 2 clocks medium for the target acc...

Page 688: ...E0 Disconnect Configuration space access Lock PCICLK AD 31 0 PAR C BE 3 0 PCIFRAME IRDY DEVSEL TRDY IDSEL REQOUT GNTIN Legend Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command LOCK BEn nth data byte enable STOP Figure 13 23 Target Read Cycle in Normal Mode Single ...

Page 689: ...E0 Disconnect Configuration space access Lock PCICLK AD 31 0 PAR C BE 3 0 PCIFRAME IRDY DEVSEL TRDY IDSEL REQOUT GNTIN Legend Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command LOCK BEn nth data byte enable STOP Figure 13 24 Target Write Cycle in Normal Mode Single ...

Page 690: ... BE0 Disconnect Lock D1 DPn 1 DPn BE1 BEn Dn PCICLK AD 31 0 PAR C BE 3 0 PCIFRAME IRDY DEVSEL TRDY IDSEL REQ GNT Legend Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command LOCK BEn nth data byte enable STOP Figure 13 25 Target Memory Read Cycle in Host Mode Burst ...

Page 691: ... BE0 Disconnect Lock D1 DPn 1 DPn BE1 BEn Dn PCICLK AD 31 0 PAR C BE 3 0 PCIFRAME IRDY DEVSEL TRDY IDSEL REQ GNT Legend Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command LOCK BEn nth data byte enable STOP Figure 13 26 Target Memory Write Cycle in Host Mode Burst ...

Page 692: ... stipulated logic level in one clock It is recommended to use this function when the PCIC issues configuration transfers in host mode Figure 13 27 shows an example of a burst memory write cycle with address stepping Figure 13 28 shows an example of a target burst read cycle with address stepping Addr D0 AP DP0 Com BE0 Dn DPn 1 DPn BEn PCICLK AD 31 0 PAR C BE 3 0 PCIFRAME IRDY DEVSEL TRDY Legend Ad...

Page 693: ...CLK AD 31 0 PAR C BE 3 0 PCIFRAME IRDY DEVSEL TRDY Legend Addr PCI space address Dn nth data AP Address parity DPn nth data parity Com Command BEn nth data byte enable Addr D0 AP DP0 Com BE0 Dn DPn 1 DPn BEn Figure 13 28 Target Memory Read Cycle in Host Bus Bridge Mode Burst with Stepping ...

Page 694: ...13 PCI Controller PCIC Rev 1 00 Jan 10 2008 Page 664 of 1658 REJ09B0261 0100 ...

Page 695: ... longword 4 bytes 16 bytes and 32 bytes Maximum transfer count 16 777 216 Address mode Dual address mode Transfer requests Choice of external request channels 0 to 3 on chip peripheral module request or auto request The following modules can issue an on chip peripheral module request SCIF0 to SCIF5 HAC0 HAC1 HSPI SIOF SSI0 SSI1 FLCTL and MMCIF Bus mode Choice of cycle steal mode normal mode or int...

Page 696: ...3 DACK0 to DACK3 LBSC DDRIF PCIC TCR6 to TCR11 CHCR6 to CHCR11 DMAOR1 SAR6 to SAR11 DAR6 to DAR11 TCRB6 to TCRB9 SARB6 to SARB9 DARB6 to DARB9 DMARS3 to DMARS5 Legend SAR0 to SAR11 DMA source address register SARB0 to SARB3 SARB6 to SARB11 DMA source address register B DAR0 to DAR11 DMA destination address register DARB0 to DARB3 DARB6 to DARB9 DMA destination address register B TCR0 to TCR11 DMA ...

Page 697: ...el 1 DREQ1 acceptance confirmation DRAK1 2 Output Notifies acceptance of DMA transfer request and start of execution from channel 1 to external device DMA transfer end notification DACK1 2 Output Outputs strobe to DMA transfer request from channel 1 to external device 2 DMA transfer request DREQ2 1 Input DMA transfer request input from external device to channel 2 DREQ2 acceptance confirmation DRA...

Page 698: ...ss register 2 DAR2 R W H FC80 8044 H 1C80 8044 32 Bck DMA transfer count register 2 TCR2 R W H FC80 8048 H 1C80 8048 32 Bck DMA channel control register 2 CHCR2 R W 1 H FC80 804C H 1C80 804C 32 Bck Pck 4 3 DMA source address register 3 SAR3 R W H FC80 8050 H 1C80 8050 32 Bck DMA destination address register 3 DAR3 R W H FC80 8054 H 1C80 8054 32 Bck DMA transfer count register 3 TCR3 R W H FC80 805...

Page 699: ...3 DMA extended resource selector 1 DMARS1 R W H FC80 9004 H 1C80 9004 16 Pck 4 5 DMA extended resource selector 2 DMARS2 R W H FC80 9008 H 1C80 9008 16 Pck 6 DMA source address register 6 SAR6 R W H FCC0 8020 H 1CC0 8020 32 Bck DMA destination address register 6 DAR6 R W H FCC0 8024 H 1CC0 8024 32 Bck DMA transfer count register 6 TCR6 R W H FCC0 8028 H 1CC0 8028 32 Bck DMA channel control registe...

Page 700: ...0 8130 32 Bck DMA destination address register B7 DARB7 R W H FCC0 8134 H 1CC0 8134 32 Bck DMA transfer count register B7 TCRB7 R W H FCC0 8138 H 1CC0 8138 32 Bck 8 DMA source address register B8 SARB8 R W H FCC0 8140 H 1CC0 8140 32 Bck DMA destination address register B8 DARB8 R W H FCC0 8144 H 1CC0 8144 32 Bck DMA transfer count register B8 TCRB8 R W H FCC0 8148 H 1CC0 8148 32 Bck 9 DMA source a...

Page 701: ...DAR2 Undefined Undefined Retained Retained Retained DMA transfer count register 2 TCR2 Undefined Undefined Retained Retained Retained DMA channel control register 2 CHCR2 H 4000 0000 H 4000 0000 Retained Retained Retained 3 DMA source address register 3 SAR3 Undefined Undefined Retained Retained Retained DMA destination address register 3 DAR3 Undefined Undefined Retained Retained Retained DMA tra...

Page 702: ... Retained Retained Retained 3 DMA source address register B3 SARB3 Undefined Undefined Retained Retained Retained DMA destination address register B3 DARB3 Undefined Undefined Retained Retained Retained DMA transfer count register B3 TCRB3 Undefined Undefined Retained Retained Retained 0 1 DMA extended resource selector 0 DMARS0 H 0000 H 0000 Retained Retained Retained 2 3 DMA extended resource se...

Page 703: ... 10 DAR10 Undefined Undefined Retained Retained Retained DMA transfer count register 10 TCR10 Undefined Undefined Retained Retained Retained DMA channel control register 10 CHCR10 H 4000 0000 H 4000 0000 Retained Retained Retained 11 DMA source address register 11 SAR11 Undefined Undefined Retained Retained Retained DMA destination address register 11 DAR11 Undefined Undefined Retained Retained Re...

Page 704: ... register B9 SARB9 Undefined Undefined Retained Retained Retained DMA destination address register B9 DARB9 Undefined Undefined Retained Retained Retained DMA transfer count register B9 TCRB9 Undefined Undefined Retained Retained Retained 6 7 DMA extended resource selector 3 DMARS3 H 0000 H 0000 Retained Retained Retained 8 9 DMA extended resource selector 4 DMARS4 H 0000 H 0000 Retained Retained ...

Page 705: ...e transfer is performed respectively In 29 bit address mode the source address is changed as follows before it is output The upper three bits are output as 000 when bits 31 to 29 are not 111 and areas 0 to 6 are used The upper three bits are output as 111 when bits 31 to 29 are not 111 and area 7 is used The written address is output as it is when bits 31 to 29 are 111 In 32 bit address mode the w...

Page 706: ...s that is different from SAR address write data to SAR then to SARB A word or longword boundary address should be specified when a word or longword transfer is performed respectively A 16 byte or 32 byte boundary value should be specified when a 16 byte or 32 byte transfer is performed respectively The initial value of SARB is undefined 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 R W R W R W R...

Page 707: ... 32 byte transfer is performed respectively In 29 bit address mode the source address is changed as follows before it is output The upper three bits are output as 000 when bits 31 to 29 are not 111 and areas 0 to 6 are used The upper three bits are output as 111 when bits 31 to 29 are not 111 and area 7 is used The written address is output as it is when bits 31 to 29 are 111 In 32 bit address mod...

Page 708: ...ddress that is different from DAR address write data to DAR then to DARB A word or longword boundary address should be specified when a word or longword transfer is performed respectively A 16 byte or 32 byte boundary value should be specified when a 16 byte or 32 byte transfer is performed respectively The initial value of DARB is undefined 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 R W R W ...

Page 709: ...is 1 16 777 215 and 16 777 216 the maximum respectively During a DMA transfer these registers indicate the remaining transfer count The upper eight bits in TCR bits 31 to 24 are always read as 0 The write value should always be 0 The initial value of TCR is undefined 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 R W R W R W R W R W R W R W R W R R R R R R R R BIt Initial value R W 0 1 2 3 4 5 6 ...

Page 710: ...nters When the values are 0 values of SAR and DAR are updated and the value of the bits 23 to 16 in TCRB are loaded to the bits 7 to 0 Set the number of transfers until reloading starts to bits 23 to 16 In reload mode a value from H FF 255 times to H 01 1 time can be specified to the bits 23 to 16 and 7 to 0 in TCRB and set the same number to bits 23 to 16 and bits 7 to 0 and set bits 15 to 8 to H...

Page 711: ... 1 0 RS 3 0 DL DS TB TS 1 0 IE TE DE Bit Bit Name Initial Value R W Descriptions 31 0 R Reserved This bit is always read as 0 The write value should always be 0 30 LCKN 1 R W Bus Lock Signal Disable Specifies whether the bus lock signal output is enabled or disabled during a read instruction for the SuperHyway bus This bit is valid in cycle steal mode Clear this bit to 0 in burst mode If the bus l...

Page 712: ... reloaded 111 Reload mode SAR is reloaded 24 0 R Reserved This bit is always read as 0 The write value should always be 0 23 DO 0 R W DMA Overrun Selects whether DREQ is detected by overrun 0 or by overrun 1 This bit is valid in only CHCR0 to CHCR3 0 Detects DREQ by overrun 0 1 Detects DREQ by overrun 1 22 RL 0 R W Request Check Level Selects whether the DRAK signal output is an active high or act...

Page 713: ...TS0 When the transfer source or transfer destination is a register in an on chip peripheral module register that the access size is specified the transfer data size for the register should be the same as the access size For the address set to SAR or DAR as transfer source or transfer destination the transfer data size should be the same as the address boundary TS2 TS1 TS0 000 Byte units 001 Word 2...

Page 714: ...n NMI interrupt or address error or clearing the DE bit bit 0 or the DME bit in DMAOR after the HE bit is set to 1 To clear the HE bit write 0 after reading 1 from the HE bit This bit is valid in only CHCR0 to CHCR3 and CHCR6 to CHCR9 0 DMA transfer is being performed or DMA transfer has been aborted TCR TCR set before transfer 2 Clearing condition Write 0 after HE is read as 1 1 TCR TCR set befor...

Page 715: ...ut in a read cycle DACK is output only when the DMA transfer source is LBSC space 1 DACK output in a write cycle DACK is output only when the DMA transfer destination is LBSC space 16 AL 0 R W Acknowledge Level Specifies whether the DACK signal output is high active or low active This bit is valid in only CHCR0 to CHCR3 If DACK active direction has been changed reflecting the change on the externa...

Page 716: ...or any setting 00 01 or 10 specifying a transfer size greater than the bus width divides bus cycles into two or more and increases the number of addresses for the divided bus cycles 13 12 SM 1 0 00 R W Source Address Mode 1 0 Specify whether the DMA source address is incremented or decremented 00 Source address is fixed 01 Source address is incremented byte unit transfer 1 word unit transfer 2 lon...

Page 717: ... R W DREQ Level and DREQ Edge Select Specify the detecting method of the DREQ input and the detecting level These bits are valid in only CHCR0 to CHCR3 Even in channels 0 to 3 if the transfer request source is specified as an on chip peripheral module or if an auto request is specified these bits are invalid 00 DREQ detected in low level DREQ 01 DREQ detected at falling edge 10 DREQ detected in hi...

Page 718: ... operation register DMAOR To clear the TE bit the TE bit should be read as 1 and then 0 is written to Even if the DE bit is set to 1 while this bit is set to 1 transfer is not enabled 0 When DMA transfer is being performed or DMA transfer has been interrupted Clearing condition Write 0 after TE is read as 1 1 TCR 0 when the final DMA transfer is being performed or the DMA transfer ends 0 DE 0 R W ...

Page 719: ...l value R W Bit Bit Name Initial Value R W Descriptions 15 14 All 0 R Reserved These bits are always read as 0 The write value should always be 0 13 12 CMS 1 0 00 R W Cycle Steal Mode Select 1 0 Select normal mode or intermittent mode in cycle steal mode To validate intermittent mode bus mode in all channels channels 0 to 5 corresponding to DMAOR0 or all channels channels 6 to 11 corresponding to ...

Page 720: ...3 CH4 CH5 DMAOR0 CH6 CH7 CH8 CH9 CH10 CH11 DMAOR1 01 CH0 CH2 CH3 CH1 CH4 CH5 DMAOR0 CH6 CH8 CH9 CH7 CH10 CH11 DMAOR1 10 Setting prohibited 11 Round robin mode for CH0 to CH5 DMAOR0 Round robin mode for CH6 to CH11 DMAOR1 When round robin mode is specified do not mix the cycle steal mode and the burst mode in any channels channels 0 to 5 corresponding to DMAOR0 For any channels corresponding to DMA...

Page 721: ...MAOR0 are set to 1 When the AE bit in DMAOR1 is set DMA transfers for channels 6 to 11 are disabled even if the DE bit in CHCR of the channels channels 6 to 11 corresponding to DMAOR1 and the DME bit in DMAOR1 are set to 1 0 No DMAC address error Clearing condition Write 0 to the AE bit after the bit is read as 1 1 DMAC address error occurs 1 NMIF 0 R W NMI Flag Indicates that an NMI interrupt occ...

Page 722: ... in DMAOR corresponding to channels should be 0 If the DME bit is cleared to 0 transfers in all channels channels 0 to 5 corresponding to DMAOR0 and all channels channels 6 to 11 corresponding to DMAOR1 are aborted In an on chip peripheral module request when aborting the transfer by clearing the DME bit clear the DME bit while all on chip peripheral module transfer requests corresponding channels...

Page 723: ...lect bits RS3 to RS0 have been set to B 1000 for CHCR When the bits are not set to B 1000 transfer request source is not accepted even if DMARS has been specified DMARS0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Ch1MID Ch1RID Ch0MID Ch0RID DMARS1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0...

Page 724: ...Ch11MID Ch11RID Ch10MID Ch10RID DMARS0 Bit Bit Name Initial Value R W Descriptions 15 14 13 12 11 10 C1MID5 C1MID4 C1MID3 C1MID2 C1MID1 C1MID0 0 0 0 0 0 0 R W R W R W R W R W R W Transfer request source module ID5 to ID0 for DMA channel 1 MID See table 14 3 9 8 C1RID1 C1RID0 0 0 R W R W Transfer request source register ID1 and ID0 for DMA channel 1 RID See table 14 3 7 6 5 4 3 2 C0MID5 C0MID4 C0MI...

Page 725: ...st source module ID5 to ID0 for DMA channel 3 MID See table 14 3 9 8 C3RID1 C3RID0 0 0 R W R W Transfer request source register ID1 and ID0 for DMA channel 3 RID See table 14 3 7 6 5 4 3 2 C2MID5 C2MID4 C2MID3 C2MID2 C2MID1 C2MID0 0 0 0 0 0 0 R W R W R W R W R W R W Transfer request source module ID5 to ID0 for DMA channel 2 MID See table 14 3 1 0 C2RID1 C2RID0 0 0 R W R W Transfer request source ...

Page 726: ...st source module ID5 to ID0 for DMA channel 5 MID See table 14 3 9 8 C5RID1 C5RID0 0 0 R W R W Transfer request source register ID1 and ID0 for DMA channel 5 RID See table 14 3 7 6 5 4 3 2 C4MID5 C4MID4 C4MID3 C4MID2 C4MID1 C4MID0 0 0 0 0 0 0 R W R W R W R W R W R W Transfer request source module ID5 to ID0 for DMA channel 4 MID See table 14 3 1 0 C4RID1 C4RID0 0 0 R W R W Transfer request source ...

Page 727: ...st source module ID5 to ID0 for DMA channel 7 MID See table 14 3 9 8 C7RID1 C7RID0 0 0 R W R W Transfer request source register ID1 and ID0 for DMA channel 7 RID See table 14 3 7 6 5 4 3 2 C6MID5 C6MID4 C6MID3 C6MID2 C6MID1 C6MID0 0 0 0 0 0 0 R W R W R W R W R W R W Transfer request source module ID5 to ID0 for DMA channel 6 MID See table 14 3 1 0 C6RID1 C6RID0 0 0 R W R W Transfer request source ...

Page 728: ...st source module ID5 to ID0 for DMA channel 9 MID See table 14 3 9 8 C9RID1 C9RID0 0 0 R W R W Transfer request source register ID1 and ID0 for DMA channel 9 RID See table 14 3 7 6 5 4 3 2 C8MID5 C8MID4 C8MID3 C8MID2 C8MID1 C8MID0 0 0 0 0 0 0 R W R W R W R W R W R W Transfer request source module ID5 to ID0 for DMA channel 8 MID See table 14 3 1 0 C8RID1 C8RID0 0 0 R W R W Transfer request source ...

Page 729: ...ource module ID5 to ID0 for DMA channel 11 MID See table 14 3 9 8 C11RID1 C11RID0 0 0 R W R W Transfer request source register ID1 and ID0 for DMA channel 11 RID See table 14 3 7 6 5 4 3 2 C10MID5 C10MID4 C10MID3 C10MID2 C10MID1 C10MID0 0 0 0 0 0 0 R W R W R W R W R W R W Transfer request source module ID5 to ID0 for DMA channel 10 MID See table 14 3 1 0 C10RID1 C10RID0 0 0 R W R W Transfer reques...

Page 730: ...it H 26 B 10 Receive SCIF2 H 29 B 001010 B 01 Transmit H 2A B 10 Receive SCIF3 H 2D B 001011 B 01 Transmit H 2E B 10 Receive SCIF4 H 31 B 001100 B 01 Transmit H 32 B 10 Receive SCIF5 H 35 B 001101 B 01 Transmit H 36 B 10 Receive HAC0 H 41 B 010000 B 01 Transmit H 42 B 10 Receive HAC1 H 45 B 010001 B 01 Transmit H 46 B 10 Receive SIOF H 51 B 010100 B 01 Transmit H 52 B 10 Receive FLCTL H 83 B 10000...

Page 731: ... to DMARS5 according to DMA channels 1 Auto Request Mode Auto request mode is a mode that automatically generates transfer request signal in the DMAC when there is no transfer request signal from an external source like memory to memory transfer or a transfer between memory and an on chip peripheral module that cannot generate transfer request When the DE bit in CHCR the DME bit in DMAOR0 for chan...

Page 732: ...cannot accept requests After acknowledge DACK is output to the accepted DREQ the DREQ pin can accept requests again When DREQ is used for level detection the timing to detect the next DREQ after outputting DACK depends on the DO bit in CHCR For details see section 14 4 7 DREQ Pin Sampling Timing Table 14 6 Selecting External Request Detection with the DO Bit CHCR DO External Request 0 Overrun 0 in...

Page 733: ...to DMARS5 and a transfer request from the FLCTL If the DMA transfer is enabled DE 1 DME 1 TE 0 AE 0 NMIF 0 in this mode a transfer is performed by transfer request signal When a transmit data empty transfer request of the SCIF0 is specified as the transfer request the transfer destination must be the SCIF0 s transmit data register Likewise when receive data full transfer request of the SCIF0 is sp...

Page 734: ...1 receiver Unread data is present In receive mode the DMRQ bit in the SSISR1 register is 1 SSIRDR1 Any Cycle steal 001000 01 SCIF0 transmitter TXI transmit FIFO data empty Any SCFTDR0 Cycle steal 10 SCIF0 receiver RXI receive FIFO data full SCFRDR0 Any Cycle steal 001001 01 SCIF1 transmitter TXI transmit FIFO data empty Any SCFTDR1 Cycle steal 10 SCIF1 receiver RXI receive FIFO data full SCFRDR1 A...

Page 735: ...ad receive data is present HACPCML1 HACPCMR1 Any Cycle steal 010100 01 SIOF transmitter Transmit FIFO data empty request Any SITDR Cycle steal 10 SIOF receiver Receive FIFO data full request SIRDR Any Cycle steal 100000 11 FLCTL data part transmitter Transmit FIFO data empty request Any FLDTFIFO Cycle steal FLCTL data part receiver Receive FIFO data full request FLDTFIFO Any Cycle steal 100001 11 ...

Page 736: ...lows Channels 0 to 5 CH0 CH1 CH2 CH3 CH4 CH5 CH0 CH2 CH3 CH1 CH4 CH5 Channels 6 to 11 CH6 CH7 CH8 CH9 CH10 CH11 CH6 CH8 CH9 CH7 CH10 CH11 These are selected by bits PR1 and PR0 in DMAOR0 and DMAOR1 2 Round Robin Mode In round robin mode each time data of one transfer unit byte word longword 16 byte or 32 byte unit is transferred on one channel the channel on which the transfer has just ended is th...

Page 737: ...e priority of channels 0 and 1 which were higher than channel 2 are also shifted If immediately after there is a request to transfer channel 5 only channel 5 becomes bottom priority and the priority of channels 3 and 4 which were higher than channel 5 are also shifted Channel 1 becomes bottom priority The priority of channel 0 which was higher than channel 1 is also shifted Channel 0 becomes botto...

Page 738: ...lowest priority 5 As channel 1 has a higher priority than channel 3 at this point the channel 1 transfer starts channel 3 is waiting for transfer 6 When the channel 1 transfer ends channel 1 has the lowest priority 7 The channel 3 transfer starts 8 When the channel 3 transfer ends channels 3 and 2 have lower priority so that channel 3 has the lowest priority Transfer request Waiting channel s DMAC...

Page 739: ... and burst mode Table 14 9 DMA Transfer Directions for Auto Request and External Request 2 Transfer Destination Transfer Source LBSC Space DBSC Space PCIC Space On Chip Peripheral Module 1 L or U Memory LBSC Space Y Y Y Y Y DBSC Space Y Y Y Y Y PCIC Space Y Y Y Y Y On Chip Peripheral Module 1 Y Y Y Y Y L or U Memory Y Y Y Y Y Legend Y Transfer is enabled Notes 1 This is the access size that is per...

Page 740: ...or U Memory LBSC Space N N N Y N DBSC Space N N N Y N PCIC Space N N N Y N On Chip Peripheral Module 1 Y Y Y Y Y L or U Memory N N N Y N Legend Y Transfer is enabled N Transfer is disabled Notes 1 This is the access size that is permitted by a register when the transfer source or destination is an on chip peripheral module 2 The transfer source or destination must be the request source register fo...

Page 741: ... shown in figure 14 4 data is read from an external memory to the DMAC in a data read cycle and then the data is written to the other external memory in a write cycle Figure 14 5 shows the DMA transfer timing in dual address mode Data buffer Address bus Data bus Address bus Data bus Memory Transfer source module Transfer destination module Memory Transfer source module Transfer destination module ...

Page 742: ...Jan 10 2008 Page 712 of 1658 REJ09B0261 0100 Transfer source address Transfer destination address CLKOUT A25 to A0 CSn RD WEn D31 to D0 DACKn Active low Figure 14 5 Example of DMA Transfer Timing in Dual Address Mode Source SRAM Destination DDR SDRAM ...

Page 743: ...tions are satisfied Cycle steal normal mode 1 can be set for only channels 0 to 5 Figure 14 6 shows an example of DMA transfer timing in cycle steal normal mode 1 DREQ SuperHyway bus cycle Bus mastership returned to CPU once Read Write Read Write CPU CPU CPU DMAC DMAC CPU DMAC DMAC CPU Figure 14 6 DMA Transfer Timing Example in Cycle Steal Normal Mode 1 DREQ Low Level Detection Normal mode 2 CHCR ...

Page 744: ...ent modes must be cycle steal mode in all channels channels 0 to 5 corresponding to DMAOR0 or all channels channels 6 to11 corresponding to DMAOR1 Figure 14 8 shows an example of DMA transfer timing in cycle steal intermittent mode DREQ SuperHyway bus cycle Read Write Read Write CPU CPU CPU DMAC DMAC CPU CPU DMAC DMAC CPU More than 16 or 64 Bck depends on DMAOR CMS settings Figure 14 8 Example e o...

Page 745: ...n cycle steal mode channel 0 with a higher priority performs the transfer of one transfer unit and the channel 1 transfer is continuously performed without releasing the bus mastership The bus mastership then switches between the two in the order channel 0 channel 1 channel 0 and channel 1 Figure 14 10 d In other words the bus status looks as if the CPU cycle reached after the transfer in cycle st...

Page 746: ...r source CH0 transfer source CPU DMA CH1 DMA CH1 DMA CH1 DMA CH0 DMA CH1 DMA CH0 DMA CH1 DMA CH1 Burst mode CPU DMA CH0 and CH1 Burst mode DMA CH0 Burst mode CH1 transfer source CH0 transfer source CPU DMA CH1 DMA CH0 DMA CH0 DMA CH0 DMA CH DMA CH0 DMA CH1 DMA CH1 Cycle steal CPU DMA CH0 Burst mode CH1 transfer source CH0 transfer source CPU DMA CH1 DMA CH0 DMA CH0 DMA CH0 DMA CH0 DMA CH0 DMA CH1 ...

Page 747: ...ettings of TS0 TS1 and TS2 In auto request mode the transfer starts automatically when the DE and DME bits are set to 1 The TCR is decremented for each transfer The actual transfer flows depend on address mode and bus mode 3 When the specified number of transfers has been completed when TCR is 0 the transfer ends successfully If the IE bit in CHCR is set to 1 at this time a DMINT interrupt is sent...

Page 748: ...ffers according to the operating conditions in each mode 6 TCRBH and TCRBL refer to TCRB23 to TCRB16 and TCRB7 to TCRB0 respectively NMIF 1 or AE 1 or DE 0 or DME 0 Normal end Transfer end NMIF 1 or AE 1 or DE 0 or DME 0 SARB DARB load TCRB TCR load HIE 0 or HE 1 Yes Yes No No 5 No Yes TCR 0 TE 1 DMINT interrupt request IE 1 Repeat mode TCR TCRB 2 HE 1 DMINT interrupt request HIE 1 Yes Yes Yes No ...

Page 749: ...and 12 B 00 SAR fixed IE bit 2 B 1 Interrupt enabled DE bit 0 B 1 DMA transfer enabled Set bits such as bits TB and TS according to use conditions Set bits CMS and PR in DMAOR according to use conditions and set the DME bit to 1 2 Voice data is received and transferred by SIOF DMAC 3 TCR is decreased to half of the initial value and an interrupt is generated After reading CHCR and confirming that ...

Page 750: ...ery four transfers Set CHCR as follows RPT bits 27 to 25 B 111 Reload mode Reloading SAR DM bits 15 to 14 B 01 An increase in DAR SM bits 13 to 12 B 01 An increase in SAR TS bit 20 and bits 4 to 3 B 010 Transfer for each four byte longword DMA transfer source addresses and DMA transfer destination addresses in the above register settings Cycle 1 Source address SAR Destination address DAR Cycle 2 S...

Page 751: ...d when word transfer is performed in 8 bit bus width longword transfer is performed in 8 or 16 bit bus width or 16 or 32 byte transfer is performed in 8 16 32 or 64 bit bus width These figures suppose that DACK of DMA1 transfer is connected When word transfer is performed in 8 bit bus width longword transfer is performed in 8 or 16 bit bus width or 16 or 32 byte transfer is performed in 8 16 32 or...

Page 752: ...Word Transfer in 8 Bit Bus Width Longword Transfer in 8 16 Bit Bus Width 16 32 Byte Transfer in 8 16 32 64 Bit Bus Width DACK of DMA1 Transfer Divided Non sensitive period CLKOUT Bus cycle Address DREQ Rising edge DRAK High active DACK High active Acceptance started Accepted after one cycle of CLKOUT at the rising edge of DACK 1st acceptance 2nd acceptance CPU CPU DMAC Figure 14 15 Example 3 of DR...

Page 753: ...st acceptance Acceptance started Accepted after one cycle of CLKOUT at the falling edge of DACK Non sensitive period 1st acceptance Acceptance started Accepted after one cycle of CLKOUT at the rising edge of DACK CPU DMAC CPU 2nd acceptance 2nd acceptance Figure 14 16 Example 1 of DREQ Input Detection in Cycle Steal Mode Level Detection Byte Transfer in 8 16 32 64 Bit Bus Width Word Transfer in 16...

Page 754: ...of CLKOUT at the first falling edge of the divided up DACK 1st acceptance 2nd acceptance CPU CPU DMAC Non sensitive period CLKOUT Acceptance started Accepted after one cycle of CLKOUT at the first rising edge of the divided up DACK 1st acceptance 2nd acceptance CPU CPU DMAC Figure 14 17 Example 2 of DREQ Input Detection in Cycle Steal Mode Level Detection Word Transfer in 8 Bit Bus Width Longword ...

Page 755: ...el DRAK High active DACK High active Bus cycle DREQ Overrun 1 High level DRAK High active DACK High active CLKOUT Address CPU CPU DMAC CLKOUT Address CPU CPU DMAC Figure 14 18 Example 3 of DREQ Input Detection in Cycle Steal Mode Level Detection Word Transfer in 8 Bit Bus Width Longword Transfer in 8 16 Bit Bus Width or 16 32 Byte Transfer in 8 16 32 64 Bit Bus Width DACK of DMA1 Transfer Is Conne...

Page 756: ...er one cycle of CLKOUT at the falling edge of DACK 1st acceptance 2nd acceptance Non sensitive period Acceptance started Accepted after one cycle of CLKOUT at the rising edge of DACK 1st acceptance 2nd acceptance CLKOUT DREQ CLKOUT DREQ CPU DMAC CPU DMAC Figure 14 20 Example 1 of DREQ Input Detection in Burst Mode Level Detection Byte Transfer in 8 16 32 64 Bit Bus Width Word Transfer in 16 32 64 ...

Page 757: ...le of CLKOUT at the first rising edge of the divided up DACK 1st acceptance 2nd acceptance Bus cycle DREQ Overrun 0 High level DRAK High active DACK High active Bus cycle DREQ Overrun 1 High level DRAK High active DACK High active CLKOUT CPU DMAC CLKOUT CPU DMAC Figure 14 21 Example 2 of DREQ Input Detection in Burst Mode Level Detection Word Transfer in 8 Bit Bus Width Longword Transfer in 8 16 B...

Page 758: ...cle of CLKOUT at the rising edge of DACK 1st acceptance 2nd acceptance Bus cycle DREQ Overrun 0 High level DRAK High active DACK High active Bus cycle DREQ Overrun 1 High level DRAK High active DACK High active Address Address CLKOUT CPU DMAC CLKOUT CPU DMAC Figure 14 22 Example 3 of DREQ Input Detection in Burst Mode Level Detection Word Transfer in 8 Bit Bus Width Longword Transfer in 8 16 Bit B...

Page 759: ...DMINT0 Channel 0 DMA transfer end half end interrupt DMINT1 Channel 1 DMA transfer end half end interrupt DMINT2 Channel 2 DMA transfer end half end interrupt DMINT3 Channel 3 DMA transfer end half end interrupt DMINT4 Channel 4 DMA transfer end half end interrupt DMINT5 Channel 5 DMA transfer end half end interrupt DMAE0 DMA address error interrupt common to channels 0 to 5 DMINT6 Channel 6 DMA t...

Page 760: ...d then start a transfer Note Set registers of channels 0 to 5 again when the AE bit of DMAOR0 is set to 1 and set registers of channels 6 to 11 again when the AE bit of DMAOR1 is set to 1 14 6 3 NMI Interrupt When a NMI interrupt is occurred DMA transfer is stopped Set registers of all channels again after returning from the exception handling routine of a NMI and then start a transfer 14 6 4 Burs...

Page 761: ...e or burst mode or external request DREQ edge detection cycle steal mode or burst mode is set Prevent DACK of two or more DMA transfer units from connecting by setting the IWRRD bits in CSnBCR to B 001 to B 111 insert a minimum of one idle cycle in read read cycles in different space and the IWRRS bits to B 001 to B 111 insert a minimum of one idle cycle in read read cycles in the same space 2 DMA...

Page 762: ...14 Direct Memory Access Controller DMAC Rev 1 00 Jan 10 2008 Page 732 of 1658 REJ09B0261 0100 ...

Page 763: ...raphic data translation accelerator the DU clock DUck used in the display unit the peripheral clock Pck used in the interface with on chip peripheral modules and the RAM clock Uck used in URAM Generates SH7785 external clocks Generates the bus clock Bck used in the interface with the external devices and the DDR clock DDRck for the memory clock used in the DBSC2 Clock operating modes Selects a cry...

Page 764: ... circuit 2 1 CLKOUT CLKOUTENB Divider 2 1 2 1 4 1 6 1 8 1 12 1 16 1 18 1 24 1 32 1 36 1 48 Bus clock Bck CPU clock Ick SHwy clock SHck GA clock GAck DU clock DUck Peripheral clock Pck DDR clock DDRck RAM clock Uck XTAL EXTAL MODE 10 MODE 4 MODE 3 MODE 2 MODE 1 MODE 0 Legend FRQCR0 Frequency control register 0 FRQCR1 Frequency control register 1 MSTPCR1 Module standby control register 1 Note For de...

Page 765: ...sed when a crystal resonator is connected to the XTAL and EXTAL pins The crystal oscillator circuit can be used by the MODE10 pin setting For details on input frequency see section 32 Electrical Characteristics Divider 1 Divider 1 divides the input clock frequency from the crystal oscillator circuit or the EXTAL pin The division ratio is set by mode pins MODE3 and MODE4 Divider 2 Divider 2 generat...

Page 766: ...t from the EXTAL pin When MODE10 is set to the high level the crystal resonator is connected directly to the EXTAL and XTAL pins MODE10 is multiplexed with the SCIF4_RXD SCIF channel 4 FD2 FLCTL and PN1 GPIO pins XTAL Output Connected to a crystal resonator EXTAL Input Used to input an external clock or connected to a crystal resonator CLKOUT 2 Clock Pins Output Used to output a local bus clock CL...

Page 767: ...of the Oscillator and PLLs Setting of Mode Control Pins 1 2 Clock Operating Mode MODE4 MODE3 MODE2 MODE1 MODE0 Divider 1 PLL1 PLL2 0 L L L L L 1 On 72 On 1 L L L L H 1 On 72 On 2 L L L H L 1 On 72 On 3 L L L H H 1 On 72 On 16 H L L L L 1 On 36 On 17 H L L L H 1 On 36 On 18 H L L H L 1 On 36 On 19 H L L H H 1 On 36 On Notes 1 For the MODE0 to MODE4 pins setting except the above mode pins MODE0 to M...

Page 768: ... 2 9 2 3 2 9 3 17 H 122B 244B 18 9 9 9 2 9 2 3 4 9 3 4 18 H 1335 3558 18 6 6 3 3 3 2 6 3 19 H 133B 355B 18 6 6 3 3 3 4 6 3 4 Table 15 4 Clock Operating Modes and Frequency Multiplication Ratio for Each Clock MODE12 or MODE11 Is Set to Low Level Frequency Multiplication Ratio for Input Clock Clock Operating Mode FRQMR1 Initial Value CPU Clock Ick RAM Clock Uck SuperHyway Clock SHck GDTA Clock GAck ...

Page 769: ...H 1FC8 0000 32 Pck Frequency control register 1 FRQCR1 R W H FFC8 0004 H 1FC8 0004 32 Pck Frequency display register 1 FRQMR1 R H FFC8 0014 H 1FC8 0014 32 Pck Sleep control register SLPCR R W H FFC8 0020 H 1FC8 0020 32 Pck PLL control register PLLCR R W H FFC8 0024 H 1FC8 0024 32 Pck Standby control register 0 MSTPCR0 R W H FFC8 0030 H 1FC8 0030 32 Pck Standby control register 1 MSTPCR1 R W H FFC8...

Page 770: ... control register SLPCR H 0000 0000 Retained Retained PLL control register PLLCR H 0000 0000 Retained Retained Standby control register 0 1 MSTPCR0 H 0000 0000 Retained Retained Standby control register 1 1 MSTPCR1 H 0000 0000 Retained Retained Standby display register 1 MSTPMR H 00x0 0000 3 Retained Retained Notes 1 For details on the standby control registers see section 17 Power Down Mode 2 The...

Page 771: ...W R W R W R W R W R W R W BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRQE R W R R R R R R R R R R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 24 All 0 R W Code value H CF These bits are always read as 0 The write value should always be H CF 23 to 1 All 0 R Reserved These bits are always read as 0 The write value ...

Page 772: ...k to the value set in FRQCR1 you must set 1 in the FRQE bit in FRQCR0 to execute the sequence that changes the frequency After the sequence is executed this register is automatically cleared to H 0000 0000 However when changing the division ratio of the DDR clock DDRck switch SDRAM to the self refreshing state For details on how to switch to or release the self refreshing state see section 12 DDR2...

Page 773: ...00 No change 0010 1 4 0011 1 6 Others Setting prohibited 23 22 21 20 SFC3 SFC2 SFC1 SFC0 0 0 0 0 R W R W R W R W Frequency division ratio of the SuperHyway clock SHck 0000 No change 0010 1 4 0011 1 6 Others Setting prohibited 19 18 17 16 BFC3 BFC2 BFC1 BFC0 0 0 0 0 R W R W R W R W Frequency division ratio of the bus clock Bck 0000 No change 0101 1 12 0110 1 16 0111 1 18 1000 1 24 1001 1 32 1010 1 ...

Page 774: ...8 0101 1 12 Others Setting prohibited 7 6 5 4 S3FC3 S3FC2 S3FC1 S3FC0 0 0 0 0 R W R W R W R W Frequency division ratio of the DU clock DUck 0000 No change 0100 1 8 0101 1 12 0110 1 16 0111 1 18 1000 1 24 1001 1 32 1010 1 36 1011 1 48 Others Setting prohibited 3 2 1 0 PFC3 PFC2 PFC1 PFC0 0 0 0 0 R W R W R W R W Frequency division ratio of the peripheral clock Pck 0000 No change 0111 1 18 1000 1 24 ...

Page 775: ...FST2 R R R R R R R R R R R R R R R R BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 x x 0 1 x x 1 x x 0 1 0 x 1 0 0 PFST0 PFST1 PFST2 PFST3 S3FST0 S3FST1 S3FST2 S3FST3 S2FST0 S2FST1 S2FST2 S2FST3 MFST0 MFST1 MFST3 MFST2 R R R R R R R R R R R R R R R R BIt Initial value R W Note The initial value x a bit whose value is undefined depends on the settings of mode pins MODE0 to MODE4 MODE1...

Page 776: ...division ratio of the DDR clock DDRck 0010 1 4 0011 1 6 11 10 9 8 S2FST3 S2FST2 S2FST1 S2FST0 0 1 0 x R R R R Frequency division ratio of the GDTA clock GAck 0100 1 8 0101 1 12 1111 Stop the clock supply 7 6 5 4 S3FST3 S3FST3 S3FST3 S3FST3 x 1 x x R R R R Frequency division ratio of the DU clock DUck 0100 1 8 0101 1 12 0110 1 16 0111 1 18 1000 1 24 1001 1 32 1010 1 36 1011 1 48 1111 Stop the clock...

Page 777: ... R R W R R R R R R R R R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 24 0 R Reserved These bits are always read as 0 The write value should always be 0 23 to 16 All 0 R W Reserved These bits are always read as 0 The write value should always be 0 If a value other than 0 is written the operation is not guaranteed 15 to 2 All 0 R Reserved These bits are always re...

Page 778: ...frequency control register FRQCR1 and frequency display register FRQMR1 and the EXTAL input Table 15 7 Relationship Between the Division Ratio of Divider 2 and the Frequency Frequency for an input clock Division ratio of divider 2 Clock operating mode 0 to 3 Clock operating mode 16 to 19 1 2 36 18 1 4 18 9 1 6 12 6 1 8 9 9 2 1 12 6 3 1 16 9 2 9 4 1 18 4 2 1 24 3 3 2 1 32 9 4 9 8 1 36 2 1 1 48 3 2 ...

Page 779: ...ernal clock has been changed to the clock with the specified division ratio Note When setting a value except H 0 in the MFC3 to MFC0 bits in FRQCR1 to change the DDR clock frequency switch SDRAM to the self refreshing state before executing step 2 above For details on how to switch to or release the self refreshing state see section 12 DDR2 SDRAM Interface DBSC2 15 6 2 Changing the Bus Clock Frequ...

Page 780: ...eration 8 When H 00000000 is read from FRQCR0 the sequence that changes the frequency has finished The internal clock has been changed to the clock with the specified division ratio Note When setting a value except H 0 in the MFC3 to MFC0 bits in FRQCR1 to change the DDR clock frequency switch SDRAM to the self refreshing state before executing step 2 above For details on how to switch to or relea...

Page 781: ... 1 48 1 4 1 12 H 1226 244A 1 2 1 4 1 4 1 8 1 8 1 36 1 4 1 16 H 1226 246A 1 2 1 4 1 4 1 8 1 16 1 36 1 4 1 16 H 1226 24AA 1 2 1 4 1 4 1 8 1 36 1 36 1 4 1 16 H 1226 244B 1 2 1 4 1 4 1 8 1 8 1 48 1 4 1 16 H 1226 245B 1 2 1 4 1 4 1 8 1 12 1 48 1 4 1 16 H 1226 246B 1 2 1 4 1 4 1 8 1 16 1 48 1 4 1 16 H 1226 248B 1 2 1 4 1 4 1 8 1 24 1 48 1 4 1 16 H 1226 24BB 1 2 1 4 1 4 1 8 1 48 1 48 1 4 1 16 H 1228 2448...

Page 782: ...GDTA clock GAck DU clock DUck Peripheral clock Pck DDR clock DDRck Bus clock Bck H 2225 2448 1 4 1 4 1 4 1 8 1 8 1 24 1 4 1 12 H 2225 2458 1 4 1 4 1 4 1 8 1 12 1 24 1 4 1 12 H 2225 2488 1 4 1 4 1 4 1 8 1 24 1 24 1 4 1 12 H 2225 244B 1 4 1 4 1 4 1 8 1 8 1 48 1 4 1 12 H 2225 245B 1 4 1 4 1 4 1 8 1 12 1 48 1 4 1 12 H 2225 246B 1 4 1 4 1 4 1 8 1 16 1 48 1 4 1 12 H 2225 248B 1 4 1 4 1 4 1 8 1 24 1 48 1...

Page 783: ...8 1 8 1 48 1 4 1 24 H 2228 245B 1 4 1 4 1 4 1 8 1 12 1 48 1 4 1 24 H 2228 246B 1 4 1 4 1 4 1 8 1 16 1 48 1 4 1 24 H 2228 248B 1 4 1 4 1 4 1 8 1 24 1 48 1 4 1 24 H 2228 24BB 1 4 1 4 1 4 1 8 1 48 1 48 1 4 1 24 H 222A 244A 1 4 1 4 1 4 1 8 1 8 1 36 1 4 1 36 H 222A 246A 1 4 1 4 1 4 1 8 1 16 1 36 1 4 1 36 H 222A 24AA 1 4 1 4 1 4 1 8 1 36 1 36 1 4 1 36 H 222B 244B 1 4 1 4 1 4 1 8 1 8 1 48 1 4 1 48 H 222B...

Page 784: ... 1 6 1 6 1 12 1 12 1 48 1 6 1 12 H 1335 358B 1 2 1 6 1 6 1 12 1 24 1 48 1 6 1 12 H 1335 35BB 1 2 1 6 1 6 1 12 1 48 1 48 1 6 1 12 H 1337 355A 1 2 1 6 1 6 1 12 1 12 1 36 1 6 1 18 H 1337 357A 1 2 1 6 1 6 1 12 1 18 1 36 1 6 1 18 H 1337 35AA 1 2 1 6 1 6 1 12 1 36 1 36 1 6 1 18 H 1338 3558 1 2 1 6 1 6 1 12 1 12 1 24 1 6 1 24 H 1338 3588 1 2 1 6 1 6 1 12 1 24 1 24 1 6 1 24 H 1338 355B 1 2 1 6 1 6 1 12 1 ...

Page 785: ... 1 6 1 6 1 12 1 12 1 48 1 6 1 12 H 3335 358B 1 6 1 6 1 6 1 12 1 24 1 48 1 6 1 12 H 3335 35BB 1 6 1 6 1 6 1 12 1 48 1 48 1 6 1 12 H 3337 355A 1 6 1 6 1 6 1 12 1 12 1 36 1 6 1 18 H 3337 357A 1 6 1 6 1 6 1 12 1 18 1 36 1 6 1 18 H 3337 35AA 1 6 1 6 1 6 1 12 1 36 1 36 1 6 1 18 H 3338 3558 1 6 1 6 1 6 1 12 1 12 1 24 1 6 1 24 H 3338 3588 1 6 1 6 1 6 1 12 1 24 1 24 1 6 1 24 H 3338 355B 1 6 1 6 1 6 1 12 1 ...

Page 786: ...s prohibited Recommended values CL1 CL2 0 to 33 pF R 0 Ω Note The values of CL1 CL2 and the dumping resistance should be determined through evaluation and consultation with the manufacturer of the crystal resonator to be used Figure 15 4 Note on Using a Crystal Resonator 2 Note on Inputting the External Clock from the EXTAL Pin Do not connect anything to the XTAL pin 3 Note on Using a PLL Oscillat...

Page 787: ...CB4 CPB4 CB5 RCB5 CPB5 Power supply 1 Power supply 2 SH7785 VDD PLL1 VSS PLL1 VDDA PLL1 VSSA PLL1 VDDQ PLL1 VSSQ PLL1 VDD PLL2 VSS PLL2 VDDQ PLL2 VSSQ PLL2 Recommended values RCB1 RCB2 RCB3 RCB4 RCB5 10 Ω CPB1 CPB2 CPB3 CPB4 CPB5 10 μF Tantalum capacitor CB1 CB2 CB3 CB4 CB5 0 1 μF Figure 15 5 Note on Using a PLL Oscillator Circuit ...

Page 788: ...15 Clock Pulse Generator CPG Rev 1 00 Jan 10 2008 Page 758 of 1658 REJ09B0261 0100 ...

Page 789: ...e watchdog timer unit monitors for system runaway using a timer counting at regular time intervals Two operating modes In watchdog timer mode internal reset of the chip is initiated on counter overflow and on chip modules are reset In interval timer mode an interrupt is generated on counter overflow Selectable between power on reset and manual reset When manual reset is selected a manual reset sig...

Page 790: ...est 2 WDTCNT WDTCSR WDTST Count up signal Comparator Reset control circuit CPG Interrupt request Interrupt control circuit INTC Peripheral clock Pck Legend WDTCNT Watchdog timer counter WDTST Watchdog timer stop time register WDTBCNT Watchdog timer base counter WDTBST Watchdog timer base stop time register WDTCSR Watchdog timer control status register WDTBCNT WDTBST Comparator Figure 16 1 Block Di...

Page 791: ...his pin places the LSI in the power on reset state MRESETOUT Manual reset output Output Low level is output during manual reset execution This pin is multiplexed with the IRQOUT INTC pin Indicate the LSI s operating status STATUS1 High High Low STATUS0 High Low Low Operating Status Reset Sleep mode Normal operation STATUS 1 0 Status output Output The STATUS1 pin is multiplexed with the DRAK1 DMAC ...

Page 792: ...C 0008 32 Pck Watchdog timer counter WDTCNT R H FFCC 0010 H 1FCC 0010 32 Pck Watchdog timer base counter WDTBCNT R H FFCC 0018 H 1FCC 0018 32 Pck Table 16 3 Register States in Each Operating Mode Register Name Abbreviation Power on Reset by PRESET Pin Power on Reset by WDT H UDI Manual Reset by WDT Multiple Exception Sleep Deep Sleep Mode by SLEEP Instruction Watchdog timer stop time register WDTS...

Page 793: ...1 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R W R W R W R W R W R W R W R W Bit Initial value Code for writing H 5A R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTST R W R W R W R W R W R W R W R W R W R W R W R W R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 24 Code for writing All 0 R W Code for wr...

Page 794: ...9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOVF WOVF RSTS WT IT TME R R R R W R W R W R W R W R R R R R R R R Bit Initial value R W Code for writing H A5 Bit Bit Name Initial Value R W Description 31 to 24 Code for writing All 0 R W Code for writing H A5 These bits are always read as H 00 When writing to this register the value written to these bits must be H A5 23 to 8 All 0 R Reserved T...

Page 795: ...ual reset 4 WOVF 0 R W Watchdog Timer Overflow Flag Indicates that WDTCNT has overflowed in watchdog timer mode This flag is not set in interval timer mode 0 WDTCNT has not overflowed 1 WDTCNT has overflowed 3 IOVF 0 R W Interval Timer Overflow Flag Indicates that WDTCNT has overflowed in interval timer mode This flag is not set in watchdog timer mode 0 WDTCNT has not overflowed 1 WDTCNT has overf...

Page 796: ...19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTBST R W R W R R R R R R R W R W R W R W R W R W R W R W Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTBST R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Code for writing H 55 Bit Bit Name Initial Value R W Description 31 to 24 Code for wr...

Page 797: ...generated in interval timer mode WDTCNT is only reset by a power on reset Writing to this register is invalid 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTCNT R R R R R R R R R R R R R R R R Bit Initial value R W Bit Bit Name Initial Valu...

Page 798: ...WDTBCNT is only reset by a power on reset Writing to this register is invalid 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTBCNT R R R R R R R R R R R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTBCNT R R R R R R R R R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to...

Page 799: ...ter initializing VBR and SR the processing branches by setting PC H A000 0000 During initialization the VBR register is rest to H 0000 0000 The SR register is initialized such that the MD RB and BL bits are set to 1 the FD bit is cleared to 0 and the interrupt mask level bits IMASK3 to IMASK0 are set to B 1111 Then the CPU and peripheral modules are initialized For details refer to the register de...

Page 800: ...lizing VBR and SR the processing branches by setting PC H A000 0000 During initialization the VBR register is rest to H 0000 0000 The SR register is initialized such that the MD RB and BL bits are set to 1 the FD bit is cleared to 0 and the interrupt mask level bits IMASK3 to IMASK0 are set to B 1111 Then the CPU and peripheral modules are initialized For details refer to the register descriptions...

Page 801: ...en the WDTCNT overflows the WDT sets the WOVF flag in WDTCSR to 1 and generates a reset of the type specified by the RSTS bit After the reset state is exited WDTCNT and WDTBCNT start counting again 16 4 3 Using Interval Timer Mode In interval timer mode the WDT generates an interval timer interrupt each time the counter overflows This allows interrupt generation at regular intervals 1 Set the WDTC...

Page 802: ...restarts counting after it has overflowed In watchdog timer mode WDTCNT and WDTBCNT are cleared to 0 after the reset state is exited and start counting up again WDTCNT value WDTBCNT value WDTST H 0000 0000 H 0003 FFFF H 0000 0000 Incremented every peripheral clock Pck cycle Counting starts Flag is set Time Time TME WOVF IOVF Incremented on each WDTBCNT overflow Cleared to 0 on overflow Cleared to ...

Page 803: ...bits in WDTST If the period of peripheral clock Pck is represented as tPck ns the maximum overflow time of WDTCNT is expressed as follows 212 bit 0 262 tPck ms 1 073 tPck s The time until WDTCNT overflows becomes minimum when H 5A00 0001 is written to WDTST In this case the overflow time is equal to that of WDTBCNT For example if the peripheral clock frequency is 50 MHz tPck is 20 ns and the overf...

Page 804: ...ntil the reset holding time elapses The reset holding time is equal to or more than 40 cycles of the peripheral clock Pck 1 When the Power Is Turned On When the power is turned on ensure that a low level is input to the PRESET pin A low level input is also needed on the TRST pin to initialize the H UDI The timing of reset state indication on the STATUS 1 0 pins is asynchronous On the other hand th...

Page 805: ...n The timing of reset state indication on the STATUS 1 0 pins is asynchronous The timing of indicating normal operation is synchronous with the peripheral clock Pck and is therefore asynchronous with the clocks input from the EXTAL pin and the CLKOUT pin CLKOUT output STATUS 1 0 output HH reset HH reset LL normal LL normal PLL oscillation settling time Reset holding time PRESET input EXTAL input C...

Page 806: ...The timing of reset state indication on the STATUS 1 0 pins is asynchronous The timing of indicating normal operation is synchronous with the peripheral clock Pck and is therefore asynchronous with the clocks input from the EXTAL pin and the CLKOUT pin CLKOUT output STATUS 1 0 output HH reset HH reset LL normal HL sleep PLL oscillation settling time Reset holding time PRESET input EXTAL input CLKO...

Page 807: ...LL2 circuit and the time until the LSI resumes operation WDT count up are also required In this case the WDT reset holding time is two peripheral clock Pck cycles or more 1 Power On Reset Caused by Watchdog Timer Overflow during Normal Operation The timing of indicating the reset state or normal operation on the STATUS 1 0 pins is synchronous with the peripheral clock Pck and is therefore asynchro...

Page 808: ... CLKOUT pin If the bus clock frequency has been changed from the initial value the oscillation settling time of PLL2 circuit and the time until the LSI resumes operation WDT count up are also required In this case the WDT reset holding time is two peripheral clock Pck cycles or more WDT reset setup time WDT count up WDT reset holding time WDT overflow signal CLKOUT output STATUS 1 0 output HH rese...

Page 809: ...e than eight cycles of the peripheral clock Pck 1 Manual Reset Caused by Watchdog Timer Overflow during Normal Operation The timing of indicating the reset state or normal operation on the STATUS 1 0 pins is synchronous with the peripheral clock Pck and is therefore asynchronous with the clocks input from the EXTAL pin and the CLKOUT pin WDT reset setup time WDT manual reset holding time WDT overf...

Page 810: ...n the STATUS 1 0 pins is synchronous with the peripheral clock Pck and is therefore asynchronous with the clocks input from the EXTAL pin and the CLKOUT pin WDT reset setup time WDT manual reset holding time WDT overflow signal CLKOUT output STATUS 1 0 output HH reset LL normal HL sleep EXTAL input CLKOUTENB output MRESETOUT output Figure 16 9 STATUS Output by Manual Reset Caused by WDT Overflow i...

Page 811: ...p mode and module standby mode Supports DDR2 SDRAM power supply backup mode that turns off the power supplies the 1 8 V power supply 17 1 1 Types of Power Down Modes Power down modes have the following modes and functions Sleep mode Deep sleep mode Module standby function DDR SDRAM power supply backup Table 17 1 shows the conditions of transition to each mode the states of the CPU on chip modules ...

Page 812: ... 2 and 17 3 3 Operate Operate Retained Stopped in six channel units channels 0 to 5 and channels 6 to 11 Stopped Specified modules stopped Operation retained Auto refresh or self refresh Clear the corresponding bits in MSTPCR0 and MSTPCR1 to 0 see sections 17 3 2 and 17 3 3 DDR2 SDRAM power supply backup 2 See section 17 7 Stopped Stopped Undefined Stopped Stopped Stopped Undefined except for the ...

Page 813: ...lexed with the DRAK0 DMAC and PK7 GPIO pins Note L means low level and H means high level 17 3 Register Descriptions Table 17 3 shows the list of registers Table 17 4 shows the register states in each processing mode Table 17 3 Register Configuration Table 17 3 Register Configuration Register Name Abbreviation R W P4 Address Area 7 Address Access Size Sync clock Sleep control register SLPCR R W H ...

Page 814: ...H 0000 0000 Retained Retained Standby display register MSTPMR H 00x0 0000 2 Retained Retained Notes 1 For details of MSTPCR0 and MSTPCR1 see figure 15 1 2 The initial value after a power on reset depends on the combination of mode pin states MODE11 and MODE12 If a low level signal is input to the MODE12 pin the initial value is H 0010 0000 If a high level signal is input to the MODE12 pin and a lo...

Page 815: ...0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSLP R W R W R R R R R R R R R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 R W Reserved These bits are always read as 0 The write v...

Page 816: ...R W BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSTP 3 2 MSTP 9 8 MSTP 13 12 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 30 All 0 R W Reserved These bits are always read as 0 The write value should always be 0 29 to 24 MSTP 29 24 All 0 R W Module Stop Bit 29 24 Sp...

Page 817: ...6 MSTP 17 16 All 0 R W Module Stop Bit 17 16 Specify that the clock supply to the module of the corresponding bit is stopped 17 HAC channel 1 16 HAC channel 0 0 The corresponding module operates 1 The clock to the corresponding module is stopped 15 14 All 0 R W Reserved These bits are always read as 0 The write value should always be 0 13 12 MSTP 13 12 All 0 R W Module Stop Bit 13 12 Specify that ...

Page 818: ...e corresponding module operates 1 The clock to the corresponding module is stopped 7 to 4 All 0 R W Reserved These bits are always read as 0 The write value should always be 0 3 2 MSTP 3 2 All 0 R W Module Stop Bit 3 2 Specify that the clock supply to the module of the corresponding bit is stopped 3 SIOF 2 HSPI 0 The corresponding module operates 1 The clock to the corresponding module is stopped ...

Page 819: ... R W R W R W R W R W R W R W R W BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSTP100 MSTP 105 104 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 20 All 0 R W Reserved These bits are always read as 0 The write value should always be 0 19 MSTP119 0 R W Module Stop B...

Page 820: ...nnels 11 to 6 MSTP104 DMAC channels 5 to 0 0 DMAC operates 1 DMAC stopped 3 to 1 All 0 R W Reserved These bits are always read as 0 The write value should always be 0 0 MSTP100 0 R W Module Stop Bit 100 Specifies that the clock supply to the GDTA module is stopped To stop the clock set this bit to 1 after confirming that the operation of GDTA is completed 0 GDTA operates 1 GDTA stopped Note The GD...

Page 821: ... MSTPS 105 R R R R R R R R R R R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 22 All 0 R Reserved These bits are always read as 0 The write value should always be 0 21 MSTPMPCI x R Module Stop Display Bit PCIC Indicates the state of clock supply to the PCIC module When a high level signal is input to the MODE12 pin the clock supply to the PCIC is stopped 0 PCIC ...

Page 822: ... of clock supply to the DMAC channels of the corresponding bit MSTPS105 DMAC channels 11 to 6 MSTPS104 DMAC channels 5 to 0 0 The DMAC channels operate 1 The DMAC channels stopped 3 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 MSTP100 0 R Module Stop Display Bit 100 Indicates the state of clock supply to the GDTA module 0 GDTA operates 1 GDTA stopped ...

Page 823: ...ode is performed while the module is operating 17 4 2 Releasing Sleep Mode Sleep mode is released by interrupts NMI IRQ IRL 7 0 and on chip module and reset In sleep mode interrupts are accepted even if the BL bit in the SR register is 1 If needed put SPC SSR etc to stack before executing the SLEEP instruction 1 Release by Interrupts When the NMI IRQ IRL 7 0 and on chip module interrupts are gener...

Page 824: ... halts but its register contents are retained The DU is stopped as well as the modules that were stopped by the module standby function Except for the DMAC peripheral modules continue to operate The clock continues to be output to the CKIO pin but all bus access including auto refresh stops When using memory that requires refreshing select self refreshing mode prior to making the transition to dee...

Page 825: ...n an NMI IRL IRQ GPIO or WDT interval timer interrupt is generated deep sleep mode is released and the interrupt exception handling is executed The code corresponding to the interrupt source is set in INTEVT For details of the timing of the changes in the STATUS pin that is similar to sleep mode see section 17 7 2 Releasing Sleep Mode 2 Release by Reset Deep sleep mode is released by means of a po...

Page 826: ... from the module standby state the module resumes operation SSI HSPI HAC and MMCIF are initialized by a manual reset even if they are in the module standby state Confirm that the operation of GDTA is completed before putting GDTA and DMAC in the module standby state Note For details of the description of the individual MSTP bits in the standby control registers see section 17 3 2 Standby Control R...

Page 827: ... 17 7 2 Releasing Sleep Mode 1 When Sleep Mode Is Released by an Interrupt Figure 17 1 shows the timing of the changes in the STATUS pin Interrupt request LL Normal HL Sleep LL Normal CLKOUT IRQOUT output STATUS 1 0 output Figure 17 1 Status Pins Output when an Interrupt Occurs in Sleep Mode 17 8 DDR SDRAM Power Supply Backup For details see section 12 5 10 DDR2 SDRAM Power Supply Backup Function ...

Page 828: ...17 Power Down Mode Rev 1 00 Jan 10 2008 Page 798 of 1658 REJ09B0261 0100 ...

Page 829: ...is selected or input capture function is used Channels 0 to 2 32 bit timer constant register for auto reload use readable writable at any time and 32 bit down counter provided for each channel Selection of six counter input clocks Channels 0 to 2 External clock TCLK and five internal clocks Pck 4 Pck 16 Pck 64 Pck 256 and Pck 1024 obtained by dividing the peripheral clock Pck is the peripheral clo...

Page 830: ...I2 Pck 4 Pck 16 Pck 64 TUNI3 TUNI4 TUNI5 Prescaler To each channel Interrupt controller Clock controller Interrupt controller Clock controller Interrupt controller TCOR TCNT TCR TCOR TCNT TCR Peripheral bus TCOR TCNT TCPR2 Bus interface Legend TCNT TCOR TCPR2 TCR TSTR0 TSTR1 Timer counter Timer constant register Input capture register 2 channel 2 only Timer control register Timer start register Fi...

Page 831: ...EJ09B0261 0100 18 2 Input Output Pins Table 18 1 shows the TMU pin configuration Table 18 1 Pin Configuration Pin Name Abbrev I O Description Clock input TCLK Input External clock input pin for channels 0 1 and 2 input capture control input pin for channel 2 ...

Page 832: ...001C 16 Pck Timer constant register 2 TCOR2 R W H FFD8 0020 H 1FD8 0020 32 Pck Timer counter 2 TCNT2 R W H FFD8 0024 H 1FD8 0024 32 Pck Timer control register 2 TCR2 R W H FFD8 0028 H 1FD8 0028 16 Pck 2 Input capture register 2 TCPR2 R H FFD8 002C H 1FD8 002C 32 Pck Common to 3 4 5 Timer start register 1 TSTR1 R W H FFDC 0004 H 1FDC 0004 8 Pck Timer constant register 3 TCOR3 R W H FFDC 0008 H 1FDC...

Page 833: ... constant register 2 TCOR2 H FFFF FFFF H FFFF FFFF Retained Retained Timer counter 2 TCNT2 H FFFF FFFF H FFFF FFFF Retained Retained Timer control register 2 TCR2 H 0000 H 0000 Retained Retained 2 Input capture register 2 TCPR2 Retained Retained Retained Retained Common to 3 4 5 Timer start register 1 TSTR1 H 00 H 00 Retained Retained Timer constant register3 TCOR3 H FFFF FFFF H FFFF FFFF Retained...

Page 834: ...Name Initial Value R W Description 7 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 STR2 0 R W Counter Start 2 Specifies whether TCNT2 is operated or stopped 0 TCNT2 count operation is stopped 1 TCNT2 performs count operation 1 STR1 0 R W Counter Start 1 Specifies whether TCNT1 is operated or stopped 0 TCNT1 count operation is stopped 1 TCNT1 performs co...

Page 835: ...0 The write value should always be 0 2 STR5 0 R W Counter Start 5 Specifies whether TCNT5 is operated or stopped 0 TCNT5 count operation is stopped 1 TCNT5 performs count operation 1 STR4 0 R W Counter Start 4 Specifies whether TCNT4 is operated or stopped 0 TCNT4 count operation is stopped 1 TCNT4 performs count operation 0 STR3 0 R W Counter Start 3 Specifies whether TCNT3 is operated or stopped...

Page 836: ...W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 BIt Initial value R W 18 3 3 Timer Counters TCNTn n 0 to 5 The TCNT registers are 32 bit readable writable registers Each TCNT counts down on the input clock selected by the TPSC2 to TPSC0 bits in TCR When a TCNT counter underflows while counting down the UNF flag is set in TCR of the corresponding channel At the same time the TCOR value is set in TCNT and t...

Page 837: ...alue R W TCR2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPSC0 TPSC1 TPSC2 CKEG0 CKEG1 UNIE ICPE0 ICPE1 UNF ICPF R W R W R W R W R W R W R W R W R W R W R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 15 to 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 ICPF 1 0 R W Input Capture Interrupt Flag Status...

Page 838: ...sed 01 Reserved setting prohibited 10 Input capture function is used but interrupt due to input capture TICPI2 is not enabled 11 Input capture function is used and interrupt due to input capture TICPI2 is enabled 5 UNIE 0 R W Underflow Interrupt Control Controls enabling or disabling of interrupt generation when the UNF status flag is set to 1 indicating TCNT underflow 0 Interrupt due to underflow...

Page 839: ...and can only be read 2 Writing 1 does not change the value the previous value is retained 3 Do not set in channels 3 4 and 5 18 3 5 Input Capture Register 2 TCPR2 TCPR2 is a 32 bit read only register for use with the input capture function provided only in channel 2 The input capture function is controlled by means of the ICPE and CKEG bits in TCR2 When input capture occurs the TCNT2 value is copi...

Page 840: ...xample of the counter operation setting procedure Counter operation setup Select counter clock Set up underflow interrupt generation Set up input capture interrupt generation When using input capture function Set timer constant register Load the counter with the initial value Start counting 1 1 2 3 4 5 6 2 3 4 5 6 Note When an interrupt is generated clear the source flag in the interrupt handler p...

Page 841: ... Page 811 of 1658 REJ09B0261 0100 2 Auto Reload Count Operation Figure 18 3 shows the TCNT auto reload operation TCNT value TCOR H 0000 0000 STR0 to STR5 UNF TCOR value is set in TCNT on underflow Time Figure 18 3 TCNT Auto Reload Operation ...

Page 842: ...n this case Internal clock Pck TCNT N 1 N N 1 Figure 18 4 Count Timing when Operating on Internal Clock Operating on external clock In channels 0 1 and 2 the external clock input pin TCLK input can be selected as the timer clock by means of the TPSC2 to TPSC0 bits in TCR The detected edge rising falling or both edges can be selected with the CKEG1 and CKEG0 bits in TCR Figure 18 5 shows the timing...

Page 843: ...tion is used 3 Use bits CKEG1 and CKEG0 in TCR2 to specify whether the rising or falling edge of the TCLK pin is to be used to set the TCNT value in TCPR2 When input capture occurs the TCNT2 value is set in TCPR2 only when the ICPF bit in TCR2 is 0 A new DMAC transfer request is not generated until processing of the previous request is finished Figure 18 7 shows the operation timing when the input...

Page 844: ... the interrupt enable bit UNIE for that channel are set to 1 When the input capture function is used and an input capture request is generated an interrupt is requested if the ICPF bit in TCR2 is 1 and the input capture control bits ICPE1 and ICPE0 in TCR2 are both set to 11 The TMU interrupt sources are summarized in table 18 4 Table 18 4 TMU Interrupt Sources Channel Interrupt Source Description...

Page 845: ... flags UNF and ICPF are cleared while the count is in progress make sure not to change the values of bits other than those being cleared 18 6 2 Reading from TCNT Reading from TCNT is performed synchronously with the timer count operation Note that when the timer count operation is performed simultaneously with reading from a register the synchronous processing causes the TCNT value before the coun...

Page 846: ...18 Timer Unit TMU Rev 1 00 Jan 10 2008 Page 816 of 1658 REJ09B0261 0100 ...

Page 847: ...he plane size is 480 234 when the plane size is WVGA 854 480 up to four planes can be combined when the plane size is SVGA 800 600 up to three planes can be combined Display size Display position Display data format 8 bits pixel 16 bits pixel ARGB 1555 YC Plane superpositioning Scrolling Wrap around Blinking Buffer control The internal register settings can be used to select two different control ...

Page 848: ...multiple planes are specified for YC RGB conversion the YC RGB conversion can be performed only for pixels in the uppermost plane Color Palette Four internal color palette planes are provided capable of simultaneously displaying 256 colors out of a possible 260 000 colors When 8 bits pixel data is selected in the plane display format one among the four planes can be selected Eight bit blend ratios...

Page 849: ...ransparent color determination 1 pixel division Transparent color determination 1 pixel division Transparent color determination Endian conversion SHwy packet router Dot clock generation frequency division circuit Superposition α blending EOR operation Peripheral bus interface Peripheral bus SHwy interface irq Dot clock area Peripheral clock area 128 bit bus SHck 64 bit bus DU clock area SHwy cloc...

Page 850: ...put EXHSYNC input VSYNC 1 I O Vertical synchronous output External vertical synchronous input Initial value VSYNC output EXVSYNC input Composite synchronous output signal CSYNC ODDF 1 I O Odd even field Initial value ODDF CLAMP output signal CLAMP DISP 1 Output Display interval DISP Composite synchronous output signal CSYNC DE output signal DE CDE 1 Output Color detection CDE DR0 1 Output Digital ...

Page 851: ...ted through external updates can be overwritten during the vertical blanking interval without display flicker by using the VBK flag and FRM flag in the display status register DSSR indicating the start position of the vertical blanking interval 2 Internal Update An internal update is an update which reflects the address mapped register settings with the internal update timing of the display unit D...

Page 852: ...ideo mode PnSPXR PnSPYR are also internally updated at the beginning of a field Internal updates at the beginning of each frame are performed at the falling edge of VSYNC output when the sync method of DSYSR is master mode TVM 00 or at the falling edge of EXVSYNC detected in TV sync mode TVM 10 In sync switching mode TVM 11 internal updates are not performed and data is retained The address mapped...

Page 853: ...020 H 1FF80020 32 Pck Display timing generation registers Horizontal display start position register HDSR R W H FFF80040 H 1FF80040 32 Pck Horizontal display end position register HDER R W H FFF80044 H 1FF80044 32 Pck Vertical display start position register VDSR R W H FFF80048 H 1FF80048 32 Pck Vertical display end position register VDER R W H FFF8004C H 1FF8004C 32 Pck Horizontal scan period reg...

Page 854: ...0098 32 Pck Raster interrupt offset register RINTOFSR R W H FFF8009C H 1FF8009C 32 Pck Display plane registers Plane 1 mode register P1MR R W H FFF80100 H 1FF80100 32 Pck Plane 1 memory width register P1MWR R W H FFF80104 H 1FF80104 32 Pck Plane 1 blend ratio register P1ALPHAR R W H FFF80108 H 1FF80108 32 Pck Plane 1 display size X register P1DSXR R W H FFF80110 H 1FF80110 32 Pck Plane 1 display s...

Page 855: ...YR R W H FFF80214 H 1FF80214 32 Pck Plane 2 display position X register P2DPXR R W H FFF80218 H 1FF80218 32 Pck Plane 2 display position Y register P2DPYR R W H FFF8021C H 1FF8021C 32 Pck Plane 2 display area start address 0 register P2DSA0R R W H FFF80220 H 1FF80220 32 Pck Plane 2 display area start address 1 register P2DSA1R R W H FFF80224 H 1FF80224 32 Pck Plane 2 start position X register P2SP...

Page 856: ...lane 3 start position Y register P3SPYR R W H FFF80334 H 1FF80334 32 Pck Plane 3 wrap around start position register P3WASPR R W H FFF80338 H 1FF80338 32 Pck Plane 3 wrap around memory width register P3WAMWR R W H FFF8033C H 1FF8033C 32 Pck Plane 3 blinking period register P3BTR R W H FFF80340 H 1FF80340 32 Pck Plane 3 transparent color 1 register P3TC1R R W H FFF80344 H 1FF80344 32 Pck Plane 3 tr...

Page 857: ...ster P4TC2R R W H FFF80448 H 1FF80448 32 Pck Plane 4 memory length register P4MLR R W H FFF80450 H 1FF80450 32 Pck Plane 5 mode register P5MR R W H FFF80500 H 1FF80500 32 Pck Plane 5 memory width register P5MWR R W H FFF80504 H 1FF80504 32 Pck Plane 5 blend ratio register P5ALPHAR R W H FFF80508 H 1FF80508 32 Pck Plane 5 display size X register P5DSXR R W H FFF80510 H 1FF80510 32 Pck Plane 5 displ...

Page 858: ...6 display size Y register P6DSYR R W H FFF80614 H 1FF80614 32 Pck Plane 6 display position X register P6DPXR R W H FFF80618 H 1FF80618 32 Pck Plane 6 display position Y register P6DPYR R W H FFF8061C H 1FF8061C 32 Pck Plane 6 display area start address 0 register P6DSA0R R W H FFF80620 H 1FF80620 32 Pck Plane 6 display area start address 1 register P6DSA1R R W H FFF80624 H 1FF80624 32 Pck Plane 6 ...

Page 859: ...F82000 32 Pck Color palette 2 register 255 CP2_255R R W H FFF823FC H 1FF823FC 32 Pck Color palette 3 register 000 CP3_000R R W H FFF83000 H 1FF83000 32 Pck Color palette 3 register 255 CP3_255R R W H FFF833FC H 1FF833FC 32 Pck Color palette 4 register 000 CP4_000R R W H FFF84000 H 1FF84000 32 Pck Color palette 4 register 255 CP4_255R R W H FFF843FC H 1FF843FC 32 Pck External synchronization contro...

Page 860: ...s except the following bits which are updated by the DRES bit in the display system control register DSYSR VSPM ODPM DIPM CSPM DIL VSL HSL Display status register DSSR H 30000000 Retained Retained Retained Retained None Display status register clear register DSRCR Undefined Retained Retained Retained Retained None Display interrupt enable register DIER H 00000000 Retained Retained Retained Retaine...

Page 861: ...gister HCR Undefined Retained Retained Retained Retained All bits Horizontal synchronous pulse width register HSWR Undefined Retained Retained Retained Retained All bits Vertical scan period register VCR Undefined Retained Retained Retained Retained All bits Vertical synchronous position register VSPR Undefined Retained Retained Retained Retained All bits Equivalent pulse width register EQWR Undef...

Page 862: ...register DOOR Undefined Retained Retained Retained Retained All bits Color detection register CDER Undefined Retained Retained Retained Retained All bits Base color register BPOR Undefined Retained Retained Retained Retained All bits Raster interrupt offset register RINTOFSR Undefined Retained Retained Retained Retained All bits Display plane registers Plane 1 mode register P1MR H 00000000 Retaine...

Page 863: ...ained Retained Retained Retained All bits Plane 1 wrap around start position register P1WASPR Undefined Retained Retained Retained Retained All bits Plane 1 wrap around memory width register P1WAMWR Undefined Retained Retained Retained Retained All bits Plane 1 blinking period register P1BTR H 00000101 Retained Retained Retained Retained All bits Plane 1 transparent color 1 register P1TC1R Undefin...

Page 864: ...Retained All bits Plane 2 display area start address 1 register P2DSA1R Undefined Retained Retained Retained Retained All bits Plane 2 start position X register P2SPXR Undefined Retained Retained Retained Retained All bits Plane 2 start position Y register P2SPYR Undefined Retained Retained Retained Retained All bits Plane 2 wrap around start position register P2WASPR Undefined Retained Retained R...

Page 865: ...ned Retained Retained Retained All bits Plane 3 display position Y register P3DPYR Undefined Retained Retained Retained Retained All bits Plane 3 display area start address 0 register P3DSA0R Undefined Retained Retained Retained Retained All bits Plane 3 display area start address 1 register P3DSA1R Undefined Retained Retained Retained Retained All bits Plane 3 start position X register P3SPXR Und...

Page 866: ...ined Retained Retained Retained All bits Plane 4 display size Y register P4DSYR Undefined Retained Retained Retained Retained All bits Plane 4 display position X register P4DPXR Undefined Retained Retained Retained Retained All bits Plane 4 display position Y register P4DPYR Undefined Retained Retained Retained Retained All bits Plane 4 display area start address 0 register P4DSA0R Undefined Retai...

Page 867: ...R Undefined Retained Retained Retained Retained All bits Plane 5 blend ratio register P5ALPHAR Undefined Retained Retained Retained Retained All bits Plane 5 display size X register P5DSXR Undefined Retained Retained Retained Retained All bits Plane 5 display size Y register P5DSYR Undefined Retained Retained Retained Retained All bits Plane 5 display position X register P5DPXR Undefined Retained ...

Page 868: ...d Retained Retained Retained Retained All bits Plane 5 memory length register P5MLR H 00000000 Retained Retained Retained Retained All bits Plane 6 mode register P6MR H 00000000 Retained Retained Retained Retained All bits Plane 6 memory width register P6MWR Undefined Retained Retained Retained Retained All bits Plane 6 blend ratio register P6ALPHAR Undefined Retained Retained Retained Retained Al...

Page 869: ... memory width register P6WAMWR Undefined Retained Retained Retained Retained All bits Plane 6 blinking period register P6BTR H 00000101 Retained Retained Retained Retained All bits Plane 6 transparent color 1 register P6TC1R Undefined Retained Retained Retained Retained All bits Plane 6 transparent color 2 register P6TC2R Undefined Retained Retained Retained Retained All bits Plane 6 memory length...

Page 870: ... 3 register 255 CP3_255R Undefined Retained Retained Retained Retained All bits Color palette 4 register 000 CP4_000R Undefined Retained Retained Retained Retained All bits Color palette 4 register 255 CP4_255R Undefined Retained Retained Retained Retained All bits External synchronization control register External synchronization control register ESCR H 00000000 Retained Retained Retained Retaine...

Page 871: ...W R W R W R W R W R W R R R R R R O 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 SCM TVM DEN DRES 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 21 All 0 R Reserved These bits are always read as 0 The write value should always be 0 20 DSEC 0 R W Yes Display Data Endian Conversion For details of data swap see section 19 4 7 Endian Convers...

Page 872: ...f this bit For details of internal update see 2 Internal Update in section 19 3 Register Descriptions 0 Internal update is performed upon each vertical sync signal VSYNC assertion 1 By setting this bit to 1 internal updates can be prohibited When this bit is set to 0 register update is performed upon the next vertical sync signal VSYNC 15 to 10 All 0 R Reserved These bits are always read as 0 The ...

Page 873: ...pected operation may occur hence DRES and DEN should be set to 0 and 1 respectively after setting all the registers in the display unit DU When DEN 1 the display data is the value stored in memory from the next frame 10 Halts display and synchronization operation Halts display operation and synchronization operation Except for the following bits in DSSR register settings are held For these setting...

Page 874: ...t disabled within the LSI the level is fixed high When a clock signal is supplied to the DCLKIN pin the clock is output from the DCLKOUT pin The HSYNC pin is the EXHSYNC input the VSYNC pin is the EXVSYNC input and the ODDF pin is the ODDF input However when the ODPM bit in DSMR is 1 the ODDF pin output is clamped 10 TV synchronization mode The HSYNC pin is the EXHSYNC input the VSYNC pin is the E...

Page 875: ... 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 29 All 0 R Reserved These bits are always read as 0 The write value should always be 0 28 VSPM 0 R W VSYNC Pin Mode Settings in DSYSR are given priority over settings in this register 0 VSYNC signal is output to the VSYNC pin 1 CSYNC signal is output to the VSYNC pin 27 ODPM 0 R W ODDF Pin Mode 0 ODD...

Page 876: ...ISP signal at high level during display interval 1 DISP signal at low level during display interval 18 VSL 0 R W VSYNC Polarity Select 0 VSYNC signal is low active 1 VSYNC signal is high active 17 HSL 0 R W HSYNC Polarity Select 0 HSYNC signal is low active 1 HSYNC signal is high active 16 DDIS 0 R W DISP Output Disable 0 DISP signal is output 1 DISP signal is not output fixed to low level 15 CDEL...

Page 877: ...el output outside of display interval interval when DISP signal is inactive 12 CDED 0 R W CDE Disable 0 CDE signal is output 1 CDE signal is not output fixed to low level 11 to 9 All 0 R Reserved These bits are always read as 0 The write value should always be 0 8 ODEV 0 R W ODD Even Select for ODDF Signal 0 In interlaced display of the same frame when the ODDF pin is at low level the first half o...

Page 878: ...l of three raster scans after the falling edge of VSYNC an equivalent pulse is output followed by separation pulse for three raster scans then an equivalent pulse for three raster scans and for the interval after this the HSYNC waveform is output as CSYNC 11 1 2 raster scan after the VSYNC falling edge an equivalent pulse is output for 2 5 raster scans then separation pulse for 2 5 raster scans th...

Page 879: ...1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 30 00 R Reserved These bits are always read as 0 The write value should always be 0 29 28 11 R Reserved These bits are always read as 1 The write value should always be 1 27 to 22 All 0 R Reserved These bits are always read as 0 The write value should always be 0 21 DFB6 0 R None Dis...

Page 880: ...lay area start address 1 The address indicated by the plane 4 display area start address 1 register P4DSA1R in plane 4 is being used as the display area start address 18 DFB3 0 R None Display Frame Buffer 3 Flag 0 The address indicated by the plane 3 display area start address 0 register P3DSA0R in plane 3 is being used as the display area start address 1 The address indicated by the plane 3 displ...

Page 881: ...d by the setting of the vertical scan period register VCR 1 Indicates that the rising edge of EXVSYNC was not detected within the vertical period determined by the setting of VCR when in TV sync mode The TVR bit holds its state until cleared to 0 by the DRES bit in DSYSR or by the TVCL bit in DSRCR 14 FRM 0 R None Frame Flag 0 After clearing to 0 the FRM bit using either the DRES bit in DSYSR or t...

Page 882: ... interval from the start of the next display until raster scans set in the raster interrupt offset register have elapsed after clearing to 0 the RINT bit using either the DRES bit in DSYSR or the RICL bit in DSRCR 1 After clearing the RINT bit using either the DRES bit in DSYSR or the RICL bit in DSRCR indicates the interval from the start of the next display after raster scans set in the raster i...

Page 883: ...t Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 TVCL Undefined W None TV Synchronous Signal Error Flag Clear 0 The TVR flag in DSSR is not changed 1 The TVR flag in DSSR is cleared to 0 14 FRCL Undefined W None Flame Flag Clear 0 The FRM flag in DSSR is not changed 1 The FRM f...

Page 884: ...ays be 0 19 3 5 Display Unit Interrupt Enable Register DIER The display unit interrupt enable register DIER is a register which enables interrupts to the CPU the causes of which are internal states of the display unit DU reflected in DSSR When bits are set in this register if bits in the same bit positions in DSSR are set an interrupt is issued to the CPU R W Internal update R W Internal update 16...

Page 885: ... DSSR 13 12 All 0 R Reserved These bits are always read as 0 The write value should always be 0 11 VBE 0 R W None Vertical Blanking Flag Interrupt Enable 0 Disables interrupt by the VBK flag in DSSR 1 Enables interrupt by the VBK flag in DSSR 10 0 R Reserved This bit is always read as 0 The write value should always be 0 9 RIE 0 R W None Vertical Blanking Flag Interrupt Enable 0 Disables interrupt...

Page 886: ...PU from the display unit DU Conditions for issuing an interrupt a b c d e a TVR TVE b FRM FRE c VBK VBE d RINT RIE e HBK HBE Interrupts from the display unit DU are reflected by bit 27 of the interrupt source register not affected by the mask state INT2A0 or by bit 27 of the interrupt source register affected by the mask state INT2A1 of the interrupt controller INTC ...

Page 887: ...R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 20 All 0 R Reserved These bits are always read as 0 The write value should always be 0 19 CP4CE 0 R W Yes Color Palette 4 Change Enable 0 Switching of color palette 4 is not performed 1 Switching of color palette 4 is performed Switc...

Page 888: ...or palette 2 is performed Switching is performed when the DRES bit in DSYSR is changed from 1 to 0 or with the timing of an internal update This bit can only be set to 1 an operation to set the bit to 0 is invalid After switching of the color palette 2 the bit is cleared to 0 When setting to 1 and clearing occur simultaneously clearing to 0 takes priority 16 CP1CE 0 R W Yes Color Palette 1 Change ...

Page 889: ... 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 DPS1 DPE1 DPS2 DPE2 DPS3 DPE3 DPS4 DPE4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 24 All 0 R Reserved These bits are always read as 0 The write value should always be 0 23 DPE6 0 R W Yes Display Plane Priority 6 Enable 22 to 20 DPS6 101 R W Yes Display Plane Priority 6 Select 1000 Select...

Page 890: ...lects and displays plane 5 in priority 5 1101 Selects and displays plane 6 in priority 5 1110 Setting prohibited 1111 Setting prohibited 0 Priority 5 is not displayed 15 DPE4 0 R W Yes Display Plane Priority 4 Enable 14 to 12 DPS4 011 R W Yes Display Plane Priority 4 Select 1000 Selects and displays plane 1 in priority 4 1001 Selects and displays plane 2 in priority 4 1010 Selects and displays pla...

Page 891: ...W Yes Display Plane Priority 2 Select 1000 Selects and displays plane 1 in priority 2 1001 Selects and displays plane 2 in priority 2 1010 Selects and displays plane 3 in priority 2 1011 Selects and displays plane 4 in priority 2 1100 Selects and displays plane 5 in priority 2 1101 Selects and displays plane 6 in priority 2 1110 Setting prohibited 1111 Setting prohibited 0 Priority 2 is not displa...

Page 892: ...R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSAE ABRE DCKE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 6 All 0 R Reserved These bits are always read as undefined The write value should always be 0 5 DCKE 0 R W None Input Dot Clock Select Enable 0 The DCLKSEL bit and bit 4 of the FRQSEL bits in the external sync control ...

Page 893: ...ALPHAR are enabled The following can be selected as the alpha blend ratio Selection is performed using the PnBRSL bits in PnALPHAR PnALPHA bits in PnALPHAR The 31 to 24 bits in the color palette registers 1 to 4 Alpha plane data display data For the alpha blend ratio refer to section 19 4 9 Superpositioning of Planes 3 to 1 All 0 R Reserved These bits are always read as undefined The write value s...

Page 894: ... 23 24 25 26 27 28 29 31 30 Bit Initial value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R R R R R R R O O O O O O O O O 0 0 0 0 0 0 0 HDS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 9 All 0 R Reserved These bits are always read as 0 The write value should always be...

Page 895: ... 24 25 26 27 28 29 31 30 Bit Initial value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R R R R R O O O O O O O O O O O 0 0 0 0 0 HDE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 11 All 0 R Reserved These bits are always read as 0 The write value should always ...

Page 896: ...23 24 25 26 27 28 29 31 30 Bit Initial value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R R R R R R R O O O O O O O O O 0 0 0 0 0 0 0 VDS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 9 All 0 R Reserved These bits are always read as 0 The write value should always be ...

Page 897: ...24 25 26 27 28 29 31 30 Bit Initial value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R R R R R R O O O O O O O O O O 0 0 0 0 0 0 VDE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 10 All 0 R Reserved These bits are always read as 0 The write value should always be ...

Page 898: ... 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R R R R R O O O O O O O O O O O 0 0 0 0 0 HC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 to 0 HC Undefined R W Yes Horizontal Cycle One horizontal scan period including the horizon...

Page 899: ...2 23 24 25 26 27 28 29 31 30 Bit Initial value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R R R R R R R O O O O O O O O O 0 0 0 0 0 0 0 HSW 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 9 0 R Reserved These bits are always read as 0 The write value should always be 0 ...

Page 900: ... W R W R W R W R W R W R W R W R W R W R R R R R R O O O O O O O O O O 0 0 0 0 0 0 VC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 to 0 VC Undefined R W Yes Vertical Cycle The vertical scan interval including the vertical blanking inte...

Page 901: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R R R R R R O O O O O O O O O O 0 0 0 0 0 0 VSP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 to 0 VSP Undefined R W Yes Vertical Sync Point The start position of ...

Page 902: ...al value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R R R R R R R R R O O O O O O O 0 0 0 0 0 0 0 0 0 EQW 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 7 All 0 R Reserved These bits are always read as 0 The write value should always be 0 6 to 0 EQW Undefined R W Yes Equal Pul...

Page 903: ... R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R R R R R R O O O O O O O O O O 0 0 0 0 0 0 SPW 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 to 0 SPW Undefined R W Yes Separation Width The low level pulse...

Page 904: ...R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R R R R R O O O O O O O O O O O 0 0 0 0 0 CLAMPS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Bit Name Initial Value R W Internal Update Description 31 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 to 0 CLAMPS Undefined R W Yes Clamp Signal Start The...

Page 905: ...28 29 31 30 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R R R R R O O O O O O O O O O O 0 0 0 0 0 CLAMPW 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Bit Name Initial Value R W Internal Update Description 31 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 to 0 CLAMPW Undefined R W Yes Clamp Si...

Page 906: ... R R R R R O O O O O O O O O O O 0 0 0 0 0 DES 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 to 0 DES Undefined R W Yes DE Signal Start The DE signal rising edge position should be set in dot clock units relative to the falling edge of...

Page 907: ... R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R R R R R O O O O O O O O O O O 0 0 0 0 0 DEW 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 to 0 DEW Undefined R W Yes DE Signal Wid...

Page 908: ... CP1IF CP1IE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 CP1IF 0 R W Yes Color Palette 1 Index F 0 The color with index F in color palette 1 is not set to the transparent color 1 The color with index F in color palette 1 is set to th...

Page 909: ...color with index A in color palette 1 is set to the transparent color 9 CP1I9 0 R W Yes Color Palette 1 Index 9 0 The color with index 9 in color palette 1 is not set to the transparent color 1 The color with index 9 in color palette 1 is set to the transparent color 8 CP1I8 0 R W Yes Color Palette 1 Index 8 0 The color with index 8 in color palette 1 is not set to the transparent color 1 The colo...

Page 910: ... 1 Index 3 0 The color with index 3 in color palette 1 is not set to the transparent color 1 The color with index 3 in color palette 1 is set to the transparent color 2 CP1I2 0 R W Yes Color Palette 1 Index 2 0 The color with index 2 in color palette 1 is not set to the transparent color 1 The color with index 2 in color palette 1 is set to the transparent color 1 CP1I1 0 R W Yes Color Palette 1 I...

Page 911: ... CP2IF CP2IE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 CP2IF 0 R W Yes Color Palette 2 Index F 0 The color with index F in color palette 2 is not set to the transparent color 1 The color with index F in color palette 2 is set to th...

Page 912: ...color with index A in color palette 2 is set to the transparent color 9 CP2I9 0 R W Yes Color Palette 2 Index 9 0 The color with index 9 in color palette 2 is not set to the transparent color 1 The color with index 9 in color palette 2 is set to the transparent color 8 CP2I8 0 R W Yes Color Palette 2 Index 8 0 The color with index 8 in color palette 2 is not set to the transparent color 1 The colo...

Page 913: ... 2 Index 3 0 The color with index 3 in color palette 2 is not set to the transparent color 1 The color with index 3 in color palette 2 is set to the transparent color 2 CP2I2 0 R W Yes Color Palette 2 Index 2 0 The color with index 2 in color palette 2 is not set to the transparent color 1 The color with index 2 in color palette 2 is set to the transparent color 1 CP2I1 0 R W Yes Color Palette 2 I...

Page 914: ... CP3IF CP3IE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 CP3IF 0 R W Yes Color Palette 3 Index F 0 The color with index F in color palette 3 is not set to the transparent color 1 The color with index F in color palette 3 is set to th...

Page 915: ...color with index A in color palette 3 is set to the transparent color 9 CP3I9 0 R W Yes Color Palette 3 Index 9 0 The color with index 9 in color palette 3 is not set to the transparent color 1 The color with index 9 in color palette 3 is set to the transparent color 8 CP3I8 0 R W Yes Color Palette 3 Index 8 0 The color with index 8 in color palette 3 is not set to the transparent color 1 The colo...

Page 916: ... 3 Index 3 0 The color with index 3 in color palette 3 is not set to the transparent color 1 The color with index 3 in color palette 3 is set to the transparent color 2 CP3I2 0 R W Yes Color Palette 3 Index 2 0 The color with index 2 in color palette 3 is not set to the transparent color 1 The color with index 2 in color palette 3 is set to the transparent color 1 CP3I1 0 R W Yes Color Palette 3 I...

Page 917: ... CP4IF CP4IE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 CP4IF 0 R W Yes Color Palette 4 Index F 0 The color with index F in color palette 4 is not set to the transparent color 1 The color with index F in color palette 4 is set to th...

Page 918: ...color with index A in color palette 4 is set to the transparent color 9 CP4I9 0 R W Yes Color Palette 4 Index 9 0 The color with index 9 in color palette 4 is not set to the transparent color 1 The color with index 9 in color palette 4 is set to the transparent color 8 CP4I8 0 R W Yes Color Palette 4 Index 8 0 The color with index 8 in color palette 4 is not set to the transparent color 1 The colo...

Page 919: ... 4 Index 3 0 The color with index 3 in color palette 4 is not set to the transparent color 1 The color with index 3 in color palette 4 is set to the transparent color 2 CP4I2 0 R W Yes Color Palette 4 Index 2 0 The color with index 2 in color palette 4 is not set to the transparent color 1 The color with index 2 in color palette 4 is set to the transparent color 1 CP4I1 0 R W Yes Color Palette 4 I...

Page 920: ...lue Bit Bit Name Initial Value R W Internal Update Description 31 to 24 All 0 R Reserved These bits are always read as 0 The write value should always be 0 23 to 18 DOR Undefined R W Yes Display Off Mode Output Red Red color display data for output when the display is off should be set 17 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 to 10 DOG Undefined ...

Page 921: ...R O O O O O O 0 0 0 0 0 0 0 0 0 0 CDR R R R W R W R W R W R W R W R R R W R W R W R W R W R W O O O O O O O O O O O O 0 0 0 0 CDB CDG 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Bit Name Initial Value R W Internal Update Description 31 to 24 All 0 R Reserved These bits are always read as 0 The write value should always be 0 23 to 18 CDR Undefined R W Yes Color Detection Red Red color data for color ...

Page 922: ...25 26 27 28 29 31 30 Bit Initial value R R R W R W R W R W R W R W R R R R R R R R O O O O O O 0 0 0 0 0 0 0 0 0 0 BPOR R R R W R W R W R W R W R W R R R W R W R W R W R W R W O O O O O O O O O O O O 0 0 0 0 BPOB BPOG 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 24 All 0 R Reserved These bits are always read as 0 The write...

Page 923: ...tion 9 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 to 2 BPOB Undefined R W Yes Background Plane Output Blue The blue color display data to be output when there is no plane for display should be set 1 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 ...

Page 924: ...0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R R R R R R O O O O O O O O O O 0 0 0 0 0 0 RINTOFS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 to 0 RINTOFS Undefined R W Yes Raster Interrupt Offset The raster offset v...

Page 925: ... R Reserved These bits are always read as 0 The write value should always be 0 20 PnYCDF 0 R W Yes Plane n YC Data Format 0 Sets the order of YC data to UYVY format 1 Sets the order of YC data to YUYV format 19 18 All 0 R Reserved These bits are always read as 0 The write value should always be 0 17 PnTC 0 R W Yes Plane n Transparent Color 0 When set to 8 bits pixel display the transparent color i...

Page 926: ...ane When plane n is the transparent color the EOR operation is not performed and the lower plane is displayed 011 Setting prohibited 100 Transparent color processing is not performed for plane n Plane n is displayed 101 Blending of plane n and the lower plane is performed The transparent color specification for plane n is ignored and blending is performed between all the pixels of plane n and the ...

Page 927: ...mode switching of the frame buffer for display is performed When the PnDC bit is 0 bit setting is possible Switching is performed in frame units After frame buffer switching after vertical blanking detection this bit is cleared to 0 6 0 R Reserved This bit is always read as 0 The write value should always be 0 5 4 PnBM 0 R W Yes Plane n Buffer Mode When set to manual display change mode or auto di...

Page 928: ... R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R W R W R W R W R W R W R W R W R W R R R O O O O O O O O O 0 0 0 0 0 0 0 PnMWX 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 13 All 0 R Reserved These bits are always read as 0 The write value should always be 0 12 to 4 PnMWX Undefined R W Yes Plane n Memory Widt...

Page 929: ...te R W Internal update 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R R R R R R O O O O O O O O O O 0 0 0 0 0 0 0 0 PnALPHA PnBRSL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 10 All 0 R Reserved The...

Page 930: ...e the blend ratio Bits 2 to 0 000 Display data for plane 1 is the blend ratio Bits 2 to 0 001 Display data for plane 2 is the blend ratio Bits 2 to 0 010 Display data for plane 3 is the blend ratio Bits 2 to 0 011 Display data for plane 4 is the blend ratio Bits 2 to 0 100 Display data for plane 5 is the blend ratio Bits 2 to 0 101 Display data for plane 6 is the blend ratio Notes 1 When the regis...

Page 931: ...ane n The value is retained during power on reset and manual reset R W Internal update R W Internal update 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R R R R R O O O O O O O O O O O 0 0 0 0 0 PnDSX 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name In...

Page 932: ...9 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R R R R R R O O O O O O O O O O 0 0 0 0 0 0 PnDSY 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 10 All 0 R Reserved These bits are always read as 0 The write value s...

Page 933: ... 30 Bit Initial value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R R R R R O O O O O O O O O O O 0 0 0 0 0 PnDPX 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 to 0 PnDPX ...

Page 934: ...30 Bit Initial value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R R R R R R O O O O O O O O O O 0 0 0 0 0 0 PnDPY 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 to 0 PnDPY Unde...

Page 935: ...W O O O O O O O O O O O O 0 0 0 0 PnDSA0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 4 PnDSA0 Undefined R W Yes Plane n Display Area Start Address 0 To enable the 31 to 29 bits the DSAE bit in DEFR should be set to 1 In the initial state the bits are not enabled and are fixed at 0 When the buffer mode for plane n is manua...

Page 936: ...W O O O O O O O O O O O O 0 0 0 0 PnDSA1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 4 PnDSA1 Undefined R W Yes Plane n Display Area Start Address 1 To enable the 31 to 29 bits the DSAE bit in DEFR should be set to 1 In the initial state the bits are not enabled and are fixed at 0 When the buffer mode for plane n is manua...

Page 937: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R R R R O O O O O O O O O O O O 0 0 0 0 PnSPX 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 12 All 0 R Reserved These bits are always read as 0 The write value should always be 0 11 to 0 PnSPX Undefined R W Yes Plane n Start Position X The horizonta...

Page 938: ...R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W O O O O O O O O O O O O O O O O PnSPY 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 to 0 PnSPY Undefined R W Yes Plane n Start Position Y...

Page 939: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R W R W R W R W R W R W R W R W R W R W R R O O O O O O O O O O 0 0 0 0 0 0 PnWASPY 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 14 All 0 R Reserved These bits are always read as 0 The write value should always be 0 13 to 4 PnWASPY Undefined R W Yes Plane n Wrap Around Start Positio...

Page 940: ... 25 26 27 28 29 31 30 Bit Initial value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R R R R O O O O O O O O O O O O 0 0 0 0 PnWAMWY 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 12 All 0 R Reserved These bits are always read as 0 The write value should alwa...

Page 941: ...nternal update R W Internal update 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W O O O O O O O O O O O O O O O O 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 PnBTB PnBTA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal...

Page 942: ...Initial value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R R R R R R R R O O O O O O O O 0 0 0 0 0 0 0 0 PnTC1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 to 0 PnTC1 Undefined R W Ye...

Page 943: ...t Initial value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W O O O O O O O O O O O O O O O O PnTC2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 to 0 Pn...

Page 944: ...W R W R W R W R W R W R W R W O O O O O O O O O O O O O O O O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PnMLY 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 17 All 0 R Reserved These bits are always read as 0 The write value should always be 0 16 to 0 PnMLY 0 R W Yes Plane n Memory Length Y The memory length Y direction memory area fo...

Page 945: ... W R W R W R W R W R W R W R W O O O O O O O O O O O O O O 0 0 CP1_000R to CP1_255R CP1_000A to CP1_255A R R R W R W R W R W R W R W R R R W R W R W R W R W R W O O O O O O O O O O O O 0 0 0 0 CP1_000B to CP1_255B CP1_000G to CP1_255G 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Bit Name Initial Value R W Internal Update Description 31 to 24 CP1_000A to CP1_255A Undefined R W Yes Color Palette 1_000 ...

Page 946: ...t six bits for each of the RGB components of a color and are used as a color palette capable of displaying 256 colors among 260 000 possible colors Bits 31 to 24 are used as a blend ratio The values are valid for 8 bits pixel data display For details of color palette operation refer to section 19 4 8 Color Palettes Values are retained during power on reset and manual reset R W Internal update R W ...

Page 947: ...00R to CP2_255R Undefined R W Yes Color Palette 2_000 to 255 Red Red color data of color palette 2 should be set 17 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 to 10 CP2_000G to CP2_255G Undefined R W Yes Color Palette 2_000 to 255 Green Green color data of color palette 2 should be set 9 8 All 0 R Reserved These bits are always read as 0 The write val...

Page 948: ... R W R W R W O O O O O O O O O O O O O O 0 0 CP3_000R to CP3_255R CP3_000A to CP3_255A R R R W R W R W R W R W R W R R R W R W R W R W R W R W O O O O O O O O O O O O 0 0 0 0 CP3_000B to CP3_255B CP3_000G to CP3_255G 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Internal Update Description 31 to 24 CP3_000A to CP3_255A Undefined R W Yes Color Palette 3_000 ...

Page 949: ...t six bits for each of the RGB components of a color and are used as a color palette capable of displaying 256 colors among 260 000 possible colors Bits 31 to 24 are used as a blend ratio The values are valid for 8 bits pixel data display For details of color palette operation refer to section 19 4 8 Color Palettes Values are retained during power on reset and manual reset R W Internal update R W ...

Page 950: ...00R to CP4_255R Undefined R W Yes Color Palette 4_000 to 255 Red Red color data of color palette 4 should be set 17 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 to 10 CP4_000G to CP4_255G Undefined R W Yes Color Palette 4_000 to 255 Green Green color data of color palette 4 should be set 9 8 All 0 R Reserved These bits are always read as 0 The write val...

Page 951: ...Description 31 to 21 All 0 R Reserved These bits are always read as 0 The write value should always be 0 20 DCLKSEL 0 R W None DOTCLKIN Select To enable this bit the DCKE bit in DEFR should be set to 1 In the initial state this bit is fixed to 0 0 The input dot clock source is the DCLKIN pin 1 The input dot clock is DUck This setting should be made such that the frequency of the frequency divided ...

Page 952: ...k for division 01100 Division by 13 of the input dot clock clock for division 01101 Division by 14 of the input dot clock clock for division 01110 Division by 15 of the input dot clock clock for division 01111 Division by 16 of the input dot clock clock for division 10000 Division by 17 of the input dot clock clock for division 10001 Division by 18 of the input dot clock clock for division 10010 D...

Page 953: ...stment R W Internal update R W Internal update 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value R R R R R W R W R W R R W R W R W R R W R W R R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRGBA CLAMPA DEA R W R W R W R R W R W R W R R W R W R W R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNCA DISPA CDEA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W In...

Page 954: ...d two dot clock cycles relative to the reference timing 011 The DE signal is output at the rising edge delayed three dot clock cycles relative to the reference timing 100 The DE signal is output at the falling edge preceding the reference timing by 1 2 dot clock cycle 101 The DE signal is output at the falling edge delayed 1 2 dot clock cycle relative to the reference timing 110 The DE signal is o...

Page 955: ...d two dot clock cycles relative to the reference timing 011 The CLAMP signal is output at the rising edge delayed three dot clock cycles relative to the reference timing 100 The CLAMP signal is output at the falling edge preceding the reference timing by 1 2 dot clock cycle 101 The CLAMP signal is output at the falling edge delayed 1 2 dot clock cycle relative to the reference timing 110 The CLAMP...

Page 956: ...rising edge delayed three dot clock cycles relative to the reference timing 100 The RGB signal is output at the falling edge preceding the reference timing by 1 2 dot clock cycle 101 The RGB signal is output at the falling edge delayed 1 2 dot clock cycle relative to the reference timing 110 The RGB signal is output at the falling edge delayed 1 1 2 dot clock cycles relative to the reference timin...

Page 957: ...d two dot clock cycles relative to the reference timing 011 The CDE signal is output at the rising edge delayed three dot clock cycles relative to the reference timing 100 The CDE signal is output at the falling edge preceding the reference timing by 1 2 dot clock cycle 101 The CDE signal is output at the falling edge delayed 1 2 dot clock cycle relative to the reference timing 110 The CDE signal ...

Page 958: ...d two dot clock cycles relative to the reference timing 011 The DISP signal is output at the rising edge delayed three dot clock cycles relative to the reference timing 100 The DISP signal is output at the falling edge preceding the reference timing by 1 2 dot clock cycle 101 The DISP signal is output at the falling edge delayed 1 2 dot clock cycle relative to the reference timing 110 The DISP sig...

Page 959: ...he rising edge delayed two dot clock cycles relative to the reference timing 011 The SYNC signal is output at the rising edge delayed three dot clock cycles relative to the reference timing 100 The SYNC signal is output at the falling edge preceding the reference timing by 1 2 dot clock cycle 101 The SYNC signal is output at the falling edge delayed 1 2 dot clock cycle relative to the reference ti...

Page 960: ... For each plane display can be turned on and off and the display data format 8 bits pixel 16 bits pixel ARGB YC blending functions and other settings can be changed independently Each plane has a double buffer configuration so that smooth display is possible Note In cases of high resolution display the unified memory traffic volume may be considerable depending on the number of combined planes and...

Page 961: ...trary O O Plane 3 O O 1 O O O 2 α blending transparent color EOR operation O X Y arbitrary O O Plane 4 O O 1 O O O 2 α blending transparent color EOR operation O X Y arbitrary O O Plane 5 O O 1 O O O 2 α blending transparent color EOR operation O X Y arbitrary O O Plane 6 O O 1 O O O 2 α blending transparent color EOR operation O X Y arbitrary O O Back ground color 3 Notes 1 Any among the color th...

Page 962: ... side The superpositioning order can be specified arbitrarily Background color can be specified Frame buffer 1 Frame buffer 2 Frame buffer 1 Output planes are combined and displayed according to the superpositioning order and blending mode for each plane Frame buffer 4 Frame buffer 3 Display side Frame buffer 4 Figure 19 2 Block Diagram of Plane Configuration and Superpositioning ...

Page 963: ...riority positions 1 to 6 and the corresponding enable bit is set to 1 Plane 4 Plane 4 is selected in one among priority positions 1 to 6 and the corresponding enable bit is set to 1 Plane 5 Plane 5 is selected in one among priority positions 1 to 6 and the corresponding enable bit is set to 1 Plane 6 Plane 6 is selected in one among priority positions 1 to 6 and the corresponding enable bit is set...

Page 964: ... position and display size are set using registers The followings are the schematic diagram of start positions and sizes related to planes and the registers used for setting start positions and sizes 1 MWX 2 DSA 5 SPX 6 SPY 7 DSX 8 DSY 3 WASPY 4 WAMWY 7 DSX 8 DSY 9 DPX 10 DPY Monitor origin upper left Memory parameters Monitor parameters 11 MLY Figure 19 3 Parameters ...

Page 965: ...ines 5 SPX Start position X PnSPXR The distance in the X direction to the display start position is set in pixel units taking the address set by DSA as the origin 6 SPY Start position Y PnSPYR The distance in the Y direction to the display start position is set in raster line units taking the address set by DSA as the origin 7 DSX Display size X PnDSXR The X direction display size of plane n is se...

Page 966: ...location Registers Display Plane Setting Register Name Plane 1 display area start address register 0 P1DSA0 Plane 1 Plane 1 display area start address register 1 P1DSA1 Plane 2 display area start address register 0 P2DSA0 Plane 2 Plane 2 display area start address register 1 P2DSA1 Plane 3 display area start address register 0 P3DSA0 Plane 3 Plane 3 display area start address register 1 P3DSA1 Pla...

Page 967: ...Index 0 Address A Index 0 Index 1 Index 2 Index 3 Address A 4 Index 7 Index 6 Index 5 Index 4 Address A 4 Index 4 Index 5 Index 6 Index 7 Address A 8 Index 11 Index 10 Index 9 Index 8 Address A 8 Index 8 Index 9 Index 10 Index 11 Little endian Big endian 16 bit pixel RGB The RGB levels are represented using 5 bits for R 6 bits for G and 5 bits for B RGB565 D15 D0 15 11 10 5 4 0 R G B The arrangeme...

Page 968: ...555 3 Address A 8 ARGB555 5 ARGB555 4 Address A 8 ARGB555 4 ARGB555 5 Little endian Big endian YC Image data has the format YC YCbCr 4 2 2 A calculation circuit is used to convert each of the 8 bits of the RGB colors of image data The YC data order corresponds to the UYVY format and YUYV format The UYVY format and YUYV format can be selected using the PnYCDF bits in PnMR The conversion formulae fo...

Page 969: ...ss A U0 Y0 V0 Y1 Address A 4 Y3 V2 Y2 U2 Address A 4 U2 Y2 V2 Y3 Address A 8 Y5 V4 Y4 U4 Address A 8 U4 Y4 V4 Y5 Little endian Big endian YUYV format A 3 A 2 A 1 A A A 1 A 2 A 3 31 23 15 7 0 31 23 15 7 0 Address A V0 Y1 U0 Y0 Address A Y0 U0 Y1 V0 Address A 4 V2 Y3 U2 Y2 Address A 4 Y2 U2 Y3 V2 Address A 8 V4 Y5 U4 Y4 Address A 8 Y4 U4 Y5 V4 Little endian Big endian ...

Page 970: ...s 0 G 5 bits 0 B 5 bits 0 YC RGB R upper 6 bits of the 8 bits G upper 6 bits of the 8 bits B upper 6 bits of the 8 bits 19 4 7 Endian Conversion The display unit DU can perform big endian little endian conversion according to the setting of the DSEC bit in DSYSR The internal data format in the display unit DU is fixed at little endian by setting the DSEC bit in DSYSR to 1 display data arranged in ...

Page 971: ...B5 B4 B3 B2 B1 B0 63 0 B15 B14 B12 B11 B10 B9 B8 127 64 W0 W1 W2 W3 63 0 W4 W5 W6 W7 63 0 127 W3 W2 W1 W0 W7 W6 W5 W4 B13 Address SHwy bus big endian Display data in the display unit DU A A 8 Data Address SHwy bus big endian Display data in the display unit DU Endian Conversion in Byte Units PnDDF 0 0 8 bits pixel PnDDF 1 1 YC Endian Conversion in Word Units PnDDF 0 1 16 bits pixel PnDDF 1 0 ARGB ...

Page 972: ...lor palette updates are being managed there is no problem with overwriting only the relevant part 2 Upon completion of color palette settings the switching enable bit must always be set to 1 3 When reading a color palette which has been written from the CPU reading should be performed before setting the switching enabled bit to 1 If read after setting the bit to 1 there is the possibility that dif...

Page 973: ...ne When the specified plane is a transparent color the lower plane is displayed Initial value 001 Blending of the specified plane with the lower plane is performed When the specified plane is a transparent color blending is not performed and the lower plane is displayed 010 EOR operation of the specified plane and the lower plane is performed When the specified plane is a transparent color EOR ope...

Page 974: ...to be used the α blending or EOR operation on off should be specified At this time when both planes for α blending or for EOR operation have the same color palette selected color palette contention only the specified plane is displayed with no α blending or EOR operation performed When display of all lower planes is turned off the specified plane is displayed That is blending or EOR operation of t...

Page 975: ...ormed according to the setting in the plane n transparent color 1 register PnTC1R When the PnTC bit PnMR is 1 up to a maximum 16 colors can be simultaneously specified for each of color palette 1 color palette 2 color palette 3 color palette 4 according to the settings in CP1TR to CP4TR Only the indexes H 00 to H 0F can be specified as transparent colors H 10 to H FF cannot be specified as transpa...

Page 976: ...ters Data Format Transparent Color Specification Bit Color Palette Select Bit Transparent Color Specification Register PnMR PnTC PnMR PnCPSL 0 PnTC1R 1 00 CP1TR 1 01 CP2TR 1 10 CP3TR 8 bits pixel 1 11 CP4TR 16 bits pixel PnTC2R ARGB PnTC2R EOR Operation EOR operation of the specified plane with the lower plane is performed ...

Page 977: ... α blending and EOR operations become invalid and the plane with the highest priority is displayed A Plane 1 α blending Plane 2 EOR operation Plane 3 Legend P1 Plane 1 P2 Plane 2 P3 Plane 3 No contention P1 is displayed P1 and P2 contention P1 is displayed P1 P2 and P3 contention P1 is displayed P2 and P3 contention P2 is displayed No contention P3 is displayed Note Bold black lines indicate the d...

Page 978: ...isplay Combining Color Palette Selection and Transparent Colors YC Data Contention The display unit DU has only one YC RGB conversion circuit internally and so YC RGB conversion cannot be performed simultaneously for two or more planes When there are pixels requiring YC RGB conversion on two or more planes simultaneously the pixels on the uppermost plane are YC RGB converted and the lower plane is...

Page 979: ...inking For each plane blinking operation can be performed by using the display area start address 0 and 1 registers Usually double buffer control is performed for each plane according to the setting of the PnBM bit in PnMR However blinking is performed with the period specified by the PnBTA and PnBTB bits in PnBTR by setting the PnBM bits in PnMR to 10 Auto display change mode blinking mode If the...

Page 980: ...ied by PnSPXR and PnSPYR taking as the origin the leading address in memory specified by PnDSA0R and PnDSA1R for each plane Figure 19 9 summarizes display scrolling The display is scrolled by setting the display start position from A to B Note Display sizes and other area settings for each plane should be set such that there is no data display outside the memory configuration area Plane 1 display ...

Page 981: ... specify the wrap around area is described below 1 The leading address of the memory used for plane n is specified in PnDSA0R and PnDSA1R 2 With the beginning of the specified memory as origin the upper left coordinates of the wrap around area are specified in PnWASPR The X direction width of the wrap around area is the memory width set in PnMWR 3 The Y direction width of the wrap around area is s...

Page 982: ...ing display data in memory For a picture of size DSX DSY and with start position SPX SPY by setting the size to DSX ΔX DSY ΔY and the start position to SPX ΔX SPY ΔY the ΔX part overflowing on the left side and the ΔY part overflowing on top can be displayed At this time the display position PnDPXR PnDPYR is fixed at 0 SPY SPX DSY DSX Monitor SPY ΔY SPX ΔX DSY ΔY DSX ΔX Monitor DSX DSY DSY ΔY DSX ...

Page 983: ...r buffer 1 start address in PnDSA0R and PnDSA1R indicated by the DFBn bit in DSSR When making a transition from this mode to another mode the PnDC bit should always be set to 1 first The following shows a control example for the manual display mode VSYNC Non interlaced Display screen operation A0 display A0 display A1 display First frame Second frame Third frame Interrupt processing Interrupt proc...

Page 984: ...the EXHSYNC signal and the rising edge of the EXVSYNC signal The horizontal sync signal vertical sync signal and clock signal from the external sync signal generation circuit are input to the HSYNC VSYNC and DCLKIN pin respectively CSYNC is at high level When in interlaced sync mode and interlaced sync video mode a signal should be input to the ODDF pin indicating odd even fields When in non inter...

Page 985: ...ync Method Switching Mode When switching from master mode into TV sync mode or from TV sync mode into master mode when necessary this mode should be switched into first Even if a transition to this mode is not made first switching of the synchronization method is possible In this mode input output pins connected to the display unit DU are for input and so pin collision can be avoided Also in this ...

Page 986: ...n and vertical direction of the display screen Display timing is set by using display timing generation registers Figure 19 13 shows the display timing in non interlaced mode Here the display screen is defined in terms of the variables of Table 19 13 hc hsw xs xw ys yw vc vsw Display area HSYNC VSYNC Figure 19 13 Display Timing Generation for Horizontal Direction and Vertical Direction of Display ...

Page 987: ...c 2 Vertical scan period Raster line vsw Vertical sync pulse width Raster line ys From rise of VSYNC to display start position in the vertical direction of the display screen Raster line yw Vertical display period of display screen Raster line Notes 1 Should be set such that hsw xs xw hc 18 decimal 2 Should be set such that vsw ys yw vc The display timing generation register settings are different...

Page 988: ...ys 2 yw Horizontal synchronous pulse width register HSWR HSW hsw 1 hsw 1 Horizontal scan period register HCR HC hc 1 hc 1 Vertical synchronous position register VSPR VSP vc vsw 1 vc vsw 1 Vertical scan period register VCR VC vc 1 vc 1 Notes The numerical values in the above table are decimal numbers 1 In all scan modes VDS VDE VSP VC settings are in single field units 2 The values of HDS and HDE a...

Page 989: ...ulse width of the CSYNC separation pulse The CSYNC waveform is selected using the CSY bit in DSMR HSW HSYNC VSYNC CSYNC CSY 00 EQW CSY 10 CSY 11 HC SPW 1 2HC When HC is odd it is rounded to an even value Equivalent pulse 2 5 rasters Separation pulse 2 5 rasters Equivalent pulse 2 5 rasters Equivalent pulse 3 rasters Separation pulse 3 rasters Equivalent pulse 3 rasters Figure 19 14 CSYNC Timing Ch...

Page 990: ... 11 1 2HC 1 2HC SPW HSW HSYNC HC Equivalent pulse 2 5 rasters Separation pulse 2 5 rasters Equivalent pulse 2 5 rasters Equivalent pulse 3 rasters Separation pulse 3 rasters Equivalent pulse 3 rasters When HC is odd it is rounded to an even value Figure 19 15 CSYNC Timing Chart Last Half of Interlace Frame ...

Page 991: ...lds The two fields are an even field and an odd field displaying different data The ODEV bit in DSMR is used to set the display order of fields in interlaced sync mode and in interlaced sync video mode When the ODEV bit is 0 the display order for one frame is odd field then even field when the ODEV bit is 1 the order for one frame is even field then odd field When in master mode high level is outp...

Page 992: ...ld Raster scanned in an even field 00 01 02 03 04 05 06 07 08 09 00 01 02 03 04 05 06 07 08 09 00 01 02 03 04 05 06 07 08 09 00 02 04 06 08 0A 0C 0E 10 12 01 03 05 07 09 0B 0D 0F 11 13 Interlaced sync video mode Non interlaced mode Interlaced sync mode Figure 19 16 Example of Display in Each Scan Mode ...

Page 993: ...ced sync video mode 1 30 second frame Display in non interlaced method In this method all lines are displayed at once without providing intervals between input video signals This input method is for monitors capable of high resolution display 0 1 2 3 476 477 HSYNC VDS VSYNC Display in non interlaced mode The ODEV and ODDF pins are not used 4 5 6 7 478 479 Figure 19 17 Display in Non Interlaced Met...

Page 994: ...field is an even field the ODDF pin is high The second field is an odd field the ODDF pin is low 2 Display in interlaced sync video mode When one frame is configured as shown below clear the ODEV bit to 0 The first field is an odd field the ODDF pin is low The second field is an even field the ODDF pin is high When one frame is configured as shown below set the ODEV bit to 1 The first field is an ...

Page 995: ...he CDE pin outside display intervals Result of comparison of output display data and color detection register Value of the color detection register CDEL CDEM Same Different 0 Other than 0 0 00 High level Low level High level Low level 0 01 High level Low level High level Low level 0 10 High level Low level Low level Low level 0 11 High level Low level High level High level 1 00 Low level High leve...

Page 996: ...tting Parameters Bit Name in OTAR Description SYNCA Sets output timing of the HSYNC VSYNC CSYNC ODDF signal DISPA Sets output timing of the DISP signal CDEA Sets output timing of the CDE signal DRGBA Sets output timing of digital RGB signal CLAMPA Sets output timing of the CLAMP signal DEA Sets output timing of the DE signal DCLKOUT Reference timing Adjustable range of output timing Register value...

Page 997: ...n dot clock units Figure 19 20 shows the timing chart However the DE signal is fixed at low level during the vertical blanking interval DCLKOUT output HSYNC signal CLAMP signal DE signal CLAMP signal DE signal CLAMP signal DE signal Starting position value 1 High level width value The minimum value of rising position 1 Start position value 1 High level width value When the HSYNC signal falls the C...

Page 998: ...ot access the display unit DU 19 6 1 Procedures before Executing the Power Down Sequence 1 Display is turned off by setting both the DEN and DRES bits in DSYSR to 0 2 Use the VBK bit in DSSR to confirm the next VBK flag because the display is turned off with the timing of VBK 3 The display unit DU displays the data in DOOR before the display is turned off 4 Execute the power down sequence 5 Displa...

Page 999: ... access is performed by the internal GADMAC to realize high speed image processing 20 1 Features CL YUV data conversion processing unit Reads an image in external memory processes the data and writes the data back to external memory Conversion modes YUV 4 2 0 YUV 4 2 2 YUYV mode ARGB8888 ARGB mode MC Video processing control unit Reads images in external memory processes the data and writes the da...

Page 1000: ...ce external external Control register Buffer RAM interface RAM 0 interface arbiter CL MC interface Buffer RAM 0 8 Kbytes Buffer RAM 1 8 Kbytes CL function block MC function block RAM 1 interface arbiter Request queue 4 planes Response queue 4 planes Color conversion table control IDCT control Arbiter CPU LBSC DDR2 SDRAM DDR2IF CLW GADMAC CLR GADMAC MCW GADMAC MCR GADMAC GDTA Figure 20 1 GDTA Block...

Page 1001: ...function blocks A total of four channels are provided including two channels for CL functions and two channels for MC functions The GADMAC is controlled through registers within the CL function block and MC function block Applications of each of the channels are as follows CLR_GADMAC Data transfer from external memory to the CL function block read data transfer CLW_GADMAC Data transfer from the CL...

Page 1002: ...T data transfer unit bus arbitration is performed The buffer RAM interface exists as two independent blocks for the two buffer RAM units Because there is no access contention even during simultaneous reading of buffer RAM 0 by the color conversion table data transfer unit and reading of buffer RAM 1 by the IDCT table transfer unit processing delays due to wait states and so on do not occur 8 CL Fu...

Page 1003: ...aces also exist in buffer RAM Note The space from H FE40_3000 to H FE40_3FFF excluding the space for registers DRCL_CTL DWCL_CTL DRMC_CTL DWMC_CTL DCP_CTL and DID_CTL is a reserved area and write access is prohibited If write access is made correct operation cannot be guaranteed Common registers for bus interface CL MC Buffer RAM 0 8 Kbytes Buffer RAM 1 8 Kbytes Reserved Undefined buffer RAM 0 mir...

Page 1004: ...t source indicating register GACISR R H FE40 0014 H 1E40 0014 32 GAck GA processing end interrupt source indication clear register GACICR W H FE40 0018 H 1E40 0018 32 GAck GA interrupt enable register GACIER R W H FE40 001C H 1E40 001C 32 GAck GA CL output data alignment register DWCL_CTL R W H FE40 3000 H 1E40 3000 32 GAck GA CL input data alignment register DRCL_CTL R W H FE40 3200 H 1E40 3200 3...

Page 1005: ... CL status register CLSR R H FE40 1008 H 1E40 1008 32 GAck CL frame width setting register CLWR R W H FE40 100C H 1E40 100C 32 GAck CL frame height setting register CLHR R W H FE40 1010 H 1E40 1010 32 GAck CL input Y padding size setting register CLIYPR R W H FE40 1014 H 1E40 1014 32 GAck CL input UV padding size setting register CLIUVPR R W H FE40 1018 H 1E40 1018 32 GAck CL output padding size s...

Page 1006: ...dding size setting register MCUVPR R W H FE40 2014 H 1E40 2014 32 GAck MC output frame Y pointer register MCOYPR R W H FE40 2018 H 1E40 2018 32 GAck MC output frame U pointer register MCOUPR R W H FE40 201C H 1E40 201C 32 GAck MC output frame V pointer register MCOVPR R W H FE40 2020 H 1E40 2020 32 GAck MC past frame Y pointer register MCPYPR R W H FE40 2024 H 1E40 2024 32 GAck MC past frame U poi...

Page 1007: ...TL H 0000 0000 H 0000 0000 Retained Retained DWMC_CTL H 0000 0000 H 0000 0000 Retained Retained DCP_CTL H 0000 0000 H 0000 0000 Retained Retained DID_CTL H 0000 0000 H 0000 0000 Retained Retained Table 20 5 GDTA States in Each Processing Mode CL Block Register Abbreviation Power On Reset Manual Reset Sleep Deep Sleep CLCF H 0000 0000 H 0000 0000 Retained H 0000_0000 CLCR H 0000 0000 H 0000 0000 Re...

Page 1008: ...H 0000 0000 H 0000 0000 Retained Retained Retained MCUVPR H 0000 0000 H 0000 0000 Retained Retained Retained MCOYPR H 0000 0000 H 0000 0000 Retained Retained Retained MCOUPR H 0000 0000 H 0000 0000 Retained Retained Retained MCOVPR H 0000 0000 H 0000 0000 Retained Retained Retained MCPYPR H 0000 0000 H 0000 0000 Retained Retained Retained MCPUPR H 0000 0000 H 0000 0000 Retained Retained Retained M...

Page 1009: ... GACER is disabled 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GACM R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GACM R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to ...

Page 1010: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CL_EN MC_EN R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 2 All 0 Reserved These bits are always read as 0 The write value should always be 0 1 MC_EN 0 R W Enables access to the MC registers 0 Writing to the MC registers is invalid The value read from the MC register is undefined 1 Reading and writing are enabled 0 CL_EN 0 R W Enables...

Page 1011: ...re always read as 0 The write value should always be 0 3 MC_EER 0 R Indicates whether an MC module error interrupt has occurred 0 No error 1 Error occurred 2 CL_EER 0 R Indicates whether a CL module error interrupt has occurred 0 No error 1 Error occurred 1 MC_END 0 R Indicates whether an MC module processing end interrupt has occurred 0 1 has been written to the MC_ENCR bit in GACICR 1 Processing...

Page 1012: ...W W W W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 4 All 0 Reserved These bits are always read as 0 The write value should always be 0 3 MC_ERCR 0 W Clears indication of an MC error interrupt clears the MC_ERR bit 0 No effect 1 Clears error interrupt indication 2 CL_ERCR 0 W Clears indication of a CL error interrupt clears the CL_ERR bit 0 No effect 1 Clears error inter...

Page 1013: ...W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 4 All 0 Reserved These bits are always read as 0 The write value should always be 0 3 MC_EREN 0 R W Controls output of an MC module error interrupt 0 Does not output the interrupt 1 Outputs the interrupt 2 CL_EREN 0 R W Controls output of a CL module error interrupt 0 Does not output the interrupt 1 Outputs the interrupt 1 MC...

Page 1014: ... BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 5 All 0 Reserved These bits are always read as 0 The write value should always be 0 4 DCLR_DTAM 0 R W Specifies data alignment conversion mode 0 Data alignment is performed using an endian signal 1 Data alignment is performed using the DRCL_CTL register setting 3 2 DCLR_DTSA 0 R W Specifies the data size for data alignment con...

Page 1015: ...W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 5 All 0 Reserved These bits are always read as 0 The write value should always be 0 4 DCLW_DTAM 0 R W Specifies data alignment conversion mode 0 Data alignment is performed using an endian signal 1 Data alignment is performed using the DWCL_CTL register setting 3 2 DCLW_DTSA 0 R W Specifies the data size for data alignment co...

Page 1016: ... BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 5 All 0 Reserved These bits are always read as 0 The write value should always be 0 4 DMCR_DTAM 0 R W Specifies data alignment conversion mode 0 Data alignment is performed using an endian signal 1 Data alignment is performed using the DRMC_CTL register setting 3 2 DMCR_DTSA 0 R W Specifies the data size for data alignment con...

Page 1017: ...W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 5 All 0 Reserved These bits are always read as 0 The write value should always be 0 4 DMCW_DTAM 0 R W Specifies data alignment conversion mode 0 Data alignment is performed using an endian signal 1 Data alignment is performed using the DWMC_CTL register setting 3 2 DMCW_DTSA 0 R W Specifies the data size for data alignment co...

Page 1018: ...R W R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 5 All 0 Reserved These bits are always read as 0 The write value should always be 0 4 DCP_DTAM 0 R W Specifies data alignment conversion mode 0 Data alignment is performed using an endian signal 1 Data alignment is performed using the DCP_CTL register setting 3 2 DCP_DTSA 0 R W Specifies the data size for data align...

Page 1019: ...R W R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 5 All 0 Reserved These bits are always read as 0 The write value should always be 0 4 DID_DTAM 0 R W Specifies data alignment conversion mode 0 Data alignment is performed using an endian signal 1 Data alignment is performed using the DID_CTL register setting 3 2 DID_DTSA 0 R W Specifies the data size for data align...

Page 1020: ...l Value R W Description 31 to 0 CL_CF 0 W Command FIFO register Notes 1 Setting Method When accessing this register the CL_EN bit in GACER should be set to 1 Access is possible only when the CL_EN bit is set to 1 If the CL_EN bit is 0 access is invalid writing is invalid the result of reading is indefinite The following shows the parameter contents assumed according to the writing order Writing Or...

Page 1021: ...and FIFO are retained and the next command is ignored 20 3 13 CL Control Register CLCR CLCR is in the CL register block and specifies the CL operating mode 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CL_MD CL_OA CL_OD CL_DA R W R W R W R W R W R W R W R W BIt Initial valu...

Page 1022: ...to YUV422 format 1 ARGB conversion Converts from YUV420 to ARGB8888 format A Table of CL_DA Register Settings And Output Data Alignment CL_DA YUYV Conversion ARGB Conversion CL_DA YUYV Conversion ARGB Conversion H 0 Y0UY1V ARGB H 10 UVY0Y1 RBAG H 1 Y0UVY1 ARBG H 11 UVY1Y0 RBGA H 2 Y0Y1UV AGRB H 12 VY1Y0U BGAR H 3 Y0Y1VU AGBR H 13 VY1UY0 BGRA H 4 Y0VY1U ABGR H 14 VY0Y1U BAGR H 5 Y0VUY1 ABRG H 15 VY...

Page 1023: ...E R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 4 All 0 Reserved These bits are always read as 0 The write value should always be 0 3 CLSR_EXE 0 R CL execution state display 0 Stopped 1 Executing 2 CL_CFF 0 R CL_CF command FIFO status display Indicates the state of command buffer reception 0 Command receivable 1 Command buffer full 1 0 CL_CFS 0 R Command pointer st...

Page 1024: ...0 CL_W R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 12 All 0 Reserved These bits are always read as 0 The write value should always be 0 11 to 0 CL_W All 0 R W Frame width setting Should be set in pixel units Value set should be 2 n n an integer greater than 0 Notes 1 CL processing is prohibited when the setting is 0 2 Addit...

Page 1025: ...9 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CL_H R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 12 All 0 Reserved These bits are always read as 0 The write value should always be 0 11 to 0 CL_H All 0 R W Frame height setting Should be set i...

Page 1026: ...1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CL_IYP R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 12 All 0 Reserved These bits are always read as 0 The write value should always be 0 11 to 0 CL_IYP All 0 R W Input Y padding size setting Should be set in byte units Value set should be 2 n n an integer gr...

Page 1027: ...0 BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CL_IUVP R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 12 All 0 Reserved These bits are always read as 0 The write value should always be 0 11 to 0 CL_IUVP All 0 R W Input UV padding size setting Should be set in byte units Notes 1 Ad...

Page 1028: ... 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CL_OP R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 12 All 0 Reserved These bits are always read as 0 The write value should always be 0 11 to 0 CL_OP All 0 R W Output padding size setting Shou...

Page 1029: ... mode 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CL_PLPT R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CL_PLPT R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 0 CL_PL...

Page 1030: ...28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MC_CF W W W W W W W W W W W W W W W W BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MC_CF W W W W W W W W W W W W W W W W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 0 MC_CF 0 W Command FIFO Register Setting Method When accessing this register the MC_EN bit in GACER should be set to...

Page 1031: ...Buffer RAM pointer Back_ Recon_down Command parameter 7 Back_ Recon_right Command parameter 8 Buffer RAM pointer MC Operating Mode Bits 2 to 0 are H 0 Intra macroblock processing Bits 2 to 0 are H 1 Forward macroblock processing Bits 2 to 0 are H 2 Reverse macroblock processing Bits 2 to 0 are H 3 Bidirectional macroblock processing Bits 2 to 0 are H 4 End command When bit 2 is 1 it is regarded as...

Page 1032: ...he buffer RAM 1 in use RAM 1 address storing IDCT data Notes on MC Command FIFO Register MCCF Settings 1 Buffer RAM pointers should point to addresses on 4 byte boundaries If not the lower address is regarded as 0 2 When setting values in this register in succession the MC module is able to receive the next command while the MC_CFF bit in MCSR is 0 To perform processing by changing the command alo...

Page 1033: ...C_CFS MC_CFF MC_CFA R R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 11 All 0 Reserved These bits are always read as 0 The write value should always be 0 10 to 8 MC_CFA All 0 R Indicates the number of commands accumulated in MCCF command FIFO maximum number accumulated is 4 Number of accumulated commands 000 0 001 1 010 2 011 3 100 4 7 to 4 All 0 Reserved These ...

Page 1034: ... input frame width in pixel units 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MC_W R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 12 All 0 Reserved These bits are always read as 0 The write value shou...

Page 1035: ... 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MC_H R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 12 All 0 Reserved These bits are always read as 0 The write value should always be 0 11 to 0 MC_H All 0 R W Frame height setting Should be set by th...

Page 1036: ...nitial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MC_YP R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 12 All 0 Reserved These bits are always read as 0 The write value should always be 0 11 to 0 MC_YP All 0 R W Input Y padding size setting Should be set by the number of bytes Notes 1 Addit...

Page 1037: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MC_UVP R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 12 All 0 Reserved These bits are always read as 0 The write value should always be 0 11 to 0 MC_UVP All 0 R W Input UV padding size setting Should be set by the number of bytes Notes 1 Addition is performed taking that 1 pixel 1 byte 2 MCWR byte...

Page 1038: ...MC_OYPT All 0 R W Output Frame Y Pointer The address should be set 0 should be written to bits 3 to 0 Note A 16 byte boundary address must be specified 20 3 28 MC Output Frame U Pointer Register MCOUPR MCOUPR is in the MC register block and specifies the U pointer address for an output frame 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MC_OUPT R W R W R W R W R W...

Page 1039: ... 0 MC_OVPT All 0 R W Output Frame V Pointer The address should be set 0 should be written to bits 2 to 0 Note An 8 byte boundary address must be specified 20 3 30 MC Past Frame Y Pointer Register MCPYPR MCPYPR is in the MC register block and specifies the Y pointer address for a past frame 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MC_PYPT R W R W R W R W R W R...

Page 1040: ...0 MC_PUPT All 0 R W Past Frame U Pointer The address should be set 0 should be written to bits 2 to 0 Note An 8 byte boundary address must be specified 20 3 32 MC Past Frame V Pointer Register MCPVPR MCPVPR is in the MC register block and specifies the V pointer address for a past frame 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MC_PVPT R W R W R W R W R W R W ...

Page 1041: ...PT All 0 R W Future Frame Y Pointer The address should be set 0 should be written to bits 3 to 0 Note A 16 byte boundary address must be specified 20 3 34 MC Future Frame U Pointer Register MCFUPR MCFUPR is in the MC register block and specifies an address to set the U pointer for a future frame 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MC_FUPT R W R W R W R W...

Page 1042: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MC_FVPT R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MC_FVPT R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 0 MC_FVPT All 0 R W Future Frame V Pointer The address should ...

Page 1043: ...sing has ended can be made by using either an interrupt or the CL_END bit in GACISR 1 Overview of YUYV Conversion Functions The following shows an outline of the YUYV conversion specification Y0 Y1 Y8 Y9 Y2 Y3 U0 U1 U4 U5 U2 U3 Y4 Y5 Y6 Y7 Input Y pointer Input U pointer Input V pointer Output pointer 1 Input data reading Frame height V0 V1 V4 V5 V2 V3 Y0 U0 Y1 V0 Y8 U0 Y10 U1 Y9 V0 Y2 U1 Y3 V1 Y4...

Page 1044: ...nteed 2 Rearrangement YUV data is rearranged according to the format indicated in the display image of figure 20 3 When converting from YUYV 4 2 0 to YUYV 4 2 2 because the data quantity for UV is 1 2 that for Y the UV data in even lines is used for the UV data in odd lines For example the UV data in line 0 is also used in line 1 Converted data is output in the converted data output order of the d...

Page 1045: ...0 0 392 U 128 A Y1 1 164 Y 16 U1 2 017 U 128 V0 1 596 V 128 V1 0 813 V 128 16 bits 16 bits A R G B A R G B A R G B A R G B A R G B A R G B Output pointer Output padding size data inserted Multiple of 32 bytes of data Buffer RAM 0 Display image Frame width 4 pixels in this sample figure Invalid data Converted data output order Output padding size 48 bytes 4 ARGB conversion with output padding 3 Col...

Page 1046: ...ize should be an integral multiple of 32 bytes for one line frame width input padding If there are deviations in the specified padding sizes for Y and U V operation is not guaranteed 2 Rearrangement YUV data is rearranged according to the format indicated in the display image of figure 20 3 When converting from YUV 4 2 0 to YUV 4 2 2 because the data quantity for UV is 1 2 that for Y the UV data i...

Page 1047: ...ersion data output order in the display image of figure 20 4 regardless of the output destination Converted data is output by the size 4 x the frame width specified by CLWR rounded up to an integral multiple of 32 bytes 5 Output data writing Because output data is transferred in 32 byte units one line of output data including output padding should be made an integral multiple of 32 bytes Padding d...

Page 1048: ...tep 3 Write the color conversion table to RAM 0 The CPU writes the color conversion table to RAM 0 Step 3 is not necessary in YUYV conversion mode it is only required in ARGB conversion mode Step 4 Write to the command FIFO The CPU writes commands to CLCF Four command parameters are required and should be written in succession in the following order 1 Data for writing Input Y pointer 2 Data for wr...

Page 1049: ... MCCF and does not accept the command for the next frame when four commands are already stored command FIFO full A judgment as to whether processing has ended can be made by using either an interrupt or the MC_END bit in GACISR Figure 20 6 illustrates the processing of one Y macroblock in forward macroblock processing After three rounds of processing for Y U and V have been done a processing end i...

Page 1050: ...xel processing get data for a block with one extra dot according to motion vector values Hardware performs processing as is even when in padding part Y0 128 bytes Y1 128 bytes Y2 128 bytes Y3 128 bytes U 128 bytes V 128 bytes Buffer RAM 1 8 Estimated image generation 7 IDCT data reading IDCT data Y 16 16 dot U 8 8 dot V 8 8 dot Y 16 16 dot U 8 8 dot V 8 8 dot Y 17 17 dot U 9 9 dot V 9 9 dot Y 16 1...

Page 1051: ...th Y padding mbcol 16 Output frame Y pointer value base point MCOYPR setting address mbrow Calculated from MCCF setting mbcol Calculated from MCCF setting width Calculated from MCWR setting Y padding Calculated from MCYPR setting Subsequently data for 16 dots 16 bytes is processed in succession U V output target address Calculation formula Output frame U point value base point mbrow 8 width 2 U pa...

Page 1052: ...address mbrow Calculated from MCCF setting mbcol Calculated from MCCF setting width Calculated from MCWR setting Y padding Calculated from MCYPR setting Subsequently data for 16 dots 16 bytes is processed in succession U V output target address Calculation formula Output frame U point value base point mbrow 8 n 1 width 2 U padding mbcol 8 Output frame U pointer value base point MCOUPR setting addr...

Page 1053: ...inter value base point MCPYPR setting address mbrow Calculated from MCCF setting mbcol Calculated from MCCF setting Recon_down Calculated from MCCF setting Recon_right Calculated from MCCF setting width Calculated from MCWR setting Y padding Calculated from MCYPR setting Depending on the motion vector value 16 dot data 16 bytes or 17 dot data 17 bytes is processed in succession Future frame Y poin...

Page 1054: ...F setting Recon_down Calculated from MCCF setting Recon_right Calculated from MCCF setting width Calculated from MCWR setting U padding Calculated from MCUVPR setting Depending on the motion vector value 8 dot data 8 bytes or 9 dot data 9 bytes is processed in succession Future frame U pointer address is calculated using a formula similar to that for the past frame V pointer address is calculated ...

Page 1055: ...ot data 16 bytes or 17 dot data 17 bytes is processed in succession Future frame Y pointer address is calculated using a formula similar to that for the past frame U V input comparison address Calculation formula Past frame U point value base point mbrow 8 Recon_down 2 1 n 1 width 2 U padding mbcol 8 Recon_right 2 1 Past frame U pointer value base point MCPUPR setting address mbrow Calculated from...

Page 1056: ... follows Correction case 1 right even down even A A 1 2 A digits below the decimal point are discarded no change Correction case 2 right even down odd A C 1 2 A digits below the decimal point are discarded Correction case 3 right odd down even A B 1 2 A digits below the decimal point are discarded Correction case 4 right odd down odd A D B C 2 4 A digits below the decimal point are discarded In bi...

Page 1057: ...ocks four luminance blocks and two chrominance blocks The above Y0 Y1 Y2 Y3 U V are CBP values of block positions in the following format CBP Blocks with YUV4 2 0 Y0 Y1 U Luminance Y Y2 Y3 Chrominance U V V Data for a CBP 0 block data invalid 9 bit saturation computation is performed for IDCT data read from RAM 1 256 x 255 The sign is discriminated using the uppermost bit bit 15 IDCT data reading ...

Page 1058: ...pointers and future frame Y U V pointers Step 3 Write IDCT data to RAM 1 The CPU writes IDCT data to RAM 1 Step 4 Write commands to FIFO The CPU writes commands to MCCF Eight command parameters are required and are written in sequence For details of settings refer to section 20 3 21 MC Command FIFO MCCF Step 5 Write the end command to command FIFO The CPU writes the end command to MCCF Step 7 Chec...

Page 1059: ...NEN MC processing ended CL_ERR interrupt CL_ERR or MC_ERR CL_EREN CL error occurred MC_ERR interrupt MC_EREN MC error occurred 20 6 Data Alignment The GDTA performs data alignment conversion of input data output data and RAM 0 1 data using an endian signal pin MD8 or using GDTA internal registers Table 20 11 shows the correspondence between data alignment conversion patterns and the settings of DR...

Page 1060: ...D5 D6 D7 D0 D1 D1 D3 D6 D7 D4 D5 D2 D3 D0 D1 D0 D1 D2 D3 D4 D5 D6 D7 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 63 5655 4847 ...

Page 1061: ...uld be used after releasing the module stop After a module is stopped the processing that was in progress and processing contents set in the CL MC command FIFO should be performed again 20 7 2 Regarding Deep Sleep Modes During GDTA operation deep sleep mode must not be entered If a transition is made to deep sleep mode during GDTA operation the GDTA processing is stopped and processing contents se...

Page 1062: ...L MC command FIFO are cleared When changing the frequency the frequency should be changed only after confirming that the CLSR EXE bit bit 3 in CLSR is 0 and the MC_CFA bits bits 10 to 8 in MCSR are 000 When resuming the processing the procedure described in section 20 4 1 3 CL Processing Procedure or section 20 4 2 2 MC Processing Procedure should be used after changing the frequency After a frequ...

Page 1063: ...er Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver Transmitter UART or Asynchronous Communication Interface Adapter ACIA There is a choice of 8 serial data transfer formats Data length 7 or 8 bits Stop bit length 1 or 2 bits Parity Even odd none Receive error detection Parity framing and overrun errors Break dete...

Page 1064: ...SCK to SCIF5_SCK pins Four interrupt sources There are four interrupt sources transmit FIFO data empty break receive FIFO data full and receive error that can issue requests independently The DMA controller DMAC can be activated to execute a data transfer by issuing a DMA transfer request in the event of a transmit FIFO data empty or receive FIFO data full interrupt When not in use the SCIF can be...

Page 1065: ...n reception control Clock Baud rate generator Peripheral bus External clock Bus interface 64 stages 64 stages Legend SCRSRn Receive shift register SCFRDRn Receive FIFO data register SCTSRn Transmit shift register SCFTDRn Transmit FIFO data register SCSMRn Serial mode register SCSCRn Serial control register SCFSRn Serial status register SCBRRn Bit rate register SCSPTRn Serial port register SCFCRn F...

Page 1066: ...SPTRW D7 D6 R Q D RTSIO C SPTRR SPTRW R Q D RTSDT C SCIF0_RTS Reset Reset Peripheral bus Modem control enable signal SCIF0_RTS signal Legend SPTRW Write to SCSPTR SPTRR Read from SCSPTR Note SCSPTR The SCIF0_RTS pin function is designated as modem control by the MCE bit in SCFCR Figure 21 2 SCIF0_RTS Pin ...

Page 1067: ...100 SPTRW D5 D4 R Q D CTSIO C SPTRR SPTRW R Q D CTSDT C SCIF0_CTS Legend SPTRW Write to SCSPTR SPTRR Read from SCSPTR Note The SCIF0_CTS pin function is designated as modem control by the MCE bit in SCFCR Modem control enable signal SCIF0_CTS signal Reset Reset Peripheral bus Figure 21 3 SCIF0_CTS Pin ...

Page 1068: ...ipheral bus Reset Reset Legend SPTRW Write to SCSPTR SPTRR Read from SCSPTR Note The SCIFn_SCK pin function is designated as internal clock output or external clock input by the C A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR SCIFn_SCK Figure 21 4 SCIFn_SCK Pin n 0 to 5 SPTRW D1 D0 R Q D SPB2IO C SPTRW R Q D SPB2DT C Legend SPTRW Write to SCSPTR SCIFn_TXD Transmit enable signal Serial transmi...

Page 1069: ...able only in channel 0 Table 21 1 Pin Configuration Pin Name Abbreviation I O Function Serial clock pin SCIF0_SCK to SCIF5_SCK I O Clock input output Receive data pin SCIF0_RXD to SCIF5_RXD Input Receive data input Transmit data pin SCIF0_TXD to SCIF5_TXD Output Transmit data output Modem control pin SCIF0_CTS I O Transmission enabled Modem control pin SCIF0_RTS I O Transmission request Note These...

Page 1070: ...1C H 1FEA 001C 16 Pck Receive FIFO data count register 0 SCRFDR0 R H FFEA 0020 H 1FEA 0020 16 Pck Serial port register 0 SCSPTR0 R W H FFEA 0024 H 1FEA 0024 16 Pck Line status register 0 SCLSR0 R W 2 H FFEA 0028 H 1FEA 0028 16 Pck Serial error register 0 SCRER0 R H FFEA 002C H 1FEA 002C 16 Pck 1 Serial mode register 1 SCSMR1 R W H FFEB 0000 H 1FEB 0000 16 Pck Bit rate register 1 SCBRR1 R W H FFEB ...

Page 1071: ...rt register 2 SCSPTR2 R W H FFEC 0024 H 1FEC 0024 16 Pck Line status register 2 SCLSR2 R W 2 H FFEC 0028 H 1FEC 0028 16 Pck Serial error register 2 SCRER2 R H FFEC 002C H 1FEC 002C 16 Pck 3 Serial mode register 3 SCSMR3 R W H FFED 0000 H 1FED 0000 16 Pck Bit rate register 3 SCBRR3 R W H FFED 0004 H 1FED 0004 8 Pck Serial control register 3 SCSCR3 R W H FFED 0008 H 1FED 0008 16 Pck Transmit FIFO da...

Page 1072: ...rt register 4 SCSPTR4 R W H FFEE 0024 H 1FEE 0024 16 Pck Line status register 4 SCLSR4 R W 2 H FFEE 0028 H 1FEE 0028 16 Pck Serial error register 4 SCRER4 R H FFEE 002C H 1FEE 002C 16 Pck 5 Serial mode register 1 SCSMR5 R W H FFEF 0000 H 1FEF 0000 16 Pck Bit rate register 5 SCBRR5 R W H FFEF 0004 H 1FEF 0004 8 Pck Serial control register 5 SCSCR5 R W H FFEF 0008 H 1FEF 0008 16 Pck Transmit FIFO da...

Page 1073: ...count register 0 SCRFDR0 H 0000 H 0000 Retained Retained Serial port register 0 SCSPTR0 H 0000 3 H 0000 3 Retained Retained Line status register 0 SCLSR0 H 0000 H 0000 Retained Retained Serial error register 0 SCRER0 H 0000 H 0000 Retained Retained 1 Serial mode register 1 SCSMR1 H 0000 H 0000 Retained Retained Bit rate register 1 SCBRR1 H FF H FF Retained Retained Serial control register 1 SCSCR1...

Page 1074: ...CRFDR2 H 0000 H 0000 Retained Retained Serial port register 2 SCSPTR2 H 0000 4 H 0000 4 Retained Retained Line status register 2 SCLSR2 H 0000 H 0000 Retained Retained Serial error register 2 SCRER2 H 0000 H 0000 Retained Retained 3 Serial mode register 3 SCSMR3 H 0000 H 0000 Retained Retained Bit rate register 3 SCBRR3 H FF H FF Retained Retained Serial control register 3 SCSCR3 H 0000 H 0000 Ret...

Page 1075: ...SCSPTR4 H 0000 4 H 0000 4 Retained Retained Line status register 4 SCLSR4 H 0000 H 0000 Retained Retained 5 Serial mode register 5 SCSMR5 H 0000 H 0000 Retained Retained Bit rate register 5 SCBRR5 H FF H FF Retained Retained Serial control register 5 SCSCR5 H 0000 H 0000 Retained Retained Transmit FIFO data register 5 SCFTDR5 Undefined Undefined Retained Retained Serial status register 5 SCFSR5 H ...

Page 1076: ... 7 BIt Initial value R W 21 3 2 Receive FIFO Data Register SCFRDR SCFRDR is an 8 bit FIFO register of 64 stages that stores received serial data When the SCIF has received one byte of serial data it transfers the received data from SCRSR to SCFRDR where it is stored and completes the receive operation SCRSR is then enabled for reception and consecutive receive operations can be performed until SCF...

Page 1077: ...FTDR to SCTSR and transmission started SCTSR cannot be directly read from and written to by the CPU 0 1 2 3 4 5 6 7 BIt Initial value R W 21 3 4 Transmit FIFO Data Register SCFTDR SCFTDR is an 8 bit FIFO register of 64 stages that stores data for serial transmission If SCTSR is empty when transmit data has been written to SCFTDR the SCIF transfers the transmit data written in SCFTDR to SCTSR and s...

Page 1078: ...R W R W R W R W R W R R R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 C A 0 R W Communication Mode Selects asynchronous mode or clocked synchronous mode as the SCIF operating mode 0 Asynchronous mode 1 Clocked synchronous mode 6 CHR 0 R W Character Length Selects 7 or 8 bits...

Page 1079: ... the O E bit setting is only valid when the PE bit is set to 1 enabling parity bit addition and checking In clocked synchronous mode or when parity addition and checking is disabled in asynchronous mode the O E bit setting is invalid 0 Even parity 1 Odd parity When even parity is set parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus ...

Page 1080: ...hould always be 0 1 0 CKS1 CKS0 0 0 R W R W Clock Select 1 and 0 These bits select the clock source for the on chip baud rate generator The clock source can be selected from Pck Pck 4 Pck 16 and Pck 64 according to the CKS1 and CKS0 settings For details on the relationship among clock sources bit rate register settings and baud rate see section 21 3 8 Bit Rate Register n SCBRR 00 Pck clock 01 Pck ...

Page 1081: ...on 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 TIE 0 R W Transmit Interrupt Enable Enables or disables transmit FIFO data empty interrupt TXI request generation when serial transmit data is transferred from SCFTDR to SCTSR the number of data bytes in SCFTDR falls to or below the transmit trigger setting count and the TDFE flag in SCFSR is set to 1 ...

Page 1082: ...t to 1 and a break interrupt BRI request when the BRK flag in SCFSR or the ORER flag in SCLSR is set to 1 0 Receive data full interrupt RXI request receive error interrupt ERI request and break interrupt BRI request disabled 1 Receive data full interrupt RXI request receive error interrupt ERI request and break interrupt BRI request enabled 5 TE 0 R W Transmit Enable Enables or disables the start ...

Page 1083: ...led 1 Reception enabled 3 3 REIE 0 R W Receive Error Interrupt Enable Enables or disables generation of receive error interrupt ERI and break interrupt BRI requests The REIE bit setting is valid only when the RIE bit is 0 Receive error interrupt ERI and break interrupt BRI requests can be cleared by reading 1 from ER and BRK in SCFSR or the ORER flag in SCLSR then clearing the flag to 0 or by clea...

Page 1084: ...IF_SCK pin functions as clock input 5 Clocked synchronous mode 0x Internal clock SCIF_SCK pin functions as synchronization clock output 1x External clock SCIF_SCK pin functions as synchronization clock input Legend x Don t care Notes 1 An RXI interrupt request can be canceled by reading 1 from the RDF or DR flag in SCFSR then clearing the flag to 0 or by clearing the RIE bit to 0 ERI and BRI inter...

Page 1085: ...the ER TEND TDFE BRK RDF and DR flags Also note that in order to clear these flags they must be read as 1 beforehand The FER flag and PER flag are read only flags and cannot be modified 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 DR RDF PER FER BRK TDFE TEND ER R W R W R R R W R W R W R W R R R R R R R R BIt Initial value R W Note Only 0 can be written to clear the flag B...

Page 1086: ... 1 1 A framing error or parity error occurred during reception Setting conditions When the SCIF checks whether the stop bit at the end of the receive data is 1 when reception ends and the stop bit is 0 2 When in reception the number of 1 bits in the receive data plus the parity bit does not match the parity setting even or odd specified by the O E bit in SCSMR 6 TEND 1 R W 1 Transmit End Indicates...

Page 1087: ...o SCFTDR after reading TDFE 1 and 0 is written to TDFE When transmit data exceeding the transmit trigger setting count is written to SCFTDR by the DMAC 1 The number of transmit data bytes in SCFTDR does not exceed the transmit trigger setting count Setting conditions Power on reset or manual reset When the number of SCFTDR transmit data bytes falls to or below the transmit trigger setting count as...

Page 1088: ...rom SCFRDR 1 There is a framing error that is to be read from SCFRDR Setting condition When there is a framing error in the data that is to be read next from SCFRDR 2 PER 0 R Parity Error Display In asynchronous mode indicates whether or not a parity error has been found in the data that is to be read next from SCFRDR 0 There is no parity error that is to be read from SCFRDR Clearing conditions Po...

Page 1089: ...eive data bytes in SCFRDR is less than the receive trigger setting count Clearing conditions Power on reset or manual reset When SCFRDR is read until the number of receive data bytes in SCFRDR falls below the receive trigger setting count after reading RDF 1 and 0 is written to RDF When SCFRDR is read by the DMAC until the number of receive data bytes in SCFRDR falls below the receive trigger sett...

Page 1090: ...o further data has arrived for at least 15 etu after the stop bit of the last data received 6 Legend etu Elementary time unit time for transfer of 1 bit Notes 1 Only 0 can be written to clear the flag 2 In 2 stop bit mode only the first stop bit is checked for a value of 1 the second stop bit is not checked 3 As SCFTDR is a 64 byte FIFO register the maximum number of bytes that can be written when...

Page 1091: ... setting is found from the following equation Asynchronous mode N 106 1 Pck 64 22n 1 B Clocked synchronous mode N 106 1 Pck 8 22n 1 B Where B Bit rate bit s N SCBRR setting for baud rate generator 0 N 255 Pck Peripheral module operating frequency MHz n 0 1 2 3 See table 21 3 for the relation between n and the baud rate generator input clock Table 21 3 SCSMR Settings SCSMR Setting n Baud Rate Gener...

Page 1092: ... R W R W R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 15 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 9 8 RSTRG2 1 RSTRG1 1 RSTRG0 1 0 0 0 R W R W R W SCIF_RTS Output Active Trigger The SCIF_RTS signal becomes high when the number of receive data stored in SCFRDR exceeds the trigger setting count shown below 000 63 001 1...

Page 1093: ...a Count Register Clear Clears the transmit data count in the transmit FIFO data count register to 0 0 The FIFO data count not cleared 4 1 The FIFO data count cleared to 0 1 RFCL 0 R W Receive FIFO Data Count Register Clear Clears the receive data count in the receive FIFO data count register to 0 0 The FIFO data count not cleared 4 1 The FIFO data count cleared 0 LOOP 0 R W Loopback Test Internall...

Page 1094: ... 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T0 T1 T2 T3 T4 T5 T6 R R R R R R R R R R R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 15 to 7 All 0 R Reserved These bits are always read as 0 The write value should always be 0 6 to 0 T6 to T0 All 0 R These bits show the number of untransmitted data bytes in SCFTDR A value of H 00 indicates that there is no trans...

Page 1095: ...U 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R0 R1 R2 R3 R4 R5 R6 R R R R R R R R R R R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 15 to 7 All 0 R Reserved These bits are always read as 0 The write value should always be 0 6 to 0 R6 to R0 All 0 R These bits show the number of receive data bytes in SCFRDR A value of H 00 indicates that ther...

Page 1096: ...nitialized in the module standby state Note that when reading data via a serial port pin in the SCIF the peripheral clock value from 2 cycles before is read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 SPB2 DT SPB2 IO SCK DT SCK IO CTS DT CTS IO RTS DT RTS IO R W R W R W R W R W R W R W R W R R R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 15 to 8 Al...

Page 1097: ...output the value set by the CTSDT bit the MCE bit in SCFCR should be cleared to 0 0 CTSDT bit value is not output to SCIF_CTS pin 1 CTSDT bit value is output to SCIF_CTS pin 4 CTSDT R W Serial Port SCIF_CTS Port Data Specifies the serial port SCIF_CTS pin input output data Input or output is specified by the CTSIO bit In output mode the CTSDT bit value is output to the SCIF_CTS pin The SCIF_CTS pi...

Page 1098: ...al port SCIF_TXD pin output condition When actually setting the SCIF_TXD pin as a port output pin to output the value set by the SPB2DT bit the TE bit in SCSCR should be cleared to 0 0 SPB2DT bit value is not output to the SCIF_TXD pin 1 SPB2DT bit value is output to the SCIF_TXD pin 0 SPB2DT R W Serial Port Break Data Specifies the serial port SCIF_RXD pin input data and SCIF_TXD pin output data ...

Page 1099: ... error occurred during reception causing abnormal termination 0 Reception in progress or reception has ended normally 2 Clearing conditions Power on reset or manual reset When 0 is written to ORER after reading ORER 1 1 An overrun error occurred during reception 3 Setting condition When the next serial reception is completed while SCFRDR receives 64 byte data SCFRDR is full Notes 1 Only 0 can be w...

Page 1100: ... bits indicate the number of data bytes in which a parity error occurred in the receive data stored in SCFRDR After the ER bit in SCFSR is set the value indicated by bits PER5 to PER0 is the number of data bytes in which a parity error occurred If all 64 bytes of receive data in SCFRDR have parity errors the value indicated by bits PER5 to PER0 is 0 7 6 All 0 R Reserved These bits are always read ...

Page 1101: ...lock source is determined by the combination of the C A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR as shown in table 21 5 Asynchronous Mode Data length Choice of 7 or 8 bits LSB first for data transmission and reception Choice of parity addition and addition of 1 or 2 stop bits the combination of these parameters determines the transfer format and character length Detection of framing errors...

Page 1102: ...ud rate generator clock and a serial clock is output to external devices When SCIF_SCK pin input is selected The on chip baud rate generator is not used and the SCIF operates on the input serial clock Table 21 4 SCSMR Settings for Serial Transfer Format Selection SCSMR Settings SCIF Transfer Format Bit 7 C A Bit 6 CHR Bit 5 PE Bit 3 STOP Mode Data Length Parity Bit Stop Bit Length 0 1 bit 0 1 No 2...

Page 1103: ... Settings Bit 7 C A Bit 1 CKE1 Bit 0 CKE0 Mode Clock Source SCIF_SCK Pin Function 0 SCIF does not use SCIF_SCK pin 0 1 Internal Outputs clock with frequency of 16 times the bit rate 0 0 1 1 Asynchronous mode External Inputs clock with frequency of 16 times the bit rate 1 0 0 1 Internal Outputs synchronization clock 1 0 Clocked synchronous mode External Inputs synchronization clock 1 ...

Page 1104: ...onous serial communication the transmission line is usually held in the mark state high level The SCIF monitors the transmission line and when it goes to the space state low level recognizes a start bit and starts serial communication One character in serial communication consists of a start bit low level followed by transmit receive data LSB first from the lowest bit a parity bit high or low leve...

Page 1105: ...ng to the SCSMR settings Table 21 6 Serial Transfer Formats Asynchronous Mode SCSMR Settings Serial Transfer Format and Frame Length CHR PE STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 S 8 bit data STOP 0 0 1 S 8 bit data STOP STOP 0 1 0 S 8 bit data P STOP 0 1 1 S 8 bit data P STOP STOP 1 0 0 S 7 bit data STOP 1 0 1 S 7 bit data STOP STOP 1 1 0 S 7 bit data P STOP 1 1 1 S 7 bit data P STOP STOP Legend S...

Page 1106: ...ng data it is necessary to clear the TE and RE bits in SCSCR to 0 then initialize the SCIF as described below When the operating mode or transfer format etc is changed the TE and RE bits must be cleared to 0 before making the change using the following procedure 1 When the TE bit is cleared to 0 SCTSR is initialized Note that clearing the TE and RE bits to 0 does not change the contents of SCFSR S...

Page 1107: ...CL bits to 0 Set TE and RE bits in SCSCR to 1 and set TIE RIE and REIE bits End of initialization Wait No Yes Set the clock selection in SCSCR Be sure to clear bits TIE RIE TE and RE to 0 Set the data transfer format in SCSMR Write a value corresponding to the bit rate into SCBRR Not necessary if an external clock is used Wait at least one bit interval then set the TE bit or RE bit in SCSCR to 1 A...

Page 1108: ...d transmit data write Read SCFSR and check that the TDFE flag is set to 1 then write transmit data to SCFTDR and clear the TDFE and TEND flags to 0 The number of transmit data bytes that can be written is 64 transmit trigger setting count 2 Serial transmission continuation procedure To continue serial transmission read 1 from the TDFE flag to confirm that writing is possible then write data to SCF...

Page 1109: ...bit in SCSCR is set to 1 at this time a transmit FIFO data empty interrupt TXI request is generated The serial transmit data is sent from the SCIF_TXD pin in the following order a Start bit One 0 bit is output b Transmit data 8 bit or 7 bit data is output in LSB first order c Parity bit One parity bit even or odd parity is output A format in which a parity bit is not output can also be selected d ...

Page 1110: ...One frame Figure 21 10 Example of SCIF Transmission Operation Example with 8 Bit Data Parity One Stop Bit 4 When modem control is enabled transmission can be stopped and restarted in accordance with the SCIF_CTS input value When SCIF_CTS is set to 1 during transmission the SCIF goes to the mark state after transmission of one frame When SCIF_CTS is set to 0 the next transmit data is output startin...

Page 1111: ... flags in SCFSR and the ORER flag in SCLSR to identify any error perform the appropriate error handling then clear the DR ER BRK and ORER flags to 0 In the case of a framing error a break can also be detected by reading the value of the SCIF_RXD pin 2 SCIF status check and receive data read Read SCFSR and check that RDF 1 then read the receive data in SCFRDR read 1 from the RDF flag and then clear...

Page 1112: ...No No No 1 Whether a framing error or parity error has occurred in the receive data that is to be read from SCFRDR can be ascertained from the FER and PER bits in SCFSR 2 When a break signal is received receive data H 00 is not transferred to SCFRDR However note that the last data in SCFRDR is H 00 and the break data in which a framing error occurred is stored When a break handling is completed an...

Page 1113: ...ot set If b c and d checks are passed the receive data is stored in SCFRDR Note Reception continues even when a parity error or framing error occurs 4 If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1 a receive FIFO data full interrupt RXI request is generated If the RIE bit or REIE bit in SCSCR is set to 1 when the ER flag changes to 1 a receive error interrupt ERI request ...

Page 1114: ...e than the SCIF_RTS output active trigger count The SCIF_RTS output active trigger value is specified by bits 10 to 8 in SCFCR For details see section 21 3 9 FIFO Control Register n SCFCR In addition SCIF_RTS is also 1 when the RE bit in SCSCR is cleared to 0 Figure 21 14 shows an example of the operation when modem control is used D0 D1 D2 D7 0 1 1 0 0 Serial data SCIF_RXD SCIF_RTS Start bit Pari...

Page 1115: ...hows the general format for clocked synchronous communication One unit of transfer data character or frame Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don t care Don t care LSB MSB Synchronization clock Serial data Note High except in continuous transfer Figure 21 15 Data Format in Clocked Synchronous Communication In clocked synchronous serial communication data on the communication line is o...

Page 1116: ...of one character and when no transfer is performed the clock is fixed high When an internal clock is selected in a receive operation only as long as the RE bit in SCSCR is set to 1 clock pulses are output until the number of receive data bytes in the receive FIFO data register reaches the receive trigger count 3 SCIF Initialization Clocked Synchronous Mode Before transmitting and receiving data it...

Page 1117: ...ialization almost ends Be sure to clear the TIE RIE TE and RE bits to 0 Set the CKE1 and CKE0 bits Set the data transfer format in SCSMR Write a value corresponding to the bit rate into SCBRR This is not necessary if an external clock is used Wait at least one bit interval after this write before moving to the next step Set the external pins to be used Set SCIF_RXD input for reception and SCIF_TXD...

Page 1118: ...sion 1 SCIF initialization See Sample SCIF Initialization Flowchart in figure 21 16 2 SCIF status check and transmit data write Read SCFSR and check that the TDFE flag is set to 1 then write transmit data to SCFTDR and clear the TDFE flag to 0 The transition of the TDFE flag from 0 to 1 can also be identified by a TXI interrupt 3 Serial transmission continuation procedure To continue serial transm...

Page 1119: ... is selected the SCIF outputs eight synchronization clock pulses for each data When the external clock is selected data is output in synchronization with the input clock The serial transmit data is sent from the SCIF_TXD pin in LSB first order 3 The SCIF checks the SCFTDR transmit data at the timing for sending the last bit If data is present the data is transferred from SCFTDR to SCTSR and then s...

Page 1120: ...ception 1 SCIF initialization See Sample SCIF Initialization Flowchart in figure 21 16 2 Receive error handling Read the ORER flag in SCLSR to identify any error perform the appropriate error handling then clear the ORER flag to 0 Transmission reception cannot be resumed while the ORER flag is set to 1 3 SCIF status check and receive data read Read SCFSR and check that RDF 1 then read the receive ...

Page 1121: ...The receive data is stored in SCRSR in LSB to MSB order After receiving the data the SCIF checks whether the receive data can be transferred from SCRSR to SCFRDR If this check is passed the receive data is stored in SCFRDR If an overrun error is detected in the error check reception cannot continue 3 If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1 a receive FIFO data full interr...

Page 1122: ... Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RXI interrupt request One frame Data read from SCFRDR and RDF flag cleared to 0 by RXI interrupt handler LSB RDF Serial data SCIF_RXD Synchronization clock ORER MSB RXI interrupt request BRI interrupt request by overrun error Figure 21 20 Example of SCIF Reception Operation ...

Page 1123: ...0 The transition of the TDFE flag from 0 to 1 can also be identified by a TXI interrupt 3 Receive error handling Read the ORER flag in SCLSR to identify any error perform the appropriate error handling then clear the ORER flag to 0 Reception cannot be resumed while the ORER flag is set to 1 4 SCIF status check and receive data read Read SCFSR and check that RDF 1 then read the receive data in SCFR...

Page 1124: ... perform data transfer If the RDF or DR flag in SCFSR is set to 1 when an RXI interrupt is enabled by the RIE bit an RXI interrupt request and a receive FIFO data full request for DMA transfer are generated If the RDF or DR flag is set to 1 when an RXI interrupt is disabled by the RIE bit only a receive FIFO data full request for DMA transfer is generated A receive FIFO data full request can activ...

Page 1125: ... ERI Interrupt initiated by receive error flag ER Not possible High RXI Interrupt initiated by receive FIFO data full flag RDF or receive data ready flag DR Possible BRI Interrupt initiated by break flag BRK or overrun error flag ORER Not possible TXI Interrupt initiated by transmit FIFO data empty flag TDFE Possible Low Note An RXI interrupt by setting of the DR flag is available only in asynchro...

Page 1126: ...and the RDF Flag The RDF flag in SCFSR is set when the number of receive data bytes in SCFRDR has become equal to or greater than the receive trigger count set by bits RTRG1 and RTRG0 in SCFCR After RDF is set receive data equivalent to the trigger count can be read from SCFRDR allowing efficient continuous reception However if the number of data bytes read in SCFRDR is equal to or greater than th...

Page 1127: ... low level and then clear the TE bit to 0 halting transmission When the TE bit is cleared to 0 the transmitter is initialized regardless of the current transmission state and 0 is output from the SCIF_TXD pin 5 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode In asynchronous mode the SCIF operates on a base clock with frequency of 16 times the bit rate In reception the SCIF syn...

Page 1128: ...2N L 0 5 F N 1 F 100 1 M Receive margin N Ratio of bit rate to clock N 16 D Clock duty D 0 to 1 0 L Frame length L 9 to 12 F Absolute value of clock rate deviation From equation 1 if F 0 and D 0 5 the reception margin is 46 875 as given by formula 2 When D 0 5 and F 0 M 0 5 1 2 16 100 46 875 2 However this is a theoretical value A reasonable margin to allow in system designs is 20 to 30 ...

Page 1129: ...t data 16 bit data and 16 bit stereo audio data MSB first for data transmission and reception Supports up to 48 kHz sampling rate Synchronization by either frame synchronization pulse or left right channel switch Supports CODEC control data interface Connectable to linear audio A Law or μ Law CODEC chip Supports both master and slave modes Serial clock An external pin input or peripheral clock Pck...

Page 1130: ... the SIOF P S Transmit FIFO 32 bits 16 stages Pck 1 nMCLK SIOF_MCLK SIOF_SCK SIOF_SYNC SIOF_TXD SIOF_RXD SIOF interrupt request Bus interface Control registers Baud rate generator Timing control Transmit control data Peripheral bus Receive FIFO 32 bits 16 stages Receive control data S P Figure 22 1 Block Diagram of SIOF ...

Page 1131: ... Serial clock I O Serial clock pin common to transmission reception SIOF_SYNC Frame synchronous signal I O Frame synchronous signal common to transmission reception SIOF_TXD Transmit data Output Transmit data pin SIOF_RXD Receive data Input Receive data pin Note A pin group to be used can be selected according to the setting of PFC For details see Peripheral Module Select Register 1 and Peripheral...

Page 1132: ...R W H FFE2 0004 H 1FE2 0004 16 Pck Receive data assign register SIRDAR R W H FFE2 0006 H 1FE2 0006 16 Pck Control data assign register SICDAR R W H FFE2 0008 H 1FE2 0008 16 Pck Control register SICTR R W H FFE2 000C H 1FE2 000C 16 Pck FIFO control register SIFCTR R W H FFE2 0010 H 1FE2 0010 16 Pck Status register SISTR R W H FFE2 0014 H 1FE2 0014 16 Pck Interrupt enable register SIIER R W H FFE2 0...

Page 1133: ... H 0000 Retained Retained Control data assign register SICDAR H 0000 H 0000 Retained Retained Control register SICTR H 0000 H 0000 Retained Retained FIFO control register SIFCTR H 1000 H 1000 Retained Retained Status register SISTR H 0000 H 0000 Retained Retained Interrupt enable register SIIER H 0000 H 0000 Retained Retained Transmit data register SITDR H xxxx xxxx H xxxx xxxx Retained Retained R...

Page 1134: ... Slave mode 2 10 Master mode 1 11 Master mode 2 13 SYNCAT 0 R W SIOF_SYNC Pin Valid Timing Indicates the position of the SIOF_SYNC signal to be output as a synchronous pulse 0 At the start bit data of frame 1 At the last bit data of slot 12 REDG 0 R W Receive Data Sampling Edge 0 The SIOF_RXD signal is sampled at the falling edge of SIOF_SCK 1 The SIOF_RXD signal is sampled at the rising edge of S...

Page 1135: ...F_SYNC signal is output as synchronous pulse 0 Active high 1 Active low 4 SYNCDL 0 R W Data Pin Bit Delay for SIOF_SYNC Pin This bit is valid when the SIOF_SYNC signal is output as synchronous pulse In slave mode specify one bit delay 0 No bit delay 1 1 bit delay 3 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 Table 22 4 shows the operation in each transf...

Page 1136: ...the SIOF_SCK pin 14 FSE 0 R W Frame Synchronous Signal Output Enable This bit is valid in master mode 0 Disables the SIOF_SYNC output outputs low level 1 Enables the SIOF_SYNC output If this bit is set to 1 the SIOF initializes the frame counter and initiates the operation 13 to 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 TXE 0 R W Transmit Enable 0 Dis...

Page 1137: ...ting of the RFWM bit in SIFCTR This bit is initialized by a receive reset 7 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 TXRST 0 R W Transmit Reset 0 Does not reset transmit operation 1 Resets transmit operation This bit setting becomes valid immediately For details on initialization see section 22 4 7 5 Transmit Receive Reset This bit is automatically...

Page 1138: ...6 SITDL 15 0 Undefined W Left Channel Transmit Data These bits specify data to be output from the SIOF_TXD pin as left channel data The position of the left channel data in the transmit frame depends on the value set in the TDLA bit in SITDAR These bits are valid when the TDLE bit in SITDAR is set to 1 15 to 0 SITDR 15 0 Undefined W Right Channel Transmit Data These bits specify data to be output ...

Page 1139: ...it Bit Name Initial Value R W Description 31 to 16 SIRDL 15 0 Undefined R Left Channel Receive Data These bits store data received from the SIOF_RXD pin as left channel data The position of the left channel data in the receive frame depends on the value set in the RDLA bit in SIRDAR These bits are valid when the RDLE bit in SIRDAR is set to 1 15 to 0 SIRDR 15 0 Undefined R Right Channel Receive Da...

Page 1140: ... R W R W R W R W R W BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 SITC1 15 0 BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 16 SITC0 15 0 H 0000 R W Control Channel 0 Transmit Data These bits specify data to be output from the SIOF_TXD pin as control channel 0 transmit data The position of the control channel 0 data in the transmit or receive frame depends on...

Page 1141: ... 14 SIRC1 15 0 BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 16 SIRC0 15 0 Undefined R W Control Channel 0 Receive Data These bits store data received from the SIOF_RXD pin as control channel 0 receive data The position of the control channel 0 data in the transmit or receive frame depends on the value set the CD0A bit in SICDAR These bits are valid when the CD0E bit in SI...

Page 1142: ...ransmit Control Data Ready 0 Indicates that writing to SITCR is disabled 1 Indicates that writing to SITCR is enabled If SITCR is written to when this bit is cleared to 0 SITCR is overwritten to and the previous contents of SITCR are not output from the SIOF_TXD pin This bit is valid when the TXE bit in SITCR is set to 1 This bit indicates the SIOF state If SITCR is written to this bit is automati...

Page 1143: ... bit are satisfied the SIOF again indicates 1 for this bit This bit is valid when the TXE bit in SICTR is 1 This bit indicates a state if the size of empty space in the transmit FIFO is less than the size specified by the TFWM bit in SIFCTR this bit is automatically cleared to 0 To enable the issuance of this interrupt source set the TDREQE bit in SIIER to 1 11 0 R Reserved This bit is always read...

Page 1144: ... of valid space in the receive FIFO exceeds the size specified by the RFWM bit in SIFCTR A receive data transfer request is issued when the valid space in the receive FIFO exceeds the value specified by the RFWM bit in SIFCTR When using receive data transfer through the DMAC this bit is always cleared by one DMAC access After DMAC access when conditions for setting this bit are satisfied this bit ...

Page 1145: ... is written to this bit the contents are cleared Writing 0 to this bit is invalid To enable the issuance of this interrupt source set the SAERRE bit in SIIER to 1 4 FSERR 0 R W Frame Synchronization Error 0 Indicates that no frame synchronization error occurs 1 Indicates that a frame synchronization error occurs A frame synchronization error occurs when the next frame synchronization timing appear...

Page 1146: ...hen 1 is written to this bit the contents are cleared Writing 0 to this bit is invalid To enable the issuance of this interrupt source set the TFOVFE bit in SIIER to 1 2 TFUDF 0 R W Transmit FIFO Underflow 0 Indicates that no transmit FIFO underflow occurs 1 Indicates that a transmit FIFO underflow occurs A transmit FIFO underflow means that loading for transmission has occurred when the transmit ...

Page 1147: ...en 1 is written to this bit the contents are cleared Writing 0 to this bit is invalid To enable the issuance of this interrupt source set the RFUDFE bit in SIIER is set to 1 0 RFOVF 0 R W Receive FIFO Overflow 0 Indicates that no receive FIFO overflow occurs 1 Indicates a receive FIFO overflow occurs A receive FIFO overflow means that writing has occurred when the receive FIFO is full When a recei...

Page 1148: ...fer Request Enable Transmits an interrupt as a CPU interrupt or a DMA transfer request when the TDREQE bit is 1 0 Used as a CPU interrupt 1 Used as a DMA transfer request to the DMAC 14 TCRDYE 0 R W Transmit Control Data Ready Enable 0 Disables interrupts due to transmit control data ready 1 Enables interrupts due to transmit control data ready 13 TFEMPE 0 R W Transmit FIFO Empty Enable 0 Disables...

Page 1149: ...AERRE 0 R W Slot Assign Error Enable 0 Disables interrupts due to slot assign error 1 Enables interrupts due to slot assign error 4 FSERRE 0 R W Frame Synchronization Error Enable 0 Disables interrupts due to frame synchronization error 1 Enables interrupts due to frame synchronization error 3 TFOVFE 0 R W Transmit FIFO Overflow Enable 0 Disables interrupts due to transmit FIFO overflow 1 Enables ...

Page 1150: ...ty 001 Setting prohibited 010 Setting prohibited 011 Setting prohibited 100 Issue a transfer request when 12 or more stages of the transmit FIFO are empty 101 Issue a transfer request when 8 or more stages of the transmit FIFO are empty 110 Issue a transfer request when 4 or more stages of the transmit FIFO are empty 111 Issue a transfer request when 1 or more stages of transmit FIFO are empty Set...

Page 1151: ...ive FIFO are valid 101 Issue a transfer request when 8 or more stages of the receive FIFO are valid 110 Issue a transfer request when 12 or more stages of the receive FIFO are valid 111 Issue a transfer request when 16 stages of the receive FIFO are valid A transfer request to the receive FIFO is issued by the RDREQE bit in SISTR The receive FIFO is always used as 16 stages of the FIFO regardless ...

Page 1152: ...ck Source Selection The master clock is the clock source input to the baud rate generator 0 Uses the input signal of the SIOF_MCLK pin as the master clock 1 Uses a peripheral clock Pck as the master clock 14 MSIMM 1 R W Master Clock Direct Selection 0 Uses the output clock of the baud rate generator as the serial clock 1 Uses the master clock itself as the serial clock 13 0 R Reserved This bit is ...

Page 1153: ... 1 1 Note This setting is valid only when the bits BRPS4 to BRPS0 are set to B 00001 22 3 11 Transmit Data Assign Register SITDAR SITDAR is a 16 bit readable writable register that specifies the position of the transmit data in a frame 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDRA 3 0 TLREP TDRE TDLA 3 0 TDLE R W R W R W R W R R R W R W R W R W R W R W R R R W R BIt In...

Page 1154: ...t channel data transmission 6 TLREP 0 R W Transmit Left Channel Repeat 0 Transmits data specified in the SITDR bit in SITDR as right channel data 1 Repeatedly transmits data specified in the SITDL bit in SITDR as right channel data This bit setting is valid when the TDRE bit is set to 1 When this bit is set to 1 the SITDR settings are ignored 5 4 All 0 R Reserved These bits are always read as 0 Th...

Page 1155: ...hese bits are always read as 0 The write value should always be 0 11 to 8 RDLA 3 0 0000 R W Receive Left Channel Data Assigns 3 to 0 These bits specify the position of left channel data in a receive frame as B 0000 0 to B 1110 14 1111 Setting prohibited Receive data for the left channel is stored in the SIRDL bit in SIRDR 7 RDRE 0 R W Receive Right Channel Data Enable 0 Disables right channel data...

Page 1156: ...ion of control channel 0 data 1 Enables transmission and reception of control channel 0 data 14 to 12 All 0 R Reserved These bits are always read as 0 The write value should always be 0 11 to 8 CD0A 3 0 0000 R W Control Channel 0 Data Assigns 3 to 0 These bits specify the position of control channel 0 data in a receive or transmit frame as B 0000 0 to B 1110 14 1111 Setting prohibited Transmit dat...

Page 1157: ...00 R W Control Channel 1 Data Assigns 3 to 0 These bits specify the position of control channel 1 data in a receive or transmit frame as B 0000 0 to B 1110 14 1111 Setting prohibited Transmit data for the control channel 1 data is specified in the SITD1 bit in SITCR Receive data for the control channel 1 data is stored in the SIRD1 bit in SIRCR ...

Page 1158: ...ion ratio from 1 to 1 32 with the BRPS4 to BRSP0 bits in SISCR and divider that can select the division ratio from 1 1 2 1 4 1 8 1 16 and 1 32 The division ratio of the baud rate generator ranges from 1 to 1 1024 of the product of the division ratios of the prescaler and the divider When the master clock is not divided by the baud rate generator the division ratio is 1 set the MSIMM bit in SISCR t...

Page 1159: ...6 144 MHz 256 bits 2 048 MHz 11 289 MHz 12 289 MHz Note Control data formats are valid when the FL bits are set to 1xxx x Don t care 22 4 2 Serial Timing 1 SIOF_SYNC The SIOF_SYNC is a frame synchronous signal Depending on the transfer mode it has the following two functions Synchronous pulse 1 bit width pulse indicating the start of the frame L R 1 2 frame width pulse indicating the left channel ...

Page 1160: ...e No delay Rch Start bit of right channel data 1 2 frame length b L R a Synchronous pulse Figure 22 3 Serial Data Synchronization Timing 2 Transmit Receive Timing The SIOF_TXD transmit timing and SIOF_RXD receive timing relative to the SIOF_SCK can be set as the sampling timing in the following two ways The transmit receive timing is set by the REDG bit in SIMDR Falling edge sampling Rising edge s...

Page 1161: ...16 bit stereo data Control data Transfer of 16 bit data uses the transmit receive control register as interface 1 Transfer Mode As shown in table 22 6 the SIOF supports the following four transfer modes The transfer mode can be specified by the TRMD1 and TRMD0 bits in SIMDR Table 22 6 Serial Transfer Modes TRMD1 and TRMD0 Transfer Mode SIOF_SYNC Bit Delay Control Data 00 Slave mode 1 Synchronous p...

Page 1162: ... 0111 8 128 8 bit monaural data 10xx 16 16 16 bit monaural data 1100 16 32 16 bit monaural stereo data 1101 16 64 16 bit monaural stereo data 1110 16 128 16 bit monaural stereo data 1111 16 256 16 bit monaural stereo data Note x Don t care 3 Slot Position The SIOF can specify the position of transmit data receive data and control data in a frame common to transmission and reception by slot numbers...

Page 1163: ...23 16 15 8 7 0 31 24 23 16 15 8 7 0 L channel data Data Data Data R channel data Figure 22 5 Transmit Receive Data Bit Alignment Note In the figure only the shaded areas are transmitted or received as valid data Therefore access must be made in byte units for 8 bit data and in word units for 16 bit data Data in not shaded areas is not transmitted or received Monaural or stereo can be specified for...

Page 1164: ...e audio mode is not supported in receive data To execute 8 bit monaural transmission or reception use the left channel 2 Control Data Control data is written to or read from by the following registers Transmit control data write SITCR 32 bit access Receive control data read SIRCR 32 bit access Figure 22 6 shows the control data and bit alignment in SITCR and SIRCR b Control data Two channels a Con...

Page 1165: ...sition Control by secondary FS Control data is valid when data length is specified as 16 bits 1 Control by Slot Position Master Mode 1 and Slave Mode 1 Control data is transferred for all frames transmitted or received by the SIOF by specifying the slot position of control data This method can be used in both SIOF master and slave modes Figure 22 7 shows an example of the control data interface ti...

Page 1166: ...s to 0 To execute control data transmission send transmit data of LSB 1 the SIOF forcibly set to 1 by writing SITCDR The CODEC outputs the secondary FS The SIOF transmits or receives stores in SIRCDR control data data specified by SITCDR synchronously with the secondary FS Figure 22 8 shows an example of the control data interface timing by the secondary FS TRMD 1 0 01 Specifications TDLE 1 RDLE 1...

Page 1167: ...eceive interrupt source The request conditions for FIFO transmit or receive can be specified individually The request conditions for the FIFO transmit and receive are specified by the TFWM2 to TFWM0 bits and the bits RFWM2 to RFWM0 in SIFCTR respectively Tables 22 11 and 22 12 summarize the conditions to issue transmit request and those to issue receive request respectively Table 22 11 Conditions ...

Page 1168: ...O is always sixteen even if the data area or empty area exceeds the FIFO size Accordingly an overflow error or underflow error occurs if data area or empty area exceeds sixteen FIFO stages The FIFO transmit or receive request is canceled when the above condition is not satisfied even if the FIFO is not empty or full 3 Number of FIFOs The number of FIFO stages used in transmission and reception is ...

Page 1169: ...ngs SIOF Operation Set operation start for baud rate generator Output serial clock Set transmit data Set to disable transmission End transmission Set the start for frame synchronous signal output and enable transmission Output frame synchronous signal and issue transmit transfer request Transmit Note When interrupts due to transmit data underflow are enabled after setting the no 6 transmit data th...

Page 1170: ... generator Output serial clock Read receive data Receive Set to disable reception End reception Set the start for frame synchronous signal output and enable reception Output frame synchronous signal Issue receive transfer request according to the receive FIFO threshold value Set SIMDR SISCR SITDAR SIRDAR SICDAR SITCR and SIFCTR Set the FSE and RXE bits in SICTR to 1 Store SIOF_RXD receive data in ...

Page 1171: ...chart SIOF Settings SIOF Operation Set to enable transmission Issue transmit transfer request to enable transmission when frame synchronous signal is input Set transmit data Transmit SITDR from SIOF_TXD synchronously with SIOF_SYNC 5 Transmit Set to disable transmission End transmission Set SIMDR SISCR SITDAR SIRDAR SICDAR SITCR and SIFCTR Set operating mode serial clock slot positions for transmi...

Page 1172: ...F Operation Set to enable reception Enable reception when the frame synchronous signal is input Read receive data Store SIOF_RXD receive data in SIRDR synchronously with SIOF_SYNC 5 Issue receive transfer request according to the receive FIFO threshold value Set to disable reception End reception Receive Set SIMDR SISCR SITDAR SIRDAR SICDAR SITCR and SIFCTR Set operating mode serial clock slot pos...

Page 1173: ...it in SICTR Table 22 13 shows the details on initialization upon transmit or receive reset Table 22 13 Transmit and Receive Reset Type Objects to be Initialized Transmit reset Stop transmitting from SIOF_TXD output according to the value set in the TXDIZ bit Transmit FIFO write pointer TCRDY TFEMP and TDREQ bits in SISTR TXE bit in SICTR Receive reset Stop receiving from SIOF_RXD Receive FIFO read...

Page 1174: ...l register is ready to be written to 6 Control RCRDY Receive control data ready The receive control data register stores valid data 7 Error TFUDF Transmit FIFO underflow Serial data transmit timing has arrived while the transmit FIFO is empty 8 TFOVF Transmit FIFO overflow Write to the transmit FIFO is performed while the transmit FIFO is full 9 RFOVF Receive FIFO overflow Serial data is received ...

Page 1175: ...owing operations Transmit FIFO underflow TFUDF The immediately preceding transmit data is again transmitted Transmit FIFO overflow TFOVF The contents of the transmit FIFO are protected and the write operation causing the overflow is ignored Receive FIFO overflow RFOVF Data causing the overflow is discarded and lost Receive FIFO underflow RFUDF An undefined value is output on the bus Frame synchron...

Page 1176: ...ethod falling edge sampling slot No 0 used for transmit and receive data a frame length 8 bits Slot No 0 TRMD 1 0 00 or 10 TDLE 1 RDLE 1 CD0E 0 REDG 0 TDLA 3 0 0000 RDLA 3 0 0000 CD0A 3 0 0000 FL 3 0 0000 frame length 8 bits TDRE 0 RDRE 0 CD1E 0 TDRA 3 0 0000 RDRA 3 0 0000 CD1A 3 0 0000 Specifications 1 frame 1 bit delay SIOF_SCK SIOF_RXD SIOF_TXD SIOF_SYNC SYNCDL 1 L channel data Figure 22 13 Tra...

Page 1177: ...bit delay SIOF_SCK SIOF_RXD SIOF_TXD SIOF_SYNC SYNCDL 1 L channel data Figure 22 14 Transmit and Receive Timing 8 Bit Monaural Data 2 3 16 bit Monaural Data Synchronous pulse method falling edge sampling slot No 0 used for transmit and receive data and frame length 64 bits TRMD 1 0 00 or 10 TDLE 1 RDLE 1 CD0E 0 REDG 0 TDLA 3 0 0000 RDLA 3 0 0000 CD0A 3 0 0000 FL 3 0 1101 frame length 64 bits TDRE ...

Page 1178: ...a Figure 22 16 Transmit and Receive Timing 16 Bit Stereo Data 1 5 16 bit Stereo Data 2 L R method rising edge sampling slot No 0 used for left channel transmit data slot No 1 used for left channel receive data slot No 2 used for right channel transmit data slot No 3 used for right channel receive data and frame length 64 bits TRMD 1 0 11 TDLE 1 RDLE 1 CD0E 0 REDG 1 TDLA 3 0 0000 RDLA 3 0 0001 CD0A...

Page 1179: ..._TXD SIOF_SYNC L channel data R channel data Control channel 0 Control channel 1 Figure 22 18 Transmit and Receive Timing 16 Bit Stereo Data 3 7 16 bit Stereo Data 4 Synchronous pulse method falling edge sampling slot No 0 used for left channel data slot No 2 used for right channel data slot No 1 used for control channel 0 data slot No 3 used for control channel 1 data and frame length 128 bits TR...

Page 1180: ...slot No 3 used for control channel 1 data and frame length 128 bits TRMD 1 0 00 or 10 TDLE 1 RDLE 1 CD0E 1 REDG 0 TDLA 3 0 0000 RDLA 3 0 0000 CD0A 3 0 0010 FL 3 0 1110 frame length 128 bits TDRE 1 RDRE 1 CD1E 1 TDRA 3 0 0001 RDRA 3 0 0001 CD1A 3 0 0011 Slot No 0 Slot No 1 Slot No 2 Slot No 3 Slot No 4 Slot No 5 Slot No 6 Slot No 7 Specifications 1 frame SIOF_SCK SIOF_RXD SIOF_TXD SIOF_SYNC L chann...

Page 1181: ...k division strategy allows a wide range of bit rates to be supported The programmable clock control logic allows setting for two different transmit protocols and accommodates transmit and receive functions on either edge of the serial clock Error detection logic is provided for warning of the receive buffer overflow The HSPI has a facility to generate the chip select signal to slave modules when c...

Page 1182: ... diagram of the HSPI HSPI_CLK HSPI_TX HSPI_RX LSB MSB SPCR HSPI_CS SPSR SPSCR SPTBR SPRBR Pck In FIFO mode Peripheral bus Transmit FIFO Receive FIFO Eight entries for each LSB MSB Bus interface Registers System control Shift register Clock division Polarity selection SCK generator Figure 23 1 Block Diagram of HSPI ...

Page 1183: ... Input Receive data input Chip select pin HSPI_CS I O Chip select 23 3 Register Descriptions Table 23 2 Register Configuration 1 Register Name Abbrev R W P4 Address Area 7 Address Size Sync Clock Control register SPCR R W H FFE5 0000 H 1FE5 0000 32 Pck Status register SPSR R H FFE5 0004 H 1FE5 0004 32 Pck System control register SPSCR R W H FFE5 0008 H 1FE5 0008 32 Pck Transmit buffer register SPT...

Page 1184: ...Retained Retained Retained Status register SPSR H xxxx xx20 1 H xxxx xx20 1 Retained Retained H xxxx xxxx 2 System control register SPSCR H 0000 0040 H 0000 0040 Retained Retained Retained Transmit buffer register SPTBR H 0000 0000 H 0000 0000 Retained Retained Retained Receive buffer register SPRBR H 0000 0000 H 0000 0000 Retained Retained Retained Notes 1 x represents an undefined value 2 x repr...

Page 1185: ...alue should always be 0 7 FBS 0 R W First Bit Start Controls the timing relationship between each bit of transferred data and the serial clock 0 The first bit transmitted from the HSPI module is set up such that it can be sampled by the receiving device at the first edge of HSPI_CLK specified by the register after the HSPI_CS pin goes low Similarly the first received bit is sampled at the first ed...

Page 1186: ...create an intermediate frequency which is further divided to create the serial clock for master mode 4 to 0 CLKC4 to CLKC0 All 0 R W Clock Division Count These bits determine the frequency dividing ratio that is used to obtain the serial clock from the intermediate clock 00000 1 intermediate frequency cycle Serial clock frequency Intermediate frequency 2 00001 2 Intermediate frequency cycles Seria...

Page 1187: ...ts are ignored and the HSPI synchronizes to the externally supplied serial clock The maximum value of the external serial clock that the module can operate with is Pck 8 If any of the FBS CLKP IDIV or CLKC bit values are changed the HSPI will undergo a software reset When IPIV or CLKC is specified or changed the internal serial clock generation counter is reset In this case data transmit receive s...

Page 1188: ... R R R R R R R R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 1 0 0 1 0 0 TXFL TXFN RXFL RXOW RXOO RXEM RXHA RXFU TXEM TXHA TXFU R R R R W R W R R R R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 11 Undefined R Reserved These bits are always read as an undefined value The write value should always be 0 10 TXFU 0 R Transmit ...

Page 1189: ...de The flag is set to 1 when the receive FIFO reaches the halfway point that is it has four bytes of data and free space for four bytes of data This flag is cleared to 0 when the receive data is read from receive FIFO and the data stored in the FIFO becomes less than four bytes halfway point If RXHA 1 and RHIE 1 an interrupt is generated 5 RXEM 1 R Receive FIFO Empty Flag This status flag is enabl...

Page 1190: ... loaded into the SPRBR in the end of a serial bus transfer This bit is cleared to 0 by reading SPRBR 1 TXFN 0 R Transmit Complete Status Flag This status flag indicates that the last transmission has been completed It is set to 1 when SPTBR is ready to accept data from the peripheral bus This bit is cleared to 0 by writing data to SPTBR If TXFN 1 and TFIE 1 an interrupt is generated 0 TXFL 0 R Tra...

Page 1191: ...R W R W R W R W R W R W R W R W R W R W R W R W R R Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 14 All 0 R Reserved These bits are always read as an undefined value The write value should always be 0 13 TEIE 0 R W Transmit FIFO Empty Interrupt Enable 0 Transmit FIFO empty interrupt disabled 1 Transmit FIFO empty interrupt enabled 12 THIE 0 R W Transmit FIFO Halfway Inter...

Page 1192: ... R W LSB MSB First Control 0 Data is transmitted and received most significant bit MSB first 1 Data is transmitted and received least significant bit LSB first 6 CSV 1 R W Chip Select Value Controls the value output as the chip select signal when the HSPI is a master and manual generation of the chip select signal has been selected 0 Chip select output is low 1 Chip select output is high 5 CSA 0 R...

Page 1193: ...R SPTBR is a 32 bit readable writable register that stores data to be transmitted 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 R R R R R R R R R R R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 TD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Descriptio...

Page 1194: ... R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 RD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 8 All 0 R Reserved These bits are always read as an undefined value The write value should always be 0 7 to 0 RD All 0 R Receive Data Data is transferred from the shift register to these ...

Page 1195: ...ither the falling or rising edge of HSPI_CLK and samples data from the slave at the opposite edge The data transfer between the master and slave is completed when the transmit complete status flag TXFN in SPSR is set to 1 This flag should be used to identify when an HSPI transfer event byte transmitted and byte received has occurred even in the case where the HSPI module is used to receive data on...

Page 1196: ...Write bytes into the transmit FIFO via SPTBR If more than eight bytes are to be transmitted enable the transmit FIFO halfway interrupt to keep track of the FIFO level as data is transmitted 3 Respond to the transmit FIFO halfway interrupt when it occurs by writing more data to the transmit FIFO and reading data from the receive FIFO via SPRBR 4 When all of the transmit data has been written into t...

Page 1197: ...conditions when FBS 1 continuous transfer It can be seen that if CLKP in SPCR is 0 transmit data is shifted at the falling edge of HSPI_CLK and receive data is sampled at the rising edge of HSPI_CLK The opposite is true when CLKP 1 Data transfer cycle HSPI_CLK CLKP 0 HSPI_CLK CLKP 1 1 4 3 2 8 7 6 5 HSPI_TX MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB HSPI_RX HSPI_CS Figure 23 3 Timing Conditions when F...

Page 1198: ...3 2 8 7 6 5 MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB HSPI_TX HSPI_RX HSPI_CX Figure 23 5 Timing Conditions when FBS 1 HSPI_CLK CLKP 0 HSPI_CLK CLKP 1 1 8 2 9 16 10 HSPI_TX MSB 6 LSB MSB 6 LSB MSB 6 LSB MSB 6 LSB HSPI_RX HSPI_CS Data transfer cycle Figure 23 6 Timing Conditions when FBS 1 Continuous Transfer The asterisk in the figures shows 0 or 1 ...

Page 1199: ...ng erroneous data 23 4 5 Clock Polarity and Transmit Control SPCR also allows the user to define the shift timing for transmit data and polarity The FBS bit in SPCR allows selection between two different transfer formats When CSA of SPSR is 0 the MSB or LSB is valid at the falling edge of HSPI_CS The CLKP bit in SPCR allows for control of the polarity select block shown in figure 23 1 which select...

Page 1200: ... and an interrupt occurs 23 4 8 Low Power Consumption and Clock Synchronization The HSPI operates in synchronization with the bus clock Module standby mode is enabled disabled by the MSTP2 bit of the CPG module standby control register 0 MSTPCR0 Take the following steps to enter module standby mode 1 Check that all data transfers have been completed The transmit buffer or FIFO must be empty and th...

Page 1201: ...of a command commands extended by the secure multimedia card Secure MMC and additional commands can be supported in the future within the range of combinations of currently defined command types response types 24 1 Features The MMCIF has the following features Supports a subset of the MultiMediaCard System Specification Version 3 1 Supports MMC mode Incorporates 64 data transfer FIFOs of 16 bits S...

Page 1202: ...sponse reception control Interrupt control MMC mode control Card clock generator Port Figure 24 1 Block Diagram of MMCIF 24 2 Input Output Pins Table 24 1 summarizes the pins of the MMCIF Table 24 1 Pin Configuration Pin Name I O Function MMCCLK Input Output Card clock output MMCCMD Input Output Command output response input MMCDAT Input Output Data input output Note For insertion detachment of a ...

Page 1203: ...egister 0 INTCR0 R W H FFE6 000C H 1FE6 000C 8 Pck Interrupt control register 1 INTCR1 R W H FFE6 000D H 1FE6 000D 8 Pck Interrupt status register 0 INTSTR0 R W H FFE6 000E H 1FE6 000E 8 Pck Interrupt status register 1 INTSTR1 R W H FFE6 000F H 1FE6 000F 8 Pck Transfer clock control register CLKON R W H FFE6 0010 H 1FE6 0010 8 Pck Command timeout control register CTOCR R W H FFE6 0011 H 1FE6 0011 ...

Page 1204: ...E6 002B 8 Pck Response register 12 RSPR12 R W H FFE6 002C H 1FE6 002C 8 Pck Response register 13 RSPR13 R W H FFE6 002D H 1FE6 002D 8 Pck Response register 14 RSPR14 R W H FFE6 002E H 1FE6 002E 8 Pck Response register 15 RSPR15 R W H FFE6 002F H 1FE6 002F 8 Pck Response register 16 RSPR16 R W H FFE6 0030 H 1FE6 0030 8 Pck CRC status register RSPRD R W H FFE6 0031 H 1FE6 0031 8 Pck Data timeout reg...

Page 1205: ... 0 INTCR0 H 00 H 00 Retained Retained Interrupt control register 1 INTCR1 H 00 H 00 Retained Retained Interrupt status register 0 INTSTR0 H 00 H 00 Retained Retained Interrupt status register 1 INTSTR1 H 00 H 00 Retained Retained Transfer clock control register CLKON H 00 H 00 Retained Retained Command timeout control register CTOCR H 01 H 01 Retained Retained Transfer byte number count register T...

Page 1206: ...RSPR11 H 00 H 00 Retained Retained Response register 12 RSPR12 H 00 H 00 Retained Retained Response register 13 RSPR13 H 00 H 00 Retained Retained Response register 14 RSPR14 H 00 H 00 Retained Retained Response register 15 RSPR15 H 00 H 00 Retained Retained Response register 16 RSPR16 H 00 H 00 Retained Retained CRC status register RSPRD H 00 H 00 Retained Retained Data timeout register DTOUTR H ...

Page 1207: ...it 0 in CMDR5 Table 24 4 CMDR Configuration Register Contents Operation CMDR0 to CMDR4 Command argument Write command arguments CMDR5 CRC and End bit Setting of CRC is unnecessary automatic calculation End bit is fixed to 1 and its setting is unnecessary automatic setting The read value is 0 1 CMDR0 to CMDR4 Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 command argument 0 0 0 0 R W R W R W R W R W...

Page 1208: ...cessary Analysis transfer of receive data of prior command if necessary Preparation of transmit data of the next command if necessary Setting of CMDTYR RSPTYR TBCR and TBNCR Setting of CMDR0 to CMDR4 The CMDR0 to CMDR4 CMDTYR RSPTYR TBCR and TBNCR registers should not be changed until command transmission has ended during the CWRE flag in CSTR has been set to 1 or until command transmit end interr...

Page 1209: ...tion Control Register OPCR OPCR is an 8 bit readable writable register that aborts command operation and suspends or continues data transfer Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W DATAEN RD_ CONTI CMD OFF R R W R W R R R R Bit Bit Name Initial Value R W Description 7 CMDOFF 0 R W Command Off Aborts all command operations MMCIF command sequence when 1 is written after a command i...

Page 1210: ...ta reception Note Do not write to this bit out of the write enable period 4 DATAEN 0 R W Data Enable Starts a write data transmission by a command with write data This bit is cleared automatically when 1 is written and the MMCIF received the DATAEN command Resumes write data transmission while the sequence has been halted by FIFO empty or termination of block writing in multiple block write Write ...

Page 1211: ...he MMCIF side When using the auto mode for a pre defined multiple block transfer the setting of the RD_CONTI bit or the DATAEN bit between blocks can be omitted 24 3 4 Card Status Register CSTR CSTR indicates the MMCIF status during command sequence execution Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R DTBUSY DTBUSY _TU REQ BUSY CWRE FIFO_ FULL FIFO_ EMPTY R R R R R R R Bit Bit Name Init...

Page 1212: ... command can be written 1 The CMDR command is waiting for transmission or is being transmitted If a new command is written a malfunction will result 3 DTBUSY 0 R Data Busy Indicates command execution status Indicates that the card is in the busy state after the command sequence of a command without data transfer which includes the busy state in the response or a command with write data has been en...

Page 1213: ...s enable or disable interrupts 1 INTCR0 Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W FEIE FFIE DRPIE DTIE CRPIE CMDIE DBS YIE R W R W R W R W R W R W R W BTIE Bit Bit Name Initial Value R W Description 7 FEIE 0 R W FIFO Empty Interrupt Flag Setting Enable 0 Disables FIFO empty interrupt disables FEI flag setting 1 Enables FIFO empty interrupt enables FEI flag setting 6 FFIE 0 R W FIFO...

Page 1214: ...isables CRPI flag setting 1 Enables command response receive end interrupt enables CRPI flag setting 2 CMDIE 0 R W Command Transmit End Interrupt Flag Setting Enable 0 Disables command transmit end interrupt disables CMDI flag setting 1 Enables command transmit end interrupt enables CMDI flag setting 1 DBSYIE 0 R W Data Busy End Interrupt Flag Setting Enable 0 Disables data busy end interrupt disa...

Page 1215: ...AT interrupt 1 Enables FSTAT interrupt 4 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 CRCERIE 0 R W CRC Error Interrupt Flag Setting Enable 0 Disables CRC error interrupt disables CRCERI flag setting 1 Enables CRC error interrupt enables CRCERI flag setting 1 DTERIE 0 R W Data Timeout Error Interrupt Flag Setting Enable 0 Disables data timeout error inter...

Page 1216: ... Q3E Bit Bit Name Initial Value R W Description 7 INTRQ3E 0 R W FRDY Interrupt Enable 0 Disables FRDY interrupt 1 Enables FRDY interrupt 6 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 FRDYIE 0 R W FIFO Ready Interrupt Enable 0 Disables FIFO ready interrupt disables FRDY flag setting 1 Enables FIFO ready interrupt enables FRDY flag setting ...

Page 1217: ... Name Initial Value R W Description Interrupt output 7 FEI 0 R W FIFO Empty Interrupt Flag 0 No interrupt Clearing condition Write 0 after reading FEI 1 Writing 1 is invalid 1 Interrupt requested Setting condition When FIFO becomes empty while FEIE 1 and data is being transmitted when the FIFO_EMPTY bit in CSTR is set FSTAT 6 FFI 0 R W FIFO Full Interrupt Flag 0 No interrupt Clearing condition Wri...

Page 1218: ...RC status is received while DRPIE 1 TRAN 4 DTI 0 R W Data Transfer End Interrupt Flag 0 No interrupt Clearing condition Write 0 after reading DTI 1 Writing 1 is invalid 1 Interrupt requested Setting condition When the number of bytes of data transfer specified in TBCR ends while DTIE 1 TRAN 3 CRPI 0 R W Command Response Receive End Interrupt Flag 0 No interrupt Clearing condition Write 0 after rea...

Page 1219: ...When the CWRE bit in CSTR is cleared TRAN 1 DBSYI 0 R W Data Busy End Interrupt Flag 0 No interrupt Clearing condition Write 0 after reading DBSYI 1 Writing 1 is invalid 1 Interrupt requested Setting condition When data busy state is canceled while DBSYIE 1 When the DTBUSY bit in CSTR is cleared TRAN 0 BTI 0 R W Multiple block Transfer End Flag 0 No interrupt Clearing condition Write 0 after readi...

Page 1220: ...lag 0 No interrupt Clearing condition Write 0 after reading CRCERI 1 Writing 1 is invalid 1 Interrupt requested Setting condition When a CRC error for command response or receive data or a CRC status error for transmit data response is detected while CRCERIE 1 For the command response CRC is checked when the RTY4 in RSPTYR is enabled ERR 1 DTERI 0 R W Data Timeout Error Interrupt Flag 0 No interru...

Page 1221: ...Name Initial Value R W Description Interrupt output 0 CTERI 0 R W Command Timeout Error Interrupt Flag 0 No interrupt Clearing condition Write 0 after reading CTERI 1 Writing 1 is invalid 1 Interrupt requested Setting condition When a command timeout error specified in TOCR occurs while CTERIE 1 ERR ...

Page 1222: ... Ready Flag Regardless of set values of DMAEN and FRDYIE this bit is read as 0 when FIFO data amount matches the asserting condition set in DMACR 2 0 and otherwise read as 1 0 FRDYI 0 R W FIFO Ready Interrupt Flag 0 No interrupt Clearing condition Write 0 after reading FRDYI 1 Writing 1 is invalid 1 Interrupt requested Setting condition When remained FIFO data does not match the assert condition s...

Page 1223: ...LK pin 1 Outputs the transfer clock from the MMCCLK pin 6 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 2 1 0 CSEL3 CSEL2 CSEL1 CSEL0 0 0 0 0 R W R W R W R W Transfer Clock Frequency Select 0000 Reserved 0001 Uses the 1 2 divided peripheral clock Pck as a transfer clock 0010 Uses the 1 4 divided peripheral clock as a transfer clock 0011 Uses the 1 8 div...

Page 1224: ... number specified in CTOCR When the CTERIE bit in INTCR1 is set to 1 the CTERI flag in INTSTR1 is set As CTOUTC continues counting transfer clock the CTERI flag setting condition is repeatedly generated To perform command timeout error handling the command sequence should be aborted by setting the CMDOFF bit to 1 and then the CTERI flag should be cleared to prevent extra interrupt generation Bit I...

Page 1225: ...ta block This setting is ignored by the stream transfer command Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R C2 C3 C1 C0 R R R R W R W R W R W Bit Bit Name Initial Value R W Description 7 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 2 1 0 CS3 CS2 CS1 CS0 0 0 0 0 R W R W R W R W Transfer Data Block Size Four or more bytes should be set before...

Page 1226: ...ing a command by setting the CMDSTART bit in CMDSTRT to 1 and ends when all necessary data transmission reception and response reception have been completed The multimedia card supports the data busy state such that only the specific command is accepted to write erase data to from the flash memory in the card during command sequence execution and after command sequence execution has ended The data...

Page 1227: ...to TY2 to all 0s Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R TY4 TY3 TY2 TY1 TY0 R W R W R W R W R W R W R W TY6 TY5 Bit Bit Name Initial Value R W Description 7 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 6 TY6 0 R W Type 6 Specifies a predefined multiple block transaction TY 1 0 should be set to 01 or 10 When using the command set to this ...

Page 1228: ...en it is aborted by the CMD12 command 1 0 TY1 TY0 0 0 R W R W Types 1 and 0 These bits specify the existence and direction of transfer data 00 A command without data transfer 01 A command with read data reception 10 A command with write data transmission 11 Setting prohibited 24 3 12 Response Type Register RSPTYR RSPTYR is an 8 bit readable writable register that specifies command format in conjun...

Page 1229: ...command with data busy 4 RTY4 0 R W Response Type 4 Specifies that the command response CRC is checked through CRC7 Bits RTY2 to RTY0 should be set to 100 0 Does not check CRC through CRC7 1 Checks CRC through CRC7 3 0 R Reserved These bits are always read as 0 The write value should always be 0 2 1 0 RTY2 RTY1 RTY0 0 0 0 R W R W R W Response Types 2 to 0 These bits specify the number of command r...

Page 1230: ...LATIVE_ADDR R1 00 4 100 CMD4 SET_DSR 00 000 CMD7 SELECT DESELECT_CARD R1b 00 1 4 100 CMD9 SEND_CSD R2 00 4 101 CMD10 SEND_CID R2 00 4 101 CMD11 READ_DAT_UNTIL_STOP R1 1 01 4 100 CMD12 STOP_TRANSMISSION R1b 1 00 1 4 100 CMD13 SEND_STATUS R1 00 4 100 CMD15 GO_INACTIVE_STATE 00 000 CMD16 SET_BLOCKLEN R1 00 4 100 CMD17 READ_SINGLE_BLOCK R1 3 01 4 100 CMD18 READ_MULTIPLE_BLOCK R1 2 2 01 4 100 CMD20 WRI...

Page 1231: ...0 4 100 CMD40 GO_IRQ_STATE R5 00 4 100 CMD42 LOCK_UNLOCK R1b 10 1 4 100 CMD55 APP_CMD R1 00 4 100 CMD56 GEN_CMD R1b 5 1 4 100 Notes A blank Means value 0 1 These commands are not supported by MMCA Ver3 1 and later cards 2 Set bits TY6 and TY2 B 10 when the number of blocks for transfer is set in advance Set bits TY6 and TY2 B 01 when the number of blocks for transfer is not set 3 Set this bit when...

Page 1232: ...er in the TBNCR The value of TBNCR is decremented by one as each block transfer is executed and the command sequence ends when the TBNCR value equals 0 TBNCR Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 15 to 0 TBNCR All 0 R W Transfer Block Numb...

Page 1233: ... number of command response bytes and valid RSPR register Table 24 6 Correspondence between Command Response Byte Number and RSPR MMC Mode Response RSPR registers 6 bytes R1 R1b R3 R4 R5 17 bytes R2 RSPR0 1st byte RSPR1 2nd byte RSPR2 3rd byte RSPR3 4th byte RSPR4 5th byte RSPR5 6th byte RSPR6 7th byte RSPR7 8th byte RSPR8 9th byte RSPR9 10th byte RSPR10 11th byte RSPR11 1st byte 12th byte RSPR12 ...

Page 1234: ...trary value RSPR0 to RSPR16 comprise a continuous 17 byte shift register 2 RSPRD Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R RSPRD R R R W R W R W R W R W Bit Bit Name Initial Value R W Description 7 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 to 0 RSPRD 00000 R W CRC status Clearing condition When writing any value to these bits cleared t...

Page 1235: ...aler output and enters the data timeout error states when the number of prescaler outputs reaches the number specified in DTOUTR When the DTERIE bit in INTCR1 is set to 1 the DTERI flag in INTSTR1 is set As DTOUTC continues counting prescaler output the DTERI flag setting condition is repeatedly generated To perform data timeout error handling the command sequence should be aborted by setting the ...

Page 1236: ...order Word access and byte access can be done in random order However DR address 1 cannot be accessed in bytes The following shows examples of DR access When data is written to DR in the following steps 1 to 4 the transmit data is stored in the FIFO as shown in figure 24 2 1 Write word data H 0123 to DR 2 Write byte data H 45 to DR 3 Write word data H 6789 to DR 4 Write byte data H AB to DR When t...

Page 1237: ...2 DR Access Example 24 3 17 FIFO Pointer Clear Register FIFOCLR The FIFO write read pointer is cleared by writing an arbitrary value to FIFOCLR Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 W FIFOCLR W W W W W W W Bit Bit Name Initial Value R W Description 7 to 0 FIFOCLR H 00 W The FIFO pointer is cleared by writing an arbitrary value to this register ...

Page 1238: ...MA request signal 6 AUTO 0 R W Auto Mode for pre define multiple block transfer using DMA transfer 0 Disable auto mode 1 Enable auto mode 5 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 1 0 SET2 SET1 SET0 0 0 0 R W R W R W DMA Request Signal Assert Condition Sets DMA request signal assert condition 000 Not output 001 FIFO remained data is 1 4 or less of...

Page 1239: ...nd data is transmitted received via the MMCDAT pin In this mode the next command can be issued while data is being transmitted received This feature is efficient for multiple block or stream transfer In this case the next command is the CMD12 command which aborts the current command sequence In MMC mode broadcast commands that simultaneously issue commands to multiple cards are supported After inf...

Page 1240: ... CMD2 Each card compares it s CID and data on the MMCCMD and if they are different the card aborts the CID output Only one card in which the CID can be entirely output enters the acknowledge state When the R2 response is necessary set CTOCR to H 01 A relative address RCA is given to the card in the acknowledge state by CMD3 The card to which the RCA is given enters the standby state By repeating C...

Page 1241: ...settings to issue the command Set the CMDSTART bit in CMDSTRT to 1 to start command transmission MMCCMD must be kept driven until the end bit output is completed The end of the command sequence is detected by poling the BUSY flag in CSTR or by the command transmit end interrupt CMDI MMCCLK MMCCMD MMCDAT CMDSTRT CMDSTART INTSTR0 CMDI CSTR CWRE BUSY REQ Input output pins Command output 48 bits Comma...

Page 1242: ...peration commands include a number of commands that do not include data transfer Such commands execute the desired data transfer using command arguments and command responses For a command that is related to time consuming processing such as flash memory write erase the card indicates the data busy state via the MMCDAT Figures 24 5 and 24 6 show examples of the command sequence for commands withou...

Page 1243: ...d through the data busy end interrupt DBSYI Write the CMDOFF bit to 1 if a CRC error CRCERI or a command timeout error CTERI occurs The MMCCMD and MMCDAT pins go to the high impedance state when the MMCIF and the MMC card do not drive the bus and the input level of these pins is high because they are pulled up internally MMCCLK MMCCMD MMCDAT CMDSTRT CMDSTART INTSTR0 CMDI CSTR BUSY CWRE REQ CRPI DB...

Page 1244: ...EQ CRPI DBSYI DTBUSY_TU DTBUSY Input output pins Command output 48 bits Command transmission started Command response reception Command transmission period Command sequence execution period Response reception completed Data busy period Busy state ends Busy state Figure 24 6 Example of Command Sequence for Commands without Data Transfer with Data Busy State ...

Page 1245: ...and type in CMDTYR Set command response type in RSPTYR Write 1 to CMDSTRT Yes No CRCERI interrupt detected Yes No CRPI interrupt detected Yes No R1b response Yes No DTBUSY detected Yes No Yes No DBSYI interrupt detected End of command sequence CTERI interrupt detected Write 1 to CMDOFF Figure 24 7 Example of Operational Flow for Commands without Data Transfer ...

Page 1246: ...t be received correctly Therefore to receive the command response correctly the command sequence must be continued set the RD_CONT bit to 1 until the command response reception ends Figures 24 8 to 24 11 show examples of the command sequence for commands with read data Figures 24 12 to 24 14 show the operational flows for commands with read data Make settings to issue the command and clear FIFO Se...

Page 1247: ...TERI occurs in the command response reception Clear the FIFO by writing the CMDOFF bit to 1 when CRC error CRCERI and data timeout error DTERI occurs in the read data reception MMCCLK MMCCMD MMCDAT CMDSTRT CMDSTART INTSTR0 CMDI CMDOFF CSTR CWRE BUSY REQ CRPI DTI FFI FIFO_FULL CMD17 READ_SINGLE_BLOCK OPCR RD_CONTI Input output pins Command Command response Read data Command transmission started Sin...

Page 1248: ...NGLE_BLOCK OPCR RD_CONTI Input output pins Transfer clock transmission halted Transfer clock transmission resumed Command response Command Block data reception suspended Read data Read data Block data reception resumed Reading data from FIFO Single block read command execution sequence Command transmission started Figure 24 9 Example of Command Sequence for Commands with Read Data Block Size FIFO ...

Page 1249: ...2 STOP_TRANSMISSION OPCR RD_CONTI Input output pins Transfer clock transmission halted Transfer clock transmission resumed Read data Block data reception ended Multiblock read command execution sequence Stop command execution sequence Command Command Command transmission started Command response Read data Read data Command response Figure 24 10 Example of Command Sequence for Commands with Read Da...

Page 1250: ...a reception resumed Data reception ended Read data from FIFO Stream read command execution sequence MMCCLK MMCCMD MMCDAT CMDSTRT CMDSTART INTSTR0 CMDI CMDOFF CSTR CWRE BUSY REQ CRPI DTI FFI FIFO_FULL OPCR RD_CONTI Command Read data Read data Read data Command response Command Command response Command transmission started Transfer clock transmission halted Data reception suspended Figure 24 11 Exam...

Page 1251: ...ormal Yes No End of command sequence CTERI interrupt detected Yes No FFI interrupt detected Set CMDOFF to 1 Read data from FIFO Set RD_CONTI to 1 Read data from FIFO No Yes DTERI interrupt detected No Yes CRCERI interrupt detected No Yes Legend Len Block length bytes Cap FIFO size bytes n FFI Number of FIFO full interrupts FFI from the start of read sequence DTERI interrupt detected Yes No DTI int...

Page 1252: ...ead response register Execute CMD18 Set CMDR then CMDSTRT Set the block size in TBCR No Yes CRCERI interrupt detected Yes No CMD16 normal end Yes No CRPI interrupt detected Yes No Response status normal Yes No CTERI interrupt detected 1 2 Figure 24 13 Example of Operational Flow for Commands with Read Data 1 Open ended Multiple Block Transfer ...

Page 1253: ...gend Len Block length bytes Cap FIFO size bytes n FFI Number of FIFO full interrupts FFI from the start of read sequence n DTI Number of data transfer end interrupts DTI from the start of read sequence DTERI interrupt detected Yes No Read next block Yes No DTI interrupt detected Yes No Cap Len 1 n DTI Cap n FFI Set CMDOFF to 1 Execute CMD12 Set CMDOFF to 1 Execute CMD12 Clear FIFO 1 2 Figure 24 13...

Page 1254: ...DR then CMDSTRT Set the block size in TBCR No Yes CRCERI interrupt detected Yes No CMD16 normal end Execute CMD23 Set the number of blocks for transfer TBNCR Yes No CMD23 normal end Yes No CRPI interrupt detected Yes No Response status normal Yes No CTERI interrupt detected 1 2 Figure 24 13 Example of Operational Flow for Commands with Read Data 3 Pre defined Multiple Block Transfer ...

Page 1255: ...ap FIFO size bytes n FFI Number of FIFO full interrupts FFI from the start of read sequence n DTI Number of data transfer end interrupts DTI from the start of read sequence DTERI interrupt detected Yes No BTI interrupt detected Yes No DTI interrupt detected Yes No Cap Len 1 n DTI Cap n FFI Yes No TBNCR value n DTI Set CMDOFF to 1 Execute CMD12 Read data from FIFO Set CMDOFF to 1 Clear FIFO 1 2 Fig...

Page 1256: ... detected Yes No Response status normal ended Yes No End of command sequence CTERI interrupt detected Yes No FFI interrupt detected Set the CMDOFF to 1 Read data from FIFO Set the RD_CONTI to 1 No Yes DTERI interrupt detected Yes No Data read completed Set the CMDOFF to 1 Execute CMD12 Execute CMD12 Read data from FIFO Set the CMDOFF to 1 Clear FIFO Figure 24 14 Example of Operational Flow for Com...

Page 1257: ...nd sequence to continue Figures 24 15 to 24 18 show examples of the command sequence for commands with write data Figures 24 19 to 24 21 show the operational flows for commands with write data Make settings to issue a command and clear FIFO Set the CMDSTART bit in CMDSTRT to 1 to start command transmission MMCCMD must be kept driven until the end bit output is completed Command transmission comple...

Page 1258: ... busy state the end of the data busy state is detected by the data busy end interrupt DBSYI Write the CMDOFF bit to 1 if a CRC error CRCERI or a command timeout error CTERI occurs in the command response reception Write the CMDOFF bit to 1 if a CRC error CRCERI or a data timeout error DTERI occurs in the write data transmission Note In a write to the card by stream transfer the MMCIF continues dat...

Page 1259: ...WRE BUSY DTBUSY DTBUSY_TU REQ CRPI DTI DBSYI FEI FIFO_EMPTY CMD24 WRITE_SINGLE_BLOCK OPCR DATAEN DRPI INTSTR0 Input output pins Command Command response Command transmission started Single block write command execution sequence Write data Status Busy Figure 24 15 Example of Command Sequence for Commands with Write Data Block Size FIFO Size ...

Page 1260: ... WRITE_SINGLE_BLOCK OPCR DATAEN Input output pins Command Command response Command transmission started Busy Transfer clock transmission halted Transfer clock transmission resumed Block data transmission suspended Writing data to FIFO Write data Write data Block data transmission resumed Single block write command execution sequence Figure 24 16 Example of Command Sequence for Commands with Write ...

Page 1261: ...25 WRITE_MULTIPE_BLOCK CMD12 STOP_TRANSMISSION OPCR DATAEN Input output pins Write data Write data Write data Status Status Block data transmission started Block data reception ended Next block data transmission started Stop command execution sequence Command Command response Command Command response Command transmission started Figure 24 17 Example of Command Sequence for Commands with Write Data...

Page 1262: ...se Command Stop command execution sequence Busy Transfer clock trans mission halted Transfer clock trans mission halted Transfer clock transmission resumed Transfer clock transmission resumed Writing data to FIFO Data transmission suspended Data transmission suspended Data transmission resumed Data transmission ended Stream write command execution sequence Command response Command transmission sta...

Page 1263: ...normal Yes No End of command sequence CTERI interrupt detected Set CMDOFF to 1 Write data to FIFO Set DATAEN to 1 Yes DTBUSY detected Yes DBSYI interrupt detected No Yes CRCERI interrupt detected No Yes Legend Len Block length bytes Cap FIFO size bytes n FEI Number of FIFO empty interrupts FEI from the start of read sequence DTERI interrupt detected Yes No DRPI interrupt detected Yes Cap n FEI Len...

Page 1264: ...ad response register Execute CMD25 Set CMDR then CMDSTRT Set the block size in TBCR No Yes CRCERI interrupt detected Yes No CMD16 normal end Yes No CRPI interrupt detected Yes No Response status normal Yes No CTERI interrupt detected 1 2 Figure 24 20 1 Example of Operational Flow for Commands with Write Data Open ended Multiple Block Transfer ...

Page 1265: ...ata if block size FIFO size Len Block length bytes Cap FIFO size bytes n FEI Number of FIFO empty interrupts FEI from the start of read sequence n DRPI Number of data response interrupts DRPI from the start of write sequence Legend DTERI interrupt detected Yes No DRPI interrupt detected Yes Cap n FEI Len 1 n DTI Len No No Yes DTI interrupt detected No Yes FEI interrupt detected No Set CMDOFF to 1 ...

Page 1266: ...response register Execute CMD25 Set CMDR then CMDSTRT Set the block size in TBCR No Yes CRCERI interrupt detected Yes No CMD16 normal end Yes No CRPI interrupt detected Yes No Response status normal Yes No CTERI interrupt detected Execute CMD 23 Yes No CMD 23 normal end 1 2 Figure 24 20 3 Example of Operational Flow for Commands with Write Data Pre defined Multiple Block Transfer ...

Page 1267: ...ytes Cap FIFO size bytes n FEI Number of FIFO empty interrupts FEI from the start of read sequence n DRPI Number of data response interrupts DRPI from the start of write sequence Legend DTERI interrupt detected Yes No DRPI interrupt detected Yes Cap n FEI Len 1 n DRPI Len No No Yes TBNCR n DRPI No Yes BTI interrupt detected No Yes DTI interrupt detected No Yes FEI interrupt detected No Set CMDOFF ...

Page 1268: ...STRT No Yes CRCERI interrupt detected Yes No CRPI interrupt detected Yes No Response status normal Yes No CTERI interrupt detected End of command sequence Write data to FIFO Set DATAEN to 1 Yes No All data written to FIFO Yes FEI interrupt detected No Set CMDOFF to 1 Set CMDOFF to 1 Execute CMD12 Figure 24 21 Example of Operational Flow for Commands with Write Data Stream Transfer ...

Page 1269: ...ch interrupt source can be individually enabled by the enable bits in INTCR0 to INTCR2 Disabled interrupt sources do not set the flag Table 24 7 MMCIF Interrupt Sources Name Interrupt source Interrupt flag FIFO empty FEI FSTAT FIFO full FFI Data response DRPI Data transfer end DTI Command response receive end CRPI Command transmit end CMDI TRAN Data busy end DBSYI CRC error CRCERI Data timeout err...

Page 1270: ... DMACR to H 00 if a CRC error CRCERI or a command timeout error CTERI occurs in the command response reception Set the CMDOFF bit to 1 clear DMACR to H 00 and clear FIFO if a CRC error CRCERI or a data timeout error DTERI occurs in the read data reception When using DMA next block read is resumed automatically when the AUTO bit in DMACR is set to 1 and normal read is detected after the block trans...

Page 1271: ...o 0 Set the CMDOFF bit to 1 and clear DMACR to H 00 if a CRC error CRCERI or a command timeout error CTERI occurs in the command response reception Set the CMDOFF bit to 1 clear DMACR to H 00 and clear FIFO if a CRC error CRCERI or a data timeout error DTERI occurs in the read data reception Notes 1 In multiple block transfer when the command sequence is ended the CMDOFF bit is written to 1 before...

Page 1272: ... 1 Clear DMACR to H 00 CMD16 normal end No Yes CRPI interrupt detected No Yes Response status normal No Yes DTI interrupt detected No Yes DMA transfer end No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No CRCERI interrupt detected Yes No DTERI interrupt detected Yes No Set the size of block for transfer in TBCR Execute CMD17 Set CMDR then CMDSTRT Set CMDOFF to 1 Clear DMACR t...

Page 1273: ...the DMAC Set DMACR in the MMCIF Read response register CMD16 normal end No Yes CRPI interrupt detected No Yes Response status normal No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Set the block size in TBCR Execute CMD 18 Set CMDR then CMDSTRT 1 2 Figure 24 23 1 Example of Read Sequence Flow Open ended Multiple Block Transfer ...

Page 1274: ...FF to 1 Clear DMACR to H 00 Execute CMD12 Set CMDOFF to 1 DTI interrupt detected No Yes DMA transfer end No Yes CRCERI interrupt detected Yes No DTERI interrupt detected Yes No Next block read No Yes 1 2 Set RD_CONTI to 1 Set CMDOFF to 1 Clear DMACR to H 00 Clear FIFO Execute CMD12 Figure 24 23 2 Example of Read Sequence Flow Open ended Multiple Block Transfer ...

Page 1275: ...response register CMD16 normal end No Yes CRPI interrupt detected No Yes Response status normal No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Set the block size in TBCR Set the number of blocks in TBNCR Execute CMD 18 Set CMDR then CMDSTRT Execute CMD 23 CMD 23 normal end No Yes 1 2 Figure 24 23 3 Example of Read Sequence Flow Pre defined Multiple Block Transfer ...

Page 1276: ...errupt detected No Yes DMA transfer end No Yes CRCERI interrupt detected Yes No DTERI interrupt detected Yes No BTI interrupt detected No Yes TBNCR n DTI No Yes Legend n DTI Number of data transfer end interrupts DTI from the start of read sequence 1 2 Set RD_CONTI to 1 Set CMDOFF to 1 Clear DMACR to H 00 Clear FIFO Execute CMD12 Figure 24 23 4 Example of Read Sequence Flow Pre defined Multiple Bl...

Page 1277: ...onse register Set CMDOFF to 1 Execute CMD12 Set CMDOFF to 1 Clear DMACR to H 00 CRPI interrupt detected No Yes Response status normal No Yes DMA transfer end No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No DTERI interrupt detected Yes No Execute CMD11 Set CMDR then CMDSTRT Set CMDOFF to 1 Execute CMD12 Clear FIFO Figure 24 24 Example of Operational Flow for Stream Read Tran...

Page 1278: ...se register CMD16 normal end No Yes CRPI interrupt detected No Yes Response status normal No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Set the block size in TBCR Set the number of blocks for transfer in TBNCR Execute CMD 18 Set CMDR then CMDSTRT Execute CMD 23 CMD 23 normal end No Yes 1 2 Figure 24 25 1 Example of Operational Flow for Auto mode Pre defined Multiple Block...

Page 1279: ... to 1 Clear DMACR to H 00 Clear DMACR to H 00 Clear FIFO Execute CMD12 Set CMDOFF to 1 Clear DMACR to H 00 Set CMDOFF to 1 BTI interrupt detected No Yes DMA transfer end No Yes CRCERI interrupt detected Yes No DTERI interrupt detected Yes No 1 2 Figure 24 25 2 Example of Operational Flow for Auto mode Pre defined Multiple Block Read Transfer ...

Page 1280: ...is completed and be sure to clear the DMAEN bit in DMACR to 0 Set the CMDOFF bit to 1 if a CRC error CRCERI or a data timeout error DTERI occurs in the command response reception Set the CMDOFF bit to 1 clear FIFO and clear DMACR to H 00 if a CRC error CRCERI or a data timeout error DTERI occurs in the write data transmission When using DMA an inter block interrupt can be processed by hardware in ...

Page 1281: ... flag DBSYI Detect whether in the data busy state through the DTBUSY bit in CSTR after data transfer end after DRPI is detected If still in the data busy state wait for the DBSY flag to confirm that the data busy state has ended Set the CMDOFF bit to 1 and end the command sequence Set the CMDOFF bit to 1 and clear DMACR to H 00 if a CRC error CRCERI or a command timeout error CTERI occurs in the c...

Page 1282: ...e DMAC Set DMACR in the MMCIF Read response register CMD16 normal end No Yes CRPI interrupt detected No Yes Response status normal No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Set the size of block for transfer in TBCR Execute CMD 24 Set CMDR then CMDSTRT 1 2 Figure 24 26 1 Example of Write Sequence Flow Single Block Transfer ...

Page 1283: ...o 1 DRPI interrupt detected No Yes DBSYI interrupt detected No Yes CRCERI interrupt detected Yes No DTERI interrupt detected Yes No DTBUSY detected No Yes FRDYI interrupt detected or DMA transfer end No Yes Clear DMACR to H 00 DMA transfer end No Yes DTI interrupt detected No Yes 1 2 Figure 24 26 2 Example of Write Sequence Flow Single Block Transfer ...

Page 1284: ...the DMAC Set DMACR in the MMCIF Read response register CMD16 normal end No Yes CRPI interrupt detected No Yes Response status normal No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Set the block size in TBCR Execute CMD 25 Set CMDR then CMDSTRT 1 2 Figure 24 27 1 Example of Write Sequence Flow Open ended Multiple Block Transfer ...

Page 1285: ...Yes No DTERI interrupt detected Yes No Next block write No Yes DTBUSY detected No Yes FRDYI interrupt detected or DMA transfer end No Yes Clear DMACR to H 00 DMA transfer end No Yes DTI interrupt detected No Yes 1 2 Set CMDOFF to 1 Clear FIFO Clear DMACR to H 00 Execute CMD12 or Stop Tran Set CMDOFF to 1 Execute CMD12 or Stop Tran Set CMDOFF to 1 Figure 24 27 2 Example of Write Sequence Flow Open ...

Page 1286: ...esponse register CMD16 normal end No Yes CRPI interrupt detected No Yes Response status normal No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Set the block size in TBCR Execute CMD 25 Set CMDR then CMDSTRT 1 2 Set the number of blocks in TBNCR Execute CMD 23 CMD 23 normal end No Yes Figure 24 27 3 Example of Write Sequence Flow Pre defined Multiple Block Transfer ...

Page 1287: ...TI interrupt detected No Yes TBNCR n DRPI No Yes DTBUSY detected No Yes FRDYI interrupt detected or DMA transfer end No Yes Clear DMACR to H 00 DMA transfer end Yes DTI interrupt detected No Yes 1 2 Set CMDOFF to 1 Clear FIFO Clear DMACR to H 00 Execute CMD12 or Stop Tran Set CMDOFF to 1 Set CMDOFF to 1 Legend n DRPI Number of data response interrupts DRPI from the start of write sequence Figure 2...

Page 1288: ...No Yes Response status normal No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Execute CMD 20 Set CMDR then CMDSTRT End of command sequence Set DATAEN to 1 FRDYI interrupt detected or DMA transfer end No Yes Clear DMACR to H 00 DMA transfer end No Yes FEI interrupt detected No Yes Set CMDOFF to 1 Execute CMD12 Set CMDOFF to 1 Figure 24 28 Example of Operational Flow for Stre...

Page 1289: ...ister CMD16 normal end No Yes CRPI interrupt detected No Yes Response status normal ended No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Set the block size in TBCR Execute CMD 25 Set CMDR then CMDSTRT 1 2 Set the number of blocks in TBNCR Execute CMD 23 CMD 23 normal end No Yes Figure 24 29 1 Example of Operational Flow for Auto mode Pre defined Multiple Block Write Transf...

Page 1290: ...tected No Yes CRCERI or WRERI interrupt detected Yes No DTERI interrupt detected Yes No DTBUSY detected No Yes Clear DMACR to H 00 DMA transfer end No Yes 1 2 Set CMDOFF to 1 Clear FIFO Clear DMACR to H 00 Execute CMD12 or Stop Tran Set CMDOFF to 1 Set CMDOFF to 1 Figure 24 29 2 Example of Operational Flow for Auto mode Pre defined Multiple Block Write Transfer ...

Page 1291: ...ttle Endian Specification When the little endian is specified the access size for registers or that for memory where the corresponding data is stored should be fixed For example if data read from the MMCIF with the word size is written to memory and then it is read from memory with the byte size data misalignment occurs ...

Page 1292: ...24 Multimedia Card Interface MMCIF Rev 1 00 Jan 10 2008 Page 1262 of 1658 REJ09B0261 0100 ...

Page 1293: ... the DMAC can be used 25 1 Features The HAC has the following features Supports a subset of digital interface to a single AC 97 revision 2 1 Audio Codec PIO transfer of status slots 1 and 2 in RX frames PIO transfer of command slots 1 and 2 in TX frames PIO transfer of data slots 3 and 4 in RX frames PIO transfer of data slots 3 and 4 in TX frames Selectable 16 bit or 20 bit DMA transfer of data s...

Page 1294: ...Interrupt request Internal bus interface Transmission CSAR TX buffer CSDR TX buffer PCML TX buffer PCMR TX buffer DMA control HAC transmitter Shift register for slot 1 Shift register for slot 2 Shift register for slot 3 Shift register for slot 4 DMA request Data 19 0 Data 19 0 Data 31 0 Data 31 0 Data 19 0 Data 19 0 Control signal Bit control signal Interrupt request Data 19 0 Data 19 0 Data 19 0 ...

Page 1295: ... O Function HAC0_BITCLK 1 Input Serial data clock HAC0_SDIN 1 Input RX frame serial input data HAC0_SDOUT 1 Output TX frame serial output data HAC0_SYNC 1 Output Frame sync HAC1_BITCLK 1 Input Serial data clock HAC1_SDIN 1 Input RX frame serial input data HAC1_SDOUT 1 Output TX frame serial output data HAC1_SYNC 1 Output Frame sync HAC_RES 1 Output Reset negative logic signal common to channels 0 ...

Page 1296: ...egister 0 HACTSR0 R W H FFE3 0054 H 1FE3 0054 32 Pck 0 RX interrupt enable register 0 HACRIER0 R W H FFE3 0058 H 1FE3 0058 32 Pck 0 RX status register 0 HACRSR0 R W H FFE3 005C H 1FE3 005C 32 Pck 0 HAC control register 0 HACACR0 R W H FFE3 0060 H 1FE3 0060 32 Pck 1 Control and status register 1 HACCR1 R W H FFE4 0008 H 1FE4 0008 32 Pck 1 Command status address register 1 HACCSAR1 R W H FFE4 0020 H...

Page 1297: ...ta register 0 HACCSDR0 H 0000 0000 H 0000 0000 Retained Retained Retained 0 PCM left channel register 0 HACPCML0 H 0000 0000 H 0000 0000 Retained Retained Retained 0 PCM right channel register 0 HACPCMR0 H 0000 0000 H 0000 0000 Retained Retained Retained 0 TX interrupt enable register 0 HACTIER0 H 0000 0000 H 0000 0000 Retained Retained Retained 0 TX status register 0 HACTSR0 H F000 0000 H F000 00...

Page 1298: ...SDR1 H 0000 0000 H 0000 0000 Retained Retained Retained 1 PCM left channel register 1 HACPCML1 H 0000 0000 H 0000 0000 Retained Retained Retained 1 PCM right channel register 1 HACPCMR1 H 0000 0000 H 0000 0000 Retained Retained Retained 1 TX interrupt enable register 1 HACTIER1 H 0000 0000 H 0000 0000 Retained Retained Retained 1 TX status register 1 HACTSR1 H F000 0000 H F000 0000 Retained Retain...

Page 1299: ...0 R R R R W W R R CR CDRT WMRT ST 0 Bit Bit Name Initial Value R W Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 CR 0 R Codec Ready 0 The HAC connected codec is not ready 1 The HAC connected codec is ready 14 to 12 All 0 R Reserved These bits are always read as 0 Write prohibited 11 CDRT 0 W HAC Cold Reset Use a cold reset only after po...

Page 1300: ...ys be 0 5 ST 0 W Start Transfer Write 0 Stops data transmission reception at the end of the current frame Do not take this action to terminate transmission reception in normal operation When terminating transmission reception in normal operation refer to the following description 1 Starts data transmission reception Read Always read as 0 4 to 0 All 0 R Reserved These bits are always read as 0 The ...

Page 1301: ... R R R R R R R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R R R R CA3 SA3 CA2 SA2 CA1 SA1 CA0 SA0 SLR EQ3 SLR EQ4 SLR EQ5 SLR EQ6 SLR EQ7 SLR EQ8 SLR EQ9 SLR EQ10 SLR EQ11 SLR EQ12 CA6 SA6 RW CA5 SA5 CA4 SA4 0 Bit Bit Name Initial Value R W Description 31 to 20 All 0 R Reserved These bits are always read as 0 The write value should a...

Page 1302: ...e the status address received via slot 1 corresponding to the codec register whose data has been returned in HACCSDR 11 10 9 8 7 6 5 4 3 2 SLREQ3 SLREQ4 SLREQ5 SLREQ6 SLREQ7 SLREQ8 SLREQ9 SLREQ10 SLREQ11 SLREQ12 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R Slot Requests 3 to 12 Valid only in the RX frame Indicate whether the codec is requesting slot data in the next TX frame Automatically set by hardwa...

Page 1303: ...equest HACRSR STDRY 1 the status data received via slot 2 can be read out from HACCSDR In both read and write HACCSAR stores the related codec register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value R R R R R R R R R R R R R W R W R W R W R W R W R W R W R R R R R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ...

Page 1304: ...0 SD10 CD9 SD9 CD8 SD8 CD7 SD7 CD6 SD6 CD5 SD5 CD4 SD4 CD3 SD3 CD2 SD2 CD1 SD1 CD0 SD0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Command Data 15 to 0 Status Data 15 to 0 Write data to these bits and then write the codec register address in HACCSAR The HAC then transmits the data to the codec Read these bits to get the contents of the codec regi...

Page 1305: ...8 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value R R R R R R R R R R R R R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W D19 D18 D17 D16 D3 D2 D1 D0 D7 D6 D5 D4 D11 D10 D9 D8 D15 D14 D13 D12 0 Bit Bit Name Initial Value R W Description...

Page 1306: ...RD1 RD2 RD0 RD7 RD6 RD5 RD4 RD11 RD10 RD9 RD8 RD15 RD14 RD13 RD12 LD3 LD1 LD2 LD0 LD7 LD6 LD5 LD4 LD11 LD10 LD9 LD8 LD15 LD14 LD13 LD12 0 Bit Bit Name Initial Value R W Description 31 to 16 LD15 to LD0 All 0 R W Left Data 15 to 0 Write the PCM playback left channel data to these bits The HAC then transmits the data to the codec on an on demand basis Read these bits to get the PCM record left chann...

Page 1307: ...28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value R R R R R R R R R R R R R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W D19 D18 D17 D16 D3 D2 D1 D0 D7 D6 D5 D4 D11 D10 D9 D8 D15 D14 D13 D12 0 Bit Bit Name Initial Value R W Descriptio...

Page 1308: ...0 R Reserved These bits are always read as 0 The write value should always be 0 29 PLTFRQIE 0 R W PCML TX Request Interrupt Enable 0 Disables PCML TX request interrupts 1 Enables PCML TX request interrupts 28 PRTFRQIE 0 R W PCMR TX Request Interrupt Enable 0 Disables PCMR TX request interrupts 1 Enables PCMR TX request interrupts 27 to 10 All 0 R Reserved These bits are always read as 0 The write ...

Page 1309: ... FRQ CMD DMT CMD AMT PRT FRQ 0 Bit Bit Name Initial Value R W 2 Description 31 CMDAMT 1 R W Command Address Empty 0 CSAR TX buffer contains untransmitted data 1 CSAR TX buffer is empty and ready to store data 1 30 CMDDMT 1 R W Command Data Empty 0 CSDR TX buffer contains untransmitted data 1 CSDR TX buffer is empty and ready to store data 1 29 PLTFRQ 1 R W PCML TX Request 0 PCML TX buffer contains...

Page 1310: ... but new data is not written to HACPCMR 7 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 Notes 1 CMDAMT and CMDDMT have no associated interrupts Poll these bits until they are read as 1 before writing a new command to HACCSAR HACCSDR When bit 19 RW of HACCSAR is 0 and TX12_ATOMIC is 1 take the following steps 1 Initialize CMDDMT and CMDAMT before first acc...

Page 1311: ... These bits are always read as 0 The write value should always be 0 22 STARYIE 0 R W Status Address Ready Interrupt Enable 0 Disables status address ready interrupts 1 Enables status address ready interrupts 21 STDRYIE 0 R W Status Data Ready Interrupt Enable 0 Disables status data ready interrupts 1 Enables status data ready interrupts 20 PLRFRQIE 0 R W PCML RX Request Interrupt Enable 0 Disables...

Page 1312: ...The write value should always be 0 25 3 9 RX Status Register HACRSR HACRSR is a 32 bit read write register that indicates the status of the HAC RX controller Writing 0 to the bit will initialize it 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value R R R R R R R R R R W R W R W R W R R R R R R R R R R R R W Bit Initial value R W 15 14 13 12 11 10 9 8 ...

Page 1313: ... RX Request 0 PCMR RX data is not ready 1 PCMR RX data is ready and must be read In DMA mode reading HACPCMR automatically clears this bit to 0 18 to 14 All 0 R Reserved These bits are always read as 0 The write value should always be 0 13 PLRFOV 0 R W PCML RX Overrun 0 No PCML RX data overrun has occurred 1 PCML RX data overrun has occurred because the HAC has received new data from slot 3 before...

Page 1314: ...t is always read as 1 The write value should always be 1 30 DMARX16 0 R W 16 bit RX DMA Enable 0 Disables 16 bit packed RX DMA mode Enables the RXDMAL_EN and RXDMAR_EN settings 1 Enables 16 bit packed RX DMA mode Disables the RXDMAL_EN and RXDMAR_EN settings 29 DMATX16 0 R W 16 bit TX DMA Enable 0 Disables 16 bit packed TX DMA mode Enables the TXDMAL_EN and TXDMAR_EN settings 1 Enables 16 bit pack...

Page 1315: ...or HACPCML 1 Enables 20 bit RX DMA for HACPCML 23 TXDMAL_EN 0 R W TX DMA Left Enable 0 Disables 20 bit TX DMA for HACPCML 1 Enables 20 bit TX DMA for HACPCML 22 RXDMAR_EN 0 R W RX DMA Right Enable 0 Disables 20 bit RX DMA for HACPCMR 1 Enables 20 bit RX DMA for HACPCMR 21 TXDMAR_EN 0 R W TX DMA Right Enable 0 Disables 20 bit TX DMA for HACPCMR 1 Enables 20 bit TX DMA for HACPCMR 20 to 0 All 0 R Re...

Page 1316: ... 25 3 AC97 Transmit Frame Structure Slot Name Description 0 SDATA_OUT TAG Codec IDs and Tags indicating valid data 1 Control CMD Addr write port Read write command and register address 2 Control DATA write port Register write data 3 PCM L DAC playback Left channel PCM output data 4 PCM R DAC playback Right channel PCM output data 5 Modem Line 1 DAC Modem 1 output data unsupported 6 PCM Center Cent...

Page 1317: ...rt Register read data 3 PCM L ADC record Left channel PCM input data 4 PCM R ADC record Right channel PCM input data 5 Modem Line 1 ADC Modem 1 input data unsupported 6 Dedicated Microphone ADC Optional PCM data unsupported 7 to 9 Reserved Reserved 10 Modem Line 2 ADC Modem 2 input data unsupported 11 Modem handset input DAC Modem handset input data unsupported 12 Modem IO status Modem control IO ...

Page 1318: ...t is possible to read 20 bit data within a 32 bit register using PIO In the case of RX overrun the new data will overwrite the current data in the RX buffer of the HAC 25 5 2 Transmitter The HAC transmitter outputs serial audio data on the HAC_SDOUT pin synchronous to HAC_BIT_CLK The transmitter sets the tag bits in slot 0 to indicate which slots in the current frame contain valid data It loads da...

Page 1319: ...ata from slots 3 and 4 are packed into a single 32 bit quantity left data and right data are in PCML which requires only one local bus access cycle It may be necessary to halt a DMA transfer before the end count is reached depending on system applications If so clear the corresponding DMA bit in HACACR to 0 DMA disabled To resume a DMA transfer reprogram the DMAC and then set the corresponding DMA...

Page 1320: ...0 0000 20 bit DMA TX slots and 2 atomic control 1 Codec ready Set HACCCR to H 0000 8000 20 bit DMA TX slots and 2 atomic control 1 Set DMAC 2 Set read address to h 26 Power down mode Ctrl Stat Set HACCSAR to H 000A 6000 1 Off chip codec internal status ADC DAC Analog REF ready Set HACCSDR to H 0000 00F0 1 Set read volume and sampling rate 1 HACACR H 0000 0000 2 Set HACCSAR and HACCSDR 3 HACACR H 0...

Page 1321: ...tryCnt to 0 Set data in CSDR Set Addr in CSAR No Clear LoopCnt to 0 RetryCnt TSR CMDAMT 1 TSR CMDDMT 1 E1 LoopCnt 1 5 RetryCnt Notes E1 Loop count required in the target system 21 E1 1000 Input Addr Address of codec register to be written to Data Data to be written to codec register RetryCnt Software counter for error detection LoopCnt Software counter for wait insertion Figure 25 4 Sample Flowcha...

Page 1322: ...ror Data 2 return Read_codec_aux Send_read_request RegN Send_read_request RegN Get_codec_data RegN Get_codec_data RegN Read_codec_aux RegV No No No Error Data acquisition Data 1 acquisition Data 2 acquisition Input RegN address of the codec register to be read Input RegN address of the codec register to be read In continuous reading of registers in some off chip codec devices the data in the regis...

Page 1323: ...lue DataT Variable to hold CSDR read value Set RegN in CSAR WaitLoop_CMDAMT Error Error Error Error Error Return Wait for 5 μs LoopCnt 2 No No Yes Yes No Yes Get_codec_data Input RegN address of the codec register to be read Input RegN address of the codec register to be read Clear LoopCnt 2 to 0 WaitLoop_RSR Assign HACCSAR read value to Addr Addr R RegN E2 LoopCnt 2 Assign HACCSDR read value to D...

Page 1324: ...er for wait insertion LoopCnt4 Software counter for wait insertion Write 0 to TSR CMDAMT Return Return Error Clear LoopCnt 3 to 0 TSR CMDAMT 1 Wait for 1 μs LoopCnt 3 Yes E3 LoopCnt 3 Error No No Yes WaitLoop_RSR Write 0 to RSR STARY Write 0 to RSR STDRY Clear LoopCnt 4 to 0 RSR STARY 1 RSR STDRY 1 Wait for 1 μs LoopCnt 4 Yes E4 LoopCnt 4 Figure 25 7 Sample Flowchart for Off Chip Codec Register Re...

Page 1325: ...s to the HAC To place the HAC into the power down mode take the following steps 1 Check that all data transfers have ended Also check that the transmit buffer is empty and the receive buffer has been read out to be empty 2 Disable all DMA requests and interrupt requests 3 Place the codec into power down mode 4 Write 0 to the MSTP16 and MSTP17 bits in the standby control register 0 MSTPCR0 25 5 7 N...

Page 1326: ...25 Audio Codec Interface HAC Rev 1 00 Jan 10 2008 Page 1296 of 1658 REJ09B0261 0100 ...

Page 1327: ...umber of channels Two channels Operating modes Compressed mode and non compressed mode The compressed mode is used for continuous bit stream transfer The non compressed mode supports all serial audio streams divided into channels The SSI module is configured as any of a transmitter or receiver The serial bus format refer to table 26 3 can be used in the compressed and non compressed mode Asynchron...

Page 1328: ...he SSI module Serial audio bus SSIn_SDATA SSIn_WS SSIn_SCK SSIn_CLK INTC DMAC DMA request Interrupt request Peripheral bus Control circuit Register SSICR SSISR SSITDR SSIRDR Data buffer Barrel shifter MSB Shift register Bit counter Serial clock control SSI module Divider LSB Note n 0 to 1 Figure 26 1 Block Diagram of SSI Module ...

Page 1329: ...Configuration Name Number of Pins I O Function SSI0_SCK 1 I O Serial bit clock SSI0_WS 1 I O Word select SSI0_SDATA 1 I O Serial data input output SSI0_CLK 1 Input Divider input clock oversampling clock 256 384 512fs input SSI1_SCK 1 I O Serial bit clock SSI1_WS 1 I O Word select SSI1_SDATA 1 I O Serial data input output SSI1_CLK 1 Input Divider input clock oversampling clock 256 384 512fs input ...

Page 1330: ...RDR1 R H FFE1 000C H 1FE1 000C 32 Pck Note Bits 26 and 27 of this register is readable writable The other bits are read only For details see section 26 3 2 Status Register SSISR Table 26 2 Register Configuration 2 Channel Register Name Abbrev Power on Reset by PRESET Pin WDT H UDI Manual Reset by WDT Multiple Exception Sleep by SLEEP Instruction Module Standby Deep Sleep 0 Control register 0 SSICR...

Page 1331: ...W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 0 R Reserved These bits are always read as an undefined value The write value should always be 0 28 DMEN 0 R W DMA Enable Enables or disables the DMA request 0 DMA request disabled 1 DMA request enabled 27 UIEN 0 R W U...

Page 1332: ...ngth These bits indicate the number of bits in a data word These bits are ignored if CPEN 1 000 8 Bits 001 16 Bits 010 18 Bits 011 20 Bits 100 22 Bits 101 24 Bits 110 32 Bits 111 Setting prohibited 18 17 16 SWL2 SWL1 SWL0 0 0 0 R W R W R W System Word Length These bits indicate the number of bits in a system word These bits are ignored if CPEN 1 000 8 Bits 001 16 Bits 010 24 Bits 011 32 Bits 100 4...

Page 1333: ...k Polarity 0 SSI_WS and SSI_SDATA change on falling edge of SSI_SCK sampled on rising edge of SCK 1 SSI_WS and SSI_SDATA change on rising edge of SSI_SCK sampled on falling edge of SCK SCKP 0 SCKP 1 SSI_SDATA input sampling timing in receive mode TRMD 0 SSI_SCK rising edge SSI_SCK falling edge SSI_SDATA output change timing in transmit mode TRMD 1 SSI_SCK falling edge SSI_SCK rising edge SSI_WS in...

Page 1334: ...ve high flow control WS high means data should be transferred low means data should not be transferred 1 SSI_WS is active low flow control WS low means data should be transferred high means data should not be transferred Note Do not change this bit when EN is 1 11 SPDP 0 R W Serial Padding Polarity This bit is ignored if CPEN 1 0 Padding bits are low 1 Padding bits are high Note The padding bits b...

Page 1335: ...s in SSIRDR or SSITDR are used on the audio serial bus Two data words are transmitted received in each 32 bit access The first data word is derived from bits 15 to 0 and the second data word is stored in bits 31 to 16 DWL 010 011 100 101 data word length 18 20 22 and 24 bits PDTA 0 left aligned The data bits which are used in SSIRDR or SSITDR are the following Bits 31 to 32 number of bits having d...

Page 1336: ...ine the division ratio between oversampling clock SSI_CLK and the serial bit clock SSI_SCK These bits are ignored if SCKD 0 The serial bit clock is used for the shift register and is provided on the SSI_SCK pin 000 Serial bit clock frequency oversampling clock frequency 1 001 Serial bit clock frequency oversampling clock frequency 2 010 Serial bit clock frequency oversampling clock frequency 4 011...

Page 1337: ...mpressed mode disabled 1 Compressed mode enabled Note In compressed mode CPEN 1 using operation mode except slave transmitter SWSD 0 and TRMD 1 Do not change this bit when EN 1 1 TRMD 0 R W Transmit Receive Mode Select 0 The SSI module is in receive mode 1 The SSI module is in transmit mode 0 EN 0 R W SSI Module Enable 0 The SSI module is disabled 1 The SSI module is enabled ...

Page 1338: ... R R R W R R R R W R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R W Description 31 to 29 0 R Reserved These bits are always read as an undefined value The write value should always be 0 28 DMRQ 0 R DMA Request Status Flag This status flag allows the CPU to see the status of the DMA request of SSI module TRMD 0 Receive Mode If DMRQ 1 then ...

Page 1339: ... indicates that SSIRDR was read out before DMRQ and DIRQ bits would indicate the existence of new unread data In this instance the same received data may be stored twice by the host which can lead to destruction of multi channel data When TRMD 1 Transmit Mode If UIRQ 1 it indicates that the transmitted data was not written in SSITDR By this the same data may be transmitted one time too often which...

Page 1340: ...low error occurs the data in the data buffer will be overwritten by the next data sent from the SSI interface When TRMD 1 Transmit Mode If OIRQ 1 it indicates that SSITDR had data written in before the data in SSITDR was transferred to the shift register This may cause the loss of data which can lead to destruction of multi channel data 25 IIRQ 1 R Idle Mode Interrupt Status Flag This status flag ...

Page 1341: ...ata exists in SSIRDR 1 Unread data exists in SSIRDR When TRMD 1 Transmit Mode 0 The transmit buffer is full 1 The transmit buffer is empty and requires that data be written in SSITDR 23 to 4 0 R Reserved These bits are always read as an undefined value The write value should always be 0 3 2 CHNO1 CHNO0 0 0 R R Channel Number The number indicates the current channel When TRMD 0 Receive Mode This bi...

Page 1342: ...he following conditions SSI Serial bus master transmitter SWSD 1 and TRMD 1 This bit is set to 1 if no more data has been written to SSITDR and the current system word has been completed It can also be set to 1 when the EN bit has been cleared and the data that has been written to SSITDR is output on the serial data input output pin SSI_SDATA i e the serial data of the system word length is output...

Page 1343: ...Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 26 3 4 Receive Data Register SSIRDR SSIRDR is a 32 bit register that stores the received data Data in SSIRDR is transferred from the shift register as each data word is received If the...

Page 1344: ...s Format TPMD CPEN SCKD SWSD EN MUEN DIEN IIEN OIEN UIEN DEL PDTA SDTA SPDP SWSP SCKP SWL 2 0 DWL 2 0 CHNL 1 0 Non Compressed Slave Receiver 0 0 0 0 Non Compressed Slave Transmitter 1 0 0 0 Non Compressed Master Receiver 0 0 1 1 Non Compressed Master Transmitter 1 0 1 1 Control bits Configuration bits Compressed Slave Receiver 0 1 0 1 0 Control bits 1 Ignored Configu ration bits Ignored Compressed...

Page 1345: ...nform to the format as specified in the SSI module then operation is not guaranteed 3 Master Receiver This mode allows the SSI module to receive serial data from another device The clock and word select signals are internally derived from the SSI_CLK input clock The format of these signals is as defined in the SSI module If the incoming data does not conform to the defined format then operation is...

Page 1346: ...d length prev sample MSB LSB 1 LSB MSB LSB 1 LSB next sample SSI_SCK SSI_WS SSI_SDATA Figure 26 2 Philips Format with No Padding System word 1 System word 2 Data word 1 Data word 2 Padding Padding SCKP 0 SWSP 0 DEL 0 CHNL 00 SPDP 0 SDTA 0 System word length data word length MSB LSB MSB LSB next SSI_SCK SSI_WS SSI_SDATA Figure 26 3 Philips Format with Padding Figure 26 4 shows the format used by So...

Page 1347: ...ta word length MSB LSB MSB LSB prev SSI_SCK SSI_WS SSI_SDATA Figure 26 5 Matsushita Format with Padding Bits First Followed by Serial Data 6 Multi Channel Formats There is an extend format of the definition of the specification by Philips and allows more than 2 channels to be transferred within two system words The SSI module supports the transfer of 4 6 and 8 channels by the use of the CHNL SWL a...

Page 1348: ...24 16 14 12 10 8 0 100 48 40 32 30 28 26 24 16 101 64 56 48 46 44 42 40 32 110 128 120 112 110 108 106 104 96 00 1 111 256 248 240 238 236 234 232 224 000 8 001 16 0 010 24 8 011 32 16 0 100 48 32 16 12 8 4 0 101 64 48 32 28 24 20 16 0 110 128 112 96 92 88 84 80 64 01 2 111 256 240 224 220 216 212 208 192 000 8 001 16 010 24 0 011 32 8 100 48 24 0 101 64 40 16 10 4 110 128 104 80 74 68 62 56 32 10...

Page 1349: ...ansmitted received first and followed by serial data in the third example This selection is purely arbitrary Data word 1 Data word 2 Data word 3 Data word 4 System word 1 System word 2 Data word 1 Data word 2 Data word 3 Data word 4 System word 1 System word 2 SCKP 0 SWSP 0 DEL 1 CHNL 01 SPDP don t care SDTA don t care System word length data word length 2 MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB M...

Page 1350: ...rd 4 Data word 5 Data word 6 Data word 7 Data word 8 Padding System word 1 Padding SCKP 0 SWSP 1 DEL 1 CHNL 11 SPDP 0 SDTA 1 System word length data word length 4 MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB SSI_SCK SSI_WS SSI_SDATA Figure 26 8 Multi channel Format 8 Channels Serial Data First Followed by Padding Bits with Padding ...

Page 1351: ...serial bus padding Arrow head indicates sampling point of receiver Bit n in SSITDR 1st channel 2nd channel SWL 6 bits not attainable in SSI module demonstration only DWL 4 bits not attainable in SSI module demonstration only CHNL 00 SCKP 0 SWSP 0 SPDP 0 SDTA 0 PDATA 0 DEL 0 MUEN 0 4 bit data samples continuously written to SSITDR are transmitted onto the serial audio bus 0 0 0 0 0 0 0 1 TDn TD28 T...

Page 1352: ...ure 26 10 Inverted Clock 2 Inverted Word Select System word 1 System word 2 As basic sample format configuration except SWSP 1 0 0 0 0 0 0 TD28 TD31 TD31 TD30 TD29 TD28 TD31 TD30 TD29 TD28 SSI_SCK SSI_WS SSI_SDATA Figure 26 11 Inverted Word Select 3 Inverted Padding Polarity System word 1 System word 2 As basic sample format configuration except SPDP 1 TD28 TD31 1 1 1 1 1 1 TD31 TD30 TD29 TD28 TD3...

Page 1353: ...ing Bits First Followed by Serial Data without Delay As basic sample format configuration except SDTA 1 and DEL 1 System word 1 System word 2 0 0 0 TD28 0 0 TD29 0 TD31 TD30 TD29 TD28 TD31 TD30 TD29 TD28 SSI_SCK SSI_WS SSI_SDATA Figure 26 14 Padding Bits First Followed by Serial Data without Delay 6 Serial Data First Followed by Padding Bits without Delay As basic sample format configuration excep...

Page 1354: ...quires downstream decoding When burst mode is not enabled there is no concept of a data word However in order to receive and transmit it is necessary to transfer between the serial bus and word formatted memory Therefore the word boundary selection is arbitrary during receive transmit and must be dealt with by another module When burst mode is enabled then data bits being transmitted can be identi...

Page 1355: ...s 26 18 and 26 19 show the compressed mode data transfer with burst mode disabled and enabled respectively TRMD 1 CPEN 1 SCKD 1 SWSD 1 SWSP 0 BREN 0 Data word 1 Data word 2 Data word 3 Null data MSB LSB MSB LSB MSB LSB SSI_SCK SSI_WS SSI_SDATA Figure 26 18 Compressed Data Format Master Transmitter Burst Mode Disabled TRMD 1 CPEN 1 SCKD 1 SWSD 1 SWSP 0 BREN 1 Data word 1 Data word 2 Data word 3 Nul...

Page 1356: ... word select pin is used as an output flow control The module always asserts the word select signal to indicate it can receive more data continuously It is the responsibility of the transmitting device to ensure it can transmit data to the SSI module in time to ensure no data is lost 4 Master Transmitter This mode allows the module to transmit a serial bit stream from internal memory to another de...

Page 1357: ...g until bus inactive Power on reset Manual reset Figure 26 20 Transition Diagram between Operation Modes 1 Configuration Mode This mode is entered after the module is released from reset All required settings in the control register should be defined in this mode before the SSI module is enabled by setting the EN bit Setting the EN bit causes the SSI module to enter the module enabled mode 2 Modul...

Page 1358: ...errupts that the SSI module generates to supply data as required This mode has a higher interrupt load as the SSI module is only double buffered and will require data to be written at least every system word period When disabling the SSI module the SSI clock must be supplied continuously until the module enters in the idle state indicated by the IIRQ bit Figure 26 21 shows the transmit operation i...

Page 1359: ... SSI module enable DMA enable error interrupts Disable SSI module disable DMA disable error interrupt enable Idle interrupt Note When SSI error interrupt occurs underflow overflow back to start and execute flow again EN 0 DMEN 0 UIEN 0 OIEN 0 IIEN 1 Wait for idle interrupt from SSI module SSI error interrupt Has DMAC Tx data been completed More data to be send EN 1 DMEN 1 UIEN 1 OIEN 1 Specify TRM...

Page 1360: ...m SSI module Disable SSI module disable DMA disable error interrupt enable Idle interrupt Wait for interrupt from SSI Use SSI status register bits to realign data after underflow overflow Load data of channel n n CHNL 1 x 2 Loop Next Channel Data interrupt More data to be send Specify TRMD EN SCKD SWSD MUEN DEL PDTA SDTA SPDP SWSP SCKP SWL DWL CHNL EN 1 DIEN 1 UIEN 1 OIEN 1 EN 0 DIEN 0 UIEN 0 OIEN...

Page 1361: ...e controlled in one of two ways either DMA or an interrupt driven Figures 26 23 and 26 24 show the flow of operation When disabling the SSI module the SSI clock must be supplied continuously until the module enters in the idle state which is indicated by the IIRQ bit Note SCKD 0 Clock input through the SSI_SCK pin SCKD 1 Clock input through the SSI_CLK pin ...

Page 1362: ...DMA enable error interrupts Wait for idle interrupt from SSI module Disable SSI module disable DMA disable error interrupt enable Idle interrupt SSI Error interrupt Has DMAC Rx data been completed More data to be received Specify TRMD EN SCKD SWSD MUEN DEL PDTA SDTA SPDP SWSP SCKP SWL DWL CHNL Note When SSI error interrupt occurs underflow overflow back to start and execute flow again EN 0 DMEN 0 ...

Page 1363: ...e enable data interrupt enable error interrupts Use SSI status register bits to realign data after underflow overflow Wait for idle interrupt from SSI module Disable SSI module disable data interrupt disable error IRQ enable idle IRQ SSI Error interrupt More data to be received Specify TRMD EN SCKD SWSD MUEN DEL PDTA SDTA SPDP SWSP SCKP SWL DWL CHNL EN 0 DIEN 0 UIEN 0 OIEN 0 IIEN 1 EN 1 DIEN 1 UIE...

Page 1364: ...ll sample data until it is ready to store the sample data that the SSI module will receive next to ensure consistency of the number of received data and so resynchronize with the audio data stream 26 4 7 Serial Clock Control This function is used to control and select which clock is used for the serial bus interface If the serial clock direction is set to input SCKD 0 the SSI module is in clock sl...

Page 1365: ...transfer 26 5 2 Pin Function Setting for the SSI Module Before setting or activating the SSI module set the peripheral module select registers and the port control registers in terms of the SSI0 and SSI1 channels as described in section 28 General Purpose I O Ports GPIO 26 5 3 Usage Note in Slave Mode When terminating data transmission in slave mode the WS signal SSI WS input should be kept the ac...

Page 1366: ...ata transmission One system word Idle or data transmission SSI internal state Keep active WS input until IDST become 1 more than five system words Resumption from first or second WS falling edge SWSP 0 after EN bit is set to 1 Termination and transition to idle Figure 26 25 SSI Transfer Termination and Resumption Timing in Slave Mode ...

Page 1367: ...tes as a page In this document a sector always refers to the access unit of 512 16 bytes 2 Access Modes The FLCTL has two selectable access modes Command access mode Performs an access by specifying a command to be issued from the FLCTL to flash memory address and data size to be input or output Sector access mode Read or write in physical sector units by specifying a physical sector By specifying...

Page 1368: ...er Read from or write to the register with the specified access size The access size of FIFO is 32 bits 4 bytes In reading set the byte number to a multiple of four In writing set the byte number to a multiple of four in writing 8 Access Time The operating frequency of the FLCTL pins can be specified by the FCKSEL bit and the QTSEL bit in FLCMNCR regardless of the operating frequency of the periph...

Page 1369: ...EL FLSTE status error or ready busy timeout error FLTEND transfer end FLTRQ0 FIFO0 transfer request FLTRQ1 FIFO1 transfer request NAND type flash memory FIFO 256 bytes 1 1 2 1 4 DMA transfer requests 2 lines Peripheral bus Peripheral bus interface Registers Interrupt control Transmission reception control Control signal Peripheral clock Pck Details of interrupt source Figure 27 1 Block Diagram of ...

Page 1370: ... IRL7 MODE2 IRL6 MODE1 IRL5 MODE0 IRL4 MODE11 SCIF4_SCK MODE10 SCIF4_RXD MODE9 SCIF4_TXD and MODE8 SCIF3_SCK FCLE Command latch enable Output CLE Command Latch Enable CLE Asserted when a command is output Multiplexed with MODE4 SCIF3_TXD FALE Address latch enable Output ALE Address Latch Enable ALE Asserted when an address is output Negated when data is input or output Multiplexed with MODE7 SCIF3...

Page 1371: ...ndicates ready state at high level Indicates busy state at low level Multiplexed with SCIF0_RXD HSPI_RX WP Write Protect Reset Prevents accidental erasure or programming when power is turned on or off at low level FSE Spare area enable Output SE Spare Area Enable Enables access to spare area This pin must be fixed low in sector access mode Multiplexed with SCIF0_RTS HSPI_CS Note Not supported by t...

Page 1372: ...r FLCMCDR R W H FFE9 0008 H 1FE9 0008 32 Pck Address register FLADR R W H FFE9 000C H 1FE9 000C 32 Pck Data register FLDATAR R W H FFE9 0010 H 1FE9 0010 32 Pck Data counter register FLDTCNTR R W H FFE9 0014 H 1FE9 0014 32 Pck Interrupt DMA control register FLINTDMACR R W H FFE9 0018 H 1FE9 0018 32 Pck Ready busy timeout setting register FLBSYTMR R W H FFE9 001C H 1FE9 001C 32 Pck Ready busy timeou...

Page 1373: ...CMCDR H 0000 0000 H 0000 0000 Retained Retained FLADR H 0000 0000 H 0000 0000 Retained Retained FLDATAR H 0000 0000 H 0000 0000 Retained Retained FLDTCNTR H 0000 0000 H 0000 0000 Retained Retained FLINTDMACR H 0000 0000 H 0000 0000 Retained Retained FLBSYTMR H 0000 0000 H 0000 0000 Retained Retained FLBSYCNT H 0000 0000 H 0000 0000 Retained Retained FLDTFIFO Undefined Undefined Retained Retained F...

Page 1374: ... NAND WF CE0 TYPE SEL Bit Bit Name Initial Value R W Description 31 to 19 All 0 R Reserved These bits are always read as 0 The write value should always be 0 18 SNAND 0 R W Large Capacity NAND Flash Memory Select This bit is used to specify the NAND flash memory that a page consists of 2048 64 bytes 0 Selects the flash memory that a page consists of 512 16 bytes 1 Selects the flash memory that a p...

Page 1375: ... 1 0 00 R W Access Mode Specification 1 0 Specify access mode 00 Command access mode 01 Sector access mode 10 Setting prohibited 11 Setting prohibited 9 NANDWF 0 R W NAND Wait Insertion Operation 0 No wait 1 A wait cycle is inserted 8 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 CE0 0 R W Chip Enable 0 0 Disabled Outputs high level to the FCE pin 1 Ena...

Page 1376: ...RCNT 1 0 DOCMD2 DOCMD1 SCTCNT 15 0 Bit Bit Name Initial Value R W Description 31 ADRCNT2 0 R W Address Issue Byte Number Specification Specifies the number of bytes issued in the address stage 0 Issues address as many as the bytes specified in ADRCNT1 and ADRCNT0 1 Issues 5 byte address Note Set ADRCNT1 and ADRCNT0 to 0 30 to 27 SCTCNT 19 16 All 0 R W Selector Transfer Count Specification 19 16 Th...

Page 1377: ...as 0 The write value should always be 0 21 SELRW 0 R W Data Read Write Specification Specifies whether the direction is read or write in data stage 0 Read 1 Write 20 DOADR 0 R W Address Stage Execution Specification Specifies whether the address stage is executed in command access mode 0 Performs no address stage 1 Performs address stage 19 18 ADRCNT 1 0 00 R W Address Issue Byte Count Specificati...

Page 1378: ...mmand stage address stage and data stage see figure 27 2 27 3 3 Command Code Register FLCMCDR FLCMCDR is a 32 bit readable writable register that specifies a command to be issued in command access or sector access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W ...

Page 1379: ...R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W ADR 31 24 ADR 23 16 ADR 15 8 ADR 7 0 Bit Bit Name Initial Value R W Description 31 to 24 ADR 31 24 H 00 R W Fourth Address Data Specify the fourth data to be output to flash memory as an address in command access mode 23 to 16 ADR 23 16 H 00 R W Third Addr...

Page 1380: ... R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W ADR 25 16 ADR 15 0 Bit Bit Name Initial Value R W Description 31 to 26 All 0 R Reserved These bits are undefined depending on the operation mode of the FLCTL 25 to 0 ADR 25 0 All 0 R W Physical Sector Address Specify a physical sector number to be accessed in sector access mode The physical sector number is converted into an addr...

Page 1381: ...23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W R R R R R R R R ADR 7 0 Bit Bit Name Initial Value R W Description 31 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 to 0 ...

Page 1382: ...used when the CPU reads from or writes to FLECFIFO In reading from FLECFIFO these bits specify the number of longwords of the data that can be read from FLECFIFO In writing to FLECFIFO these bits specify the number of longwords of empty area that can be written to FLECFIFO 23 to 16 DTFLW 7 0 H 00 R FLDTFIFO Access Count Specify the number of longwords 4 bytes in FLDTFIFO to be read or written Thes...

Page 1383: ...t Initial value R W Bit Initial value R W DT 31 24 DT 23 16 DT 15 8 DT 7 0 Bit Bit Name Initial Value R W Description 31 to 24 DT 31 24 H 00 R W Fourth Data Specify the 4th data to be input or output via the FD7 to FD0 pins In writing Specify write data In reading Store read data 23 to 16 DT 23 16 H 00 R W Third Data Specify the 3rd data to be input or output via the FD7 to FD0 pins In writing Spe...

Page 1384: ...the FLCTL to the DMAC is issued after each access mode has started 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W FIFOTRG 1 0 AC1 CLR AC0 CLR DREQ1 EN DREQ0 EN...

Page 1385: ...CPU when FLDTFIFO stores 128 bytes of data or issue a DMA transfer request when FLDTFIFO stores 16 bytes of data 2 In writing flash memory 00 Issue an interrupt to the CPU when FLDTFIFO has 4 bytes or more of empty area do not set DMA transfer 01 Issue an interrupt or a DMA transfer request to the CPU when FLDTFIFO has 16 bytes or more of empty area 10 Issue an interrupt to the CPU when FLDTFIFO h...

Page 1386: ... from FLECFIFO 16 DREQ0EN 0 R W FLDTFIFODMA Request Enable Enables or disables the DMA transfer request issued from FLDTFIFO 0 Disables the issue of DMA transfer request from FLDTFIFO 1 Enables the issue of DMA transfer request from FLDTFIFO 15 to 9 All 0 R Reserved These bits are always read as 0 The write value should always be 0 8 STERB 0 R W Status Error Indicates the result of status read Thi...

Page 1387: ...it is a flag bit 1 cannot be written to this bit Only 0 can be written to clear the flag 0 Indicates that no transfer request is issued from FLECFIFO 1 Indicates that a transfer request is issued from FLECFIFO 5 TRREQF0 0 R W FLDTFIFO Transfer Request Flag Indicates that a transfer request is issued from FLDTFIFO Since this bit is a flag bit 1 cannot be written to this bit Only 0 can be written to...

Page 1388: ...ransfer 1 Enables an interrupt to the CPU at the end of a transfer 1 TRINTE1 0 R W FLECFIFO Transfer Request Enable to CPU Enables or disables an interrupt request to the CPU by a transfer request from FLECFIFO 0 Disables an interrupt request to the CPU by a transfer request from FLECFIFO 1 Enables an interrupt request to the CPU by a transfer request from FLECFIFO When the DMA transfer is enabled...

Page 1389: ...R R R R R R R R R R R R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W RBTMOUT 20 16 RBTMOUT 15 0 Bit Bit Name Initial Value R W Description 31 to 21 All 0 R Reserved These bits are always read as 0 The write value should always be 0 20 to 0 RBTMOUT 20 0 H 00000 R W Ready Busy Timeout Spe...

Page 1390: ...ed if an interrupt is enabled by the RBERINTE bit in FLINTDMACR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Initial value R W STAT 7 0 RBTIMCNT 20 16 RBTIMCNT 15 0 Bit Bit Name Initial Value R W Descripti...

Page 1391: ... value R W Bit Initial value R W DTFO 31 24 DTFO 23 16 DTFO 15 8 DTFO 7 0 Bit Bit Name Initial Value R W Description 31 to 24 DTFO 31 24 R W First Data Specify the first data to be input or output via the FD7 to FD0 pins In writing Specify write data In reading Store read data 23 to 16 DTFO 23 16 R W Second Data Specify the second data to be input or output via the FD7 to FD0 pins In writing Speci...

Page 1392: ...Bit Initial value R W ECFO 31 24 ECFO 23 16 ECFO 15 8 ECFO 7 0 Bit Bit Name Initial Value R W Description 31 to 24 ECFO 31 24 Undefined R W First Data Specify the first data to be input or output via the FD7 to FD0 pins In writing Specify write data In reading Store read data 23 to 16 ECFO 23 16 Undefined R W Second Data Specify the second data to be input or output via the FD7 to FD0 pins In writ...

Page 1393: ... TREND TRSTRT Bit Bit Name Initial Value R W Description 7 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 TREND 0 R W Processing End Flag Indicates that the processing performed in the specified access mode has been completed The write value should always be 0 0 TRSTRT 0 R W Transfer Start When the TREND bit is 0 processing in the access mode specified b...

Page 1394: ... direction and number of times for the registers In this mode DMA transfer of input or output data can be performed by using FLDTFIFO 1 NAND Type Flash Memory Access 512 16 Bytes Figure 27 2 shows an example of reading operation for NAND type flash memory In this example the first command is set to H 00 address data length is set to 3 bytes and the number of read bytes is set to 6 bytes in the dat...

Page 1395: ... 4 show examples of writing operation for NAND type flash memory 512 16 bytes H 80 A2 A1 A3 1 2 3 4 5 6 CLE ALE I O7 to I O0 R B WE RE Figure 27 3 Writing Operation Timing for NAND Type Flash Memory CLE WE RE ALE I O7 to I O0 R B H 10 H 70 Status Figure 27 4 Status Read Operation Timing for NAND Type Flash Memory ...

Page 1396: ...or NAND type flash memory In this example the first command is set to H 00 the second command is set to H 30 address data length is set to 4 bytes and the number of read bytes is set to 4 bytes in the data counter CLE ALE I O7 to I O0 R B WE RE H 00 H 30 1 2 3 4 A1 A2 A3 A4 Command stage Address stage Data stage Command stage Figure 27 5 Reading Operation Timing for NAND Type Flash Memory ...

Page 1397: ...show examples of writing operation for NAND type flash memory 2048 64 bytes CLE ALE I O7 to I O0 R B WE RE H 80 A1 A2 A3 A4 1 2 3 4 H 10 Figure 27 6 Writing Operation Timing for NAND Type Flash Memory CLE ALE I O7 to I O0 R B WE RE H 10 H 70 Status Figure 27 7 Status Read Operation Timing for NAND Type Flash Memory ...

Page 1398: ...red in FLECFIFO DMA transfer can be performed by setting the DREQ1EN and DREQ0EN bits in FLINTDMACR Figure 27 8 shows the relationship of DMA transfer between sectors in flash memory data and control code and memory in the address space FLCTL FLDTFIFO FLECFIFO Flash memory Data 512 bytes Control code 16 bytes DMA channel 0 transfer DMA channel 1 transfer Address space external memory area Data are...

Page 1399: ... Row2 Row3 Col1 Col2 Row1 Row2 Physical sector address For NAND type flash memory 512 16 bytes Physical sector address bits FLADR 17 0 Order of address output to NAND type flash memory I O For NAND type flash memory 2048 64 bytes Physical sector address Physical sector address bits FLADR 17 0 Order of address output to NAND type flash memory I O Note Since the address at each boundary 512 16 bytes...

Page 1400: ... count specification register settings when transferring logical sectors 0 to 40 which are not contiguous because of an unusable sector in NAND type flash memory 00 12 0 0 11 11 12 13 13 40 40 300 12 300 1 13 28 FLADR ADR17 to ADR0 FLCMDCR SCTCNT Physical sector Values specified in registers by CPU Physical sector specification Physical sector transfer count Sectors 0 to 11 are transferred Sector ...

Page 1401: ...the STERINTE bit in FLINTDMACR is enabled 1 Status Read of NAND Type Flash Memory 512 16 Bytes The status read of NAND type flash memory can be performed by inputting the command H 70 to NAND type flash memory When the DOSR bit in FLCMDCR is set to 1 and writing is performed in command access mode or sector access mode the FLCTL automatically inputs H 70 to NAND type flash memory and status read i...

Page 1402: ...s mode or sector access mode the FLCTL automatically inputs H 70 to NAND type flash memory and status read is performed During the status read of NAND type flash memory the I O7 to I O0 pins indicate the following information as shown in table 27 5 Table 27 5 Status Read of NAND Type Flash Memory 2048 64 Bytes I O Status Definition Description I O7 Write protection 0 Cannot be written 1 Can be wri...

Page 1403: ...cute second command stage DOADR B 1 execute address stage ADRMD B 1 address register value is output as memory address ADRCNT 1 0 B 01 issue 2 byte address DOSR B 1 perform status read Command code register FLCMCDR CMD 7 0 H 60 block erase command CMD 15 8 H D0 block erase execute command Address register FLADR Set erase addresses to ADR 7 0 and ADR 15 8 Transfer control register FLTRCR TRSTRT B 1...

Page 1404: ...ls Common control register FLCMNCR ACM 1 0 B 01 sector access mode CE0 B 1 enable the chip TYPESEL B 1 select NAND type flash memory Command control register FLCMDCR SELRW B 1 flash write DOCMD1 B 1 execute first command stage DOCMD2 B 1 execute second command stage DOADR B 1 execute address stage ADRMD B 1 specify physical sector address ADRCNT 1 0 B 10 issue 3 byte address DOSR B 1 perform statu...

Page 1405: ... 1 0 B 10 issue 3 byte address DOSR B 1 perform status read Command code register FLCMCDR CMD 7 0 H 00 flash read command Address register FLADR Set addresses to ADR 7 0 ADR 15 8 and ADR 23 16 Data counter register FLDTCNTR Specify number of bytes of read data to DTCNT 11 0 Interrupt DMA control register FLINTDMACR Set enable bit of DMA transfer or interrupt request to 1 Transfer control register ...

Page 1406: ...le Bit Description STERB STERINTE Status error FLSTE interrupt BTOERB RBERINTE Ready busy timeout error FLTEND interrupt TREND TEINTE Transfer end FLTRQ0 interrupt TRREQF0 TRINTE0 FIFO0 transfer request FLTRQ1 interrupt TRREQF1 TRINTE1 FIFO1 transfer request 27 7 DMA Transfer Settings The FLCTL can request DMA transfers separately to the data sector FLDTFIFO and control code sector FLECFIFO Table ...

Page 1407: ...ns of peripheral modules to select whether the pins are used by the GPIO or the peripheral modules The GPIO has the following features Each port pin is a multiplexed pin for which the port control register can specify the pin function and control the pull up MOS of the pin Each port has a data register that stores data for the pins GPIO interrupts are supported Note For the ports which can be used...

Page 1408: ... 2 B PB4 input output LBSC PCIC D51 AD19 2 B PB3 input output LBSC PCIC D50 AD18 2 B PB2 input output LBSC PCIC D49 AD17 DB5 2 B PB1 input output LBSC PCIC DU D48 AD16 DB4 2 B PB0 input output LBSC PCIC DU D47 AD15 DB3 2 C PC7 input output LBSC PCIC DU D46 AD14 DB2 2 C PC6 input output LBSC PCIC DU D45 AD13 DB1 2 C PC5 input output LBSC PCIC DU D44 AD12 DB0 2 C PC4 input output LBSC PCIC DU D43 AD...

Page 1409: ...output LBSC D28 F PF4 input output LBSC D27 F PF3 input output LBSC D26 F PF2 input output LBSC D25 F PF1 input output LBSC D24 F PF0 input output LBSC D23 G PG7 input output LBSC D22 G PG6 input output LBSC D21 G PG5 input output LBSC D20 G PG4 input output LBSC D19 G PG3 input output LBSC D18 G PG2 input output LBSC D17 G PG1 input output LBSC D16 G PG0 input output LBSC SCIF1_SCK H PH7 input ou...

Page 1410: ...ATUS0 DRAK0 1 K PK7 input output STATUS DMAC STATUS1 DRAK1 1 K PK6 input output STATUS DMAC DACK2 SCIF2_TXD MMCCMD SIOF_TXD 1 K PK5 input output DMAC SCIF2 MMCIF SIOF DACK3 SCIF2_SCK MMCDAT SIOF_SCK 1 K PK4 input output DMAC SCIF2 MMCIF SIOF DREQ0 K PK3 input output DMAC DREQ1 K PK2 input output DMAC DACK0 K PK1 input output DMAC DACK1 K PK0 input output DMAC DREQ2 INTB 1 L PL7 input output DMAC P...

Page 1411: ...PCIC DU TRDY DISP 2 P PP2 input output PCIC DU IRDY HSYNC 2 P PP1 input output PCIC DU PCIFRAME VSYNC 2 P PP0 input output PCIC DU INTA Q PQ4 input output PCIC GNT0 GNTIN Q PQ3 input output PCIC REQ0 REQOUT Q PQ2 input output PCIC PERR Q PQ1 input output PCIC SERR Q PQ0 input output PCIC WE7 CBE3 2 R PR3 input output LBSC PCIC WE6 CBE2 2 R PR2 input output LBSC PCIC WE5 CBE1 2 R PR1 input output L...

Page 1412: ...er PJCR R W H FFE7 0010 H 1FE7 0010 16 Pck Port K control register PKCR R W H FFE7 0012 H 1FE7 0012 16 Pck Port L control register PLCR R W H FFE7 0014 H 1FE7 0014 16 Pck Port M control register PMCR R W H FFE7 0016 H 1FE7 0016 16 Pck Port N control register PNCR R W H FFE7 0018 H 1FE7 0018 16 Pck Port P control register PPCR R W H FFE7 001A H 1FE7 001A 16 Pck Port Q control register PQCR R W H FF...

Page 1413: ...k Port J pull up control register PJPUPR R W H FFE7 0050 H 1FE7 0050 8 Pck Port K pull up control register PKPUPR R W H FFE7 0052 H 1FE7 0052 8 Pck Port L pull up control register PLPUPR R W H FFE7 0054 H 1FE7 0054 8 Pck Port M pull up control register PMPUPR R W H FFE7 0056 H 1FE7 0056 8 Pck Port N pull up control register PNPUPR R W H FFE7 0058 H 1FE7 0058 8 Pck Input pin pull up control registe...

Page 1414: ...tained Retained Retained Port N control register PNCR H FFFF Retained Retained Retained Retained Port P control register PPCR H 0000 Retained Retained Retained Retained Port Q control register PQCR H 0000 Retained Retained Retained Retained Port R control register PRCR H 0000 Retained Retained Retained Retained Port A data register PADR H 00 Retained Retained Retained Retained Port B data register...

Page 1415: ...H FF Retained Retained Retained Retained Port K pull up control register PKPUPR H FF Retained Retained Retained Retained Port L pull up control register PLPUPR H FF Retained Retained Retained Retained Port M pull up control register PMPUPR H FF Retained Retained Retained Retained Port N pull up control register PNPUPR H FF Retained Retained Retained Retained Input pin pull up control register 1 PP...

Page 1416: ...n 15 14 PA7MD1 PA7MD0 0 0 R W R W PA7 Mode 00 LBSC PCIC module D63 AD31 When the bus mode is set to DU via the bus mode pins MODE11 and MODE12 port input pull up MOS On is selected 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 13 12 PA6MD1 PA6MD0 0 0 R W R W PA6 Mode 00 LBSC PCIC module D62 AD30 When the bus mode is set to DU via the bus mode pins MODE11 and MODE12 port...

Page 1417: ...s set to DU via the bus mode pins MODE11 and MODE12 port input pull up MOS On is selected 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 5 4 PA2MD1 PA2MD0 0 0 R W R W PA2 Mode 00 LBSC PCIC module D58 AD26 When the bus mode is set to DU module via the bus mode pins MODE11 and MODE12 port input pull up MOS On is selected 01 Port output 10 Port input pull up MOS Off 11 Port...

Page 1418: ...de 00 LBSC PCIC module D56 AD24 When the bus mode is set to DU via the bus mode pins MODE11 and MODE12 port input pull up MOS On is selected 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On Note The module that uses the pin can be selected by the bus mode pins MODE11 and MODE12 For the details on setting the bus mode pin refer to the Appendix ...

Page 1419: ...n 15 14 PB7MD1 PB7MD0 0 0 R W R W PB7 Mode 00 LBSC PCIC module D55 AD23 When the bus mode is set to DU via the bus mode pins MODE11 and MODE12 port input pull up MOS On is selected 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 13 12 PB6MD1 PB6MD0 0 0 R W R W PB6 Mode 00 LBSC PCIC module D54 AD22 When the bus mode is set to DU via the bus mode pins MODE11 and MODE12 port...

Page 1420: ... output 10 Port input pull up MOS Off 11 Port input pull up MOS On 5 4 PB2MD1 PB2MD0 0 0 R W R W PB2 Mode 00 LBSC PCIC module D50 AD18 When the bus mode is set to DU via the bus mode pins MODE11 and MODE12 port input pull up MOS On is selected 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 3 2 PB1MD1 PB1MD0 0 0 R W R W PB1 Mode 00 LBSC PCIC DU module D49 AD17 DB5 01 Port...

Page 1421: ...R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 15 14 PC7MD1 PC7MD0 0 0 R W R W PC7 Mode 00 LBSC PCIC DU module D47 AD15 DB3 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 13 12 PC6MD1 PC6MD0 0 0 R W R W PC6 Mode 00 LBSC PCIC DU module D46 AD14 DB2 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 11 10 PC5MD1 PC5M...

Page 1422: ...ule D42 AD10 DG4 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 3 2 PC1MD1 PC1MD0 0 0 R W R W PC1 Mode 00 LBSC PCIC DU module D41 AD9 DG3 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 1 0 PC0MD1 PC0MD0 0 0 R W R W PC0 Mode 00 LBSC PCIC DU module D40 AD8 DG2 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On Note The modu...

Page 1423: ...W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 15 14 PD7MD1 PD7MD0 0 0 R W R W PD7 Mode 00 LBSC PCIC DU module D39 AD7 DG1 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 13 12 PD6MD1 PD6MD0 0 0 R W R W PD6 Mode 00 LBSC PCIC DU module D38 AD6 DG0 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 11 10 PD5MD1 PD5M...

Page 1424: ...ule D34 AD2 DR2 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 3 2 PD1MD1 PD1MD0 0 0 R W R W PD1 Mode 00 LBSC PCIC DU module D33 AD1 DR1 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 1 0 PD0MD1 PD0MD0 0 0 R W R W PD0 Mode 00 LBSC PCIC DU module D32 AD0 DR0 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On Note The modul...

Page 1425: ... All 0 R W Reserved These bits are always read as 0 and the write value should always be 0 11 10 PE5MD1 PE5MD0 0 0 R W R W PE5 Mode 00 PCIC module REQ1 When the bus mode is set to the local bus or DU via the bus mode pins MODE1 and MODE2 port input pull up MOS On is selected 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 9 8 PE4MD1 PE4MD0 0 0 R W R W PE4 Mode 00 PCIC mod...

Page 1426: ...ull up MOS Off 11 Port input pull up MOS On 3 2 PE1MD1 PE1MD0 0 0 R W R W PE1 Mode 00 PCIC module GNT2 When the bus mode is set to the local bus or DU via the bus mode pins MODE1 and MODE2 port input pull up MOS On is selected 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 1 0 PE0MD1 PE0MD0 1 1 R W R W PE0 Mode 00 PCIC MMCIF module GNT3 MMCCLK 01 Port output 10 Port inpu...

Page 1427: ...W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 15 14 PF7MD1 PF7MD0 0 0 R W R W PF7 Mode 00 LBSC module D31 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 13 12 PF6MD1 PF6MD0 0 0 R W R W PF6 Mode 00 LBSC module D30 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 11 10 PF5MD1 PF5M...

Page 1428: ...S Off 11 Port input pull up MOS On 5 4 PF2MD1 PF2MD0 0 0 R W R W PF2 Mode 00 LBSC module D26 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 3 2 PF1MD1 PF1MD0 0 0 R W R W PF1 Mode 00 LBSC module D25 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 1 0 PF0MD1 PF0MD0 0 0 R W R W PF0 Mode 00 LBSC module D24 01 Port output 10 Port input pull up MOS Of...

Page 1429: ...W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 15 14 PG7MD1 PG7MD0 0 0 R W R W PG7 Mode 00 LBSC module D23 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 13 12 PG6MD1 PG6MD0 0 0 R W R W PG6 Mode 00 LBSC module D22 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 11 10 PG5MD1 PG5M...

Page 1430: ...S Off 11 Port input pull up MOS On 5 4 PG2MD1 PG2MD0 0 0 R W R W PG2 Mode 00 LBSC module D18 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 3 2 PG1MD1 PG1MD0 0 0 R W R W PG1 Mode 00 LBSC module D17 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 1 0 PG0MD1 PG0MD0 0 0 R W R W PG0 Mode 00 LBSC module D16 01 Port output 10 Port input pull up MOS Of...

Page 1431: ... W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 15 14 PH7MD1 PH7MD0 1 1 R W R W PH7 Mode 00 SCIF 1 module SCIF1_SCK 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 13 12 PH6MD1 PH6MD0 1 1 R W R W PH6 Mode 00 SCIF 1 module SCIF1_RXD 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 11 10 PH5MD1 PH5MD0 1 1 R W ...

Page 1432: ...0 HSPI FLCTL module SCIF0_SCK HSPI_CLK FRE 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 3 2 PH1MD1 PH1MD0 1 1 R W R W PH1 Mode 00 SCIF 0 HSPI FLCTL module SCIF0_RXD HSPI_RX FRB 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 1 0 PH0MD1 PH0MD0 1 1 R W R W PH0 Mode 00 SCIF 0 HSPI FLCTL module SCIF0_TXD HSPI_TX FWE 01 Port output 10 Port input pu...

Page 1433: ... Name Initial value R W Description 15 14 PJ7MD1 PJ7MD0 1 1 R W R W PJ7 Mode 00 SCIF 5 HAC 1 SSI 1 module SCIF5_TXD HAC1_SYNC SSI1_WS 1 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 13 12 PJ6MD1 PJ6MD0 1 1 R W R W PJ6 Mode 00 SIOF HAC 0 SSI 0 module SIOF_TXD HAC0_SDOOUT SSI0_SDATA 1 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 11 10 PJ5MD1 P...

Page 1434: ...ff 11 Port input pull up MOS On 3 2 PJ1MD1 PJ1MD0 1 1 R W R W PJ1 Mode 00 HAC 1 SSI 1 module HAC1_BITCLK SSI1_CLK 1 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 1 0 PJ0MD1 PJ0MD0 1 1 R W R W PJ0 Mode 00 TMU LBSC module MODE13 TCLK IOIS16 1 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 2 Notes 1 The module that uses this pin can be selected b...

Page 1435: ...alue R W Bit Bit Name Initial value R W Description 15 14 PK7MD1 PK7MD0 0 0 R W R W PK7 Mode 00 STATUS DMAC module STATUS0 DRAK0 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 13 12 PK6MD1 PK6MD0 0 0 R W R W PK6 Mode 00 STATUS DMAC module STATUS0 DRAK0 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 11 10 PK5MD1 PK5MD0 1 1 R W R W PK5 Mode 00 DM...

Page 1436: ...1 1 R W R W PK2 Mode 00 DMAC module DREQ1 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 3 2 PK1MD1 PK1MD0 1 1 R W R W PK1 Mode 00 DMAC module DACK0 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 1 0 PK0MD1 PK0MD0 1 1 R W R W PK0 Mode 00 DMAC module DACK1 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On Note The module ...

Page 1437: ... W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 15 14 PL7MD1 PL7MD0 1 1 R W R W PL7 Mode 00 DMAC PCIC module DREQ2 INTB 1 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 13 12 PL6MD1 PL6MD0 1 1 R W R W PL6 Mode 00 DMAC PCIC module DREQ3 INTC 1 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 11 10 PL5MD1 PL5MD0 ...

Page 1438: ...Port input pull up MOS On 2 3 2 PL1MD1 PL1MD0 1 1 R W R W PL1 Mode 00 INTC FLCTL module MODE3 IRL7 FD7 1 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 2 1 0 PL0MD1 PL0MD0 1 1 R W R W PL0 Mode 00 DMAC LBSC module MODE12 DRAK3 CE2B 1 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 2 Notes 1 The module that uses this pin can be selected by the per...

Page 1439: ... PM1 MD0 PM1 MD1 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 15 to 4 All 1 R W Reserved These bits are always read as 1 and the write value should always be 1 3 2 PM1MD1 PM1MD0 0 0 R W R W PM1 Mode 00 LBSC module BREQ BSACK 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 1 0 PM0MD1 PM0MD0...

Page 1440: ... Bit Bit Name Initial value R W Description 15 14 PN7MD1 PN7MD0 1 1 R W R W PN7 Mode 00 SCIF 5 HAC 1 SSI 1 module SCIF5_RXD HAC1_SDIN SSI1_SCK 1 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 13 12 PL6MD1 PL6MD0 1 1 R W R W PN6 Mode 00 SCIF 5 HAC 1 SSI 1 module SCIF5_CSK HAC1_SDOUT SSI1_SDATA 1 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 11 ...

Page 1441: ...t input pull up MOS On 2 3 2 PL1MD1 PL1MD0 1 1 R W R W PN1 Mode 00 SCIF 4 FLCTL module MODE10 SCIF4_RXD FD2 1 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 2 1 0 PL0MD1 PL0MD0 1 1 R W R W PL0 Mode 00 SCIF 4 FLCTL module MODE11 SCIF4_SCK FD3 1 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 2 Notes 1 The module that uses this pin can be selected...

Page 1442: ... value R W Bit Bit Name Initial value R W Description 15 to 12 All 0 R W Reserved These bits are always read as 0 and the write value should always be 0 11 10 PP5MD1 PP5MD0 0 0 R W R W PP5 Mode 00 PCIC DU module DEVSEL DCLKOUT When the bus mode is set to the local bus by the bus mode pins MODE11 and MODE12 port input pull up MOS On is selected 01 Port output 10 Port input pull up MOS Off 11 Port i...

Page 1443: ... is selected 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 3 2 PP1MD1 PP1MD0 0 0 R W R W PP1 Mode 00 PCIC DU module IRDY HSYNC When the bus mode is set to the local bus by the bus mode pins MODE11 and MODE12 port input pull up MOS On is selected 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 1 0 PP0MD1 PP0MD0 0 0 R W R W PP0 Mode 00 PCIC DU mo...

Page 1444: ...e R W Bit Bit Name Initial value R W Description 15 to 10 All 0 R W Reserved These bits are always read as 0 and the write value should always be 0 9 8 PQ4MD1 PQ4MD0 0 0 R W R W PQ4 Mode 00 PCIC module INTA When the bus mode is set to the local bus or DU via the bus mode pins MODE1 and MODE2 port input pull up MOS On is selected 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MO...

Page 1445: ...l up MOS Off 11 Port input pull up MOS On 3 2 PQ1MD1 PQ1MD0 0 0 R W R W PQ1 Mode 00 PCIC module PERR When the bus mode is set to the local bus or DU via the bus mode pins MODE1 and MODE2 port input pull up MOS On is selected 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 1 0 PQ0MD1 PQ0MD0 0 0 R W R W PQ0 Mode 00 PCIC module SERR When the bus mode is set to the local bus ...

Page 1446: ...ue R W Bit Bit Name Initial value R W Description 15 to 8 All 0 R W Reserved These bits are always read as 0 and the write value should always be 0 7 6 PR3MD1 PR3MD0 0 0 R W R W PR3 Mode 00 LBSC PCIC module WE7 CBE3 When the bus mode is set to DU via the bus mode pins MODE11 and MODE12 port input pull up MOS On is selected 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 5...

Page 1447: ... On is selected 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 1 0 PR0MD1 PR0MD0 0 0 R W R W PR0 Mode 00 LBSC PCIC module WE4 CBE0 When the bus mode is set to DU via the bus mode pins MODE11 and MODE12 port input pull up MOS On is selected 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On Note The module that uses the pin can be selected by the bu...

Page 1448: ...A5DT 0 R W 4 PA4DT 0 R W 3 PA3DT 0 R W 2 PA2DT 0 R W These bits store output data of a pin which is used as a general purpose output port When the pin functions as a general purpose output port reading the port will read out the value of the corresponding bit of this register When the pin functions as a general purpose input port reading the port will read out the status of the corresponding pin 1...

Page 1449: ...B5DT 0 R W 4 PB4DT 0 R W 3 PB3DT 0 R W 2 PB2DT 0 R W These bits store output data of a pin which is used as a general purpose output port When the pin functions as a general purpose output port reading the port will read out the value of the corresponding bit of this register When the pin functions as a general purpose input port reading the port will read out the status of the corresponding pin 1...

Page 1450: ...al value R W Bit Bit Name Initial value R W Description 7 PC7DT 0 R W 6 PC6DT 0 R W 5 PC5DT 0 R W 4 PC4DT 0 R W 3 PC3DT 0 R W 2 PC2DT 0 R W These bits store output data of a pin which is used as a general purpose output port When the pin functions as a general purpose output port reading the port will read out the value of the corresponding bit of this register When the pin functions as a general ...

Page 1451: ...al value R W Bit Bit Name Initial value R W Description 7 PD7DT 0 R W 6 PD6DT 0 R W 5 PD5DT 0 R W 4 PD4DT 0 R W 3 PD3DT 0 R W 2 PD2DT 0 R W 1 PD1DT 0 R W These bits store output data of a pin which is used as a general purpose output port When the pin functions as a general purpose output port reading the port will read out the value of the corresponding bit of this register When the pin functions...

Page 1452: ...ays be 0 5 PE5DT 0 R W 4 PE4DT 0 R W 3 PE3DT Pin input R W 2 PE2DT 0 R W 1 PE1DT 0 R W 0 PE0DT Pin input R W These bits store output data of a pin which is used as a general purpose output port When the pin functions as a general purpose output port reading the port will read out the value of the corresponding bit of this register When the pin functions as a general purpose input port reading the ...

Page 1453: ...al value R W Bit Bit Name Initial value R W Description 7 PF7DT 0 R W 6 PF6DT 0 R W 5 PF5DT 0 R W 4 PF4DT 0 R W 3 PF3DT 0 R W 2 PF2DT 0 R W These bits store output data of a pin which is used as a general purpose output port When the pin functions as a general purpose output port reading the port will read out the value of the corresponding bit of this register When the pin functions as a general ...

Page 1454: ...al value R W Bit Bit Name Initial value R W Description 7 PG7DT 0 R W 6 PG6DT 0 R W 5 PG5DT 0 R W 4 PG4DT 0 R W 3 PG3DT 0 R W 2 PG2DT 0 R W 1 PG1DT 0 R W These bits store output data of a pin which is used as a general purpose output port When the pin functions as a general purpose output port reading the port will read out the value of the corresponding bit of this register When the pin functions...

Page 1455: ...l value R W Description 7 PH7DT Pin input R W 6 PH6DT Pin input R W 5 PH5DT Pin input R W 4 PH4DT Pin input R W 3 PH3DT Pin input R W 2 PH2DT Pin input R W 1 PH1DT Pin input R W These bits store output data of a pin which is used as a general purpose output port When the pin functions as a general purpose output port reading the port will read out the value of the corresponding bit of this registe...

Page 1456: ...l value R W Description 7 PJ7DT Pin input R W 6 PJ6DT Pin input R W 5 PJ5DT Pin input R W 4 PJ4DT Pin input R W 3 PJ3DT Pin input R W 2 PJ2DT Pin input R W 1 PJ1DT Pin input R W These bits store output data of a pin which is used as a general purpose output port When the pin functions as a general purpose output port reading the port will read out the value of the corresponding bit of this registe...

Page 1457: ...e Initial value R W Description 7 PK7DT 0 R W 6 PK6DT 0 R W 5 PK5DT Pin input R W 4 PK4DT Pin input R W 3 PK3DT Pin input R W 2 PK2DT Pin input R W 1 PK1DT Pin input R W These bits store output data of a pin which is used as a general purpose output port When the pin functions as a general purpose output port reading the port will read out the value of the corresponding bit of this register When t...

Page 1458: ...l value R W Description 7 PL7DT Pin input R W 6 PL6DT Pin input R W 5 PL5DT Pin input R W 4 PL4DT Pin input R W 3 PL3DT Pin input R W 2 PL2DT Pin input R W These bits store output data of a pin which is used as a general purpose output port When the pin functions as a general purpose output port reading the port will read out the value of the corresponding bit of this register When the pin functio...

Page 1459: ...e Initial value R W Description 7 to 2 All 0 R W Reserved These bits are always read as 0 and the write value should always be 0 1 PM1DT 0 R W 0 PM0DT 0 R W These bits store output data of a pin which is used as a general purpose output port When the pin functions as a general purpose output port reading the port will read out the value of the corresponding bit of this register When the pin functi...

Page 1460: ... R W Bit Bit Name Initial value R W Description 7 PN7DT Pin input R W 6 PN6DT Pin input R W 5 PN5DT 0 R W 4 PN4DT 0 R W 3 PN3DT 0 R W 2 PN2DT 0 R W These bits store output data of a pin which is used as a general purpose output port When the pin functions as a general purpose output port reading the port will read out the value of the corresponding bit of this register When the pin functions as a ...

Page 1461: ... should always be 0 5 PP5DT 0 R W 4 PP4DT 0 R W 3 PP3DT 0 R W 2 PP2DT 0 R W 1 PP1DT 0 R W 0 PP0DT 0 R W These bits store output data of a pin which is used as a general purpose output port When the pin functions as a general purpose output port reading the port will read out the value of the corresponding bit of this register When the pin functions as a general purpose input port reading the port ...

Page 1462: ...e should always be 0 4 PQ4DT 0 R W 3 PQ3DT 0 R W 2 PQ2DT 0 R W 1 PQ1DT 0 R W 0 PQ0DT 0 R W These bits store output data of a pin which is used as a general purpose output port When the pin functions as a general purpose output port reading the port will read out the value of the corresponding bit of this register When the pin functions as a general purpose input port reading the port will read out...

Page 1463: ...he write value should always be 0 3 PR3DT 0 R W 2 PR2DT 0 R W 1 PR1DT 0 R W 0 PR0DT 0 R W These bits store output data of a pin which is used as a general purpose output port When the pin functions as a general purpose output port reading the port will read out the value of the corresponding bit of this register When the pin functions as a general purpose input port reading the port will read out ...

Page 1464: ...ster is ignored 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 PE0 PUPR PE3 PUPR R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 7 to 4 All 1 R W Reserved These bits are always read as 1 and the write value should always be 1 3 PE3PUPR 1 R W Pull up of the Port E3 pin can be controlled independently 0 PE3 pull up off 1 PE3 pull up on 2 and 1 All 1 R W Reserved The...

Page 1465: ...en the port H pins are used by the GPIO the setting for this register is ignored 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 PH0 PUPR PH1 PUPR PH2 PUPR PH3 PUPR PH4 PUPR PH5 PUPR PH6 PUPR PH7 PUPR R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 7 PH7PUPR 1 R W 6 PH6PUPR 1 R W 5 PH5PUPR 1 R W 4 PH4PUPR 1 R W 3 PH3PUPR 1 R W 2 PH2PUPR 1 R W 1 PH1PUPR 1 R W Pull u...

Page 1466: ...en the port J pins are used by the GPIO the setting for this register is ignored 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 PJ0 PUPR PJ1 PUPR PJ2 PUPR PJ3 PUPR PJ4 PUPR PJ5 PUPR PJ6 PUPR PJ7 PUPR R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 7 PJ7PUPR 1 R W 6 PJ6PUPR 1 R W 5 PJ5PUPR 1 R W 4 PJ4PUPR 1 R W 3 PJ3PUPR 1 R W 2 PJ2PUPR 1 R W 1 PJ1PUPR 1 R W Pull u...

Page 1467: ...en the port K pins are used by the GPIO the setting for this register is ignored 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 PK0 PUPR PK1 PUPR PK2 PUPR PK3 PUPR PK4 PUPR PK5 PUPR PK6 PUPR PK7 PUPR R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 7 PK7PUPR 1 R W 6 PK6PUPR 1 R W 5 PK5PUPR 1 R W 4 PK4PUPR 1 R W 3 PK3PUPR 1 R W 2 PK2PUPR 1 R W 1 PK1PUPR 1 R W Pull u...

Page 1468: ...en the port L pins are used by the GPIO the setting for this register is ignored 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 PL0 PUPR PL1 PUPR PL2 PUPR PL3 PUPR PL4 PUPR PL5 PUPR PL6 PUPR PL7 PUPR R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 7 PL7PUPR 1 R W 6 PL6PUPR 1 R W 5 PL5PUPR 1 R W 4 PL4PUPR 1 R W 3 PL3PUPR 1 R W 2 PL2PUPR 1 R W 1 PL1PUPR 1 R W Pull u...

Page 1469: ...ed by peripheral modules When the port M pins are used by the GPIO the setting for this register is ignored 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 PM0 PUPR PM1 PUPR R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 7 to 2 All 1 R W Reserved These bits are always read as 1 and the write value should always be 1 1 PM1PUPR 1 R W 0 PM0PUPR 1 R W Pull up of each ...

Page 1470: ...en the port N pins are used by the GPIO the setting for this register is ignored 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 PN0 PUPR PN1 PUPR PN2 PUPR PN3 PUPR PN4 PUPR PN5 PUPR PN6 PUPR PN7 PUPR R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 7 PN7PUPR 1 R W 6 PN6PUPR 1 R W 5 PN5PUPR 1 R W 4 PN4PUPR 1 R W 3 PN3PUPR 1 R W 2 PN2PUPR 1 R W 1 PN1PUPR 1 R W Pull u...

Page 1471: ...to 3 All 1 R W Reserved These bits are always read as 1 and the write value should always be 1 2 RDYPUP 1 R W Controls pull up of the RDY pin 0 RDY pull up off 1 RDY pull up on 1 and 0 All 1 R W Reserved These bits are always read as 1 and the write value should always be 1 28 2 41 Input Pin Pull Up Control Register 2 PPUPR2 PPUPR2 is a 16 bit readable writable register that performs the pull up c...

Page 1472: ...up of the SCIF2_RXD SIOF_RXD pin 0 SCIF2_RXD SIOF_RXD pull up off 1 SCIF2_RXD SIOF_RXD pull up on 4 NMIPUP 1 R W Controls pull up of the NMI pin 0 NMI pull up off 1 NMI pull up on 3 IRL3PUP 1 R W Controls pull up of the IRL3 pin 0 IRL3 pull up off 1 IRL3 pull up on 2 IRL2PUP 1 R W Controls pull up of the IRL2 pin 0 IRL2 pull up off 1 IRL2 pull up on 1 IRL1PUP 1 R W Controls pull up of the RL1 pin ...

Page 1473: ...L0 P1M SEL1 P1M SEL9 P1M SEL11 P1M SEL10 P1M SEL7 P1M SEL8 P1M SEL4 P1M SEL5 P1M SEL6 P1M SEL12 P1M SEL13 P1M SEL15 P1M SEL14 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 15 P1MSEL15 0 R W Out of the modules STATUS and DMAC selects the one which uses the pins STATUS0 DRAK0 and STATUS1 DRAK1 0 STATUS 1 DMAC 14 P1MSE...

Page 1474: ...ses the pins MODE12 DRAK3 CE2B and DRAK2 CE2A 0 DMAC 1 LBSC At power on reset by the PRESET pin MODE12 is selected 9 PMSEL9 0 R W Out of the modules TMU and LBSC selects the one which uses the MODE13 TCLK IOIS16 pin 0 TMU 1 LBSC At power on reset by the PRESET pin MODE13 is selected 8 7 P1MSEL8 P1MSEL7 0 0 R W R W Out of the modules SCIF 0 HSPI and FLCTL selects the one which uses the pins SCIF0_T...

Page 1475: ... the pins SIOF_SCK HAC0_BITCLK SSIO_CLK SIOF_MCLK HAC_RES SIOF_SYNC HAC0_SYNC SSIO_WS SIOF_RXD HAC0_SDIN SSIO_SCK and SIOF_TXD HAC0_SDOUT SSIO_SDATA 00 SIOF 01 HAC 10 SSI 0 11 Setting prohibited When 10 is selected the SIOF_MCLK HAC_RES pin is used as HAC_RES 2 1 P1MSEL2 P1MSEL1 0 0 R W R W Out of the modules SCIF 5 HAC 1 SSI 1 selects the one which uses the pins HAC1_BITCLK SSI1_CLK SCIF5_TXD HAC...

Page 1476: ...1 and P1MSEL6 and P1MSEL5 must be specified without contradiction The settings of the registers when the SIOF is used are shown in the following Correct operation of the SIOF cannot be guaranteed by the settings other than the following Register Bit Name When the Following SIOF Pin Groups Are Used SIOF_SCK HAC0_BITCLK SSIO_CLK SIOF_MCLK HAC_RES SIOF_SYNC HAC0_SYNC SSIO_WS SIOF_RXD HAC0_SDIN SSIO_S...

Page 1477: ...n be used to select the module that uses multiplexed pins For details of pin multiplexing see table 28 1 This register is valid only when peripheral modules are selected by PACR to PHCR PJCR to PNCR PPCR to PRCR of the GPIO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P2M SEL2 P2M SEL0 P2M SEL1 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial val...

Page 1478: ...1MSEL4 and 3 SIOF_SCK HAC0_BITCLK SSIO_CLK SIOF_MCLK HAC_RES SIOF_SYNC HAC0_SYNC SSIO_WS SIOF_RXD HAC0_SDIN SSIO_SCK SIOF_TXD HAC0_SDOUT SSIO_SDATA 1 Uses the SIOF pin selected by P1MSEL12 11 and P1MSEL6 and 5 DACK3 SCIF2_SCK MMCDATA SIOF_SCK DACK2 SCIF2_TXD MMCCMD SIOF_TXD SCIF2_RXD SIOF_RXD MODE5 SIOF_MCLK MODE6 SIOF_SYNC Note At power on reset by the PRESET pin MODE5 and MODE6 are selected 0 P2...

Page 1479: ...rt pull up control registers PEPUPR PHPUPR PJPUPR PKPUPR PLPUPR PMPUPR and PNPUPR peripheral module select register 1 P1MSELR peripheral module select register 2 P2MSELR and bus mode pin MODE11 and MODE12 are invalid Figure 28 1 shows an example of operation timing diagram when port A is used as an output port The output data is written to port data registers PADR to PRDR and then the data is outp...

Page 1480: ...In this case for each input port the settings of port pull up control registers PEPUPR PHPUPR PJPUPR PKPUPR PLPUPR PMPUPR and PNPUPR peripheral module select register 1 P1MSELR peripheral module select register 2 P2MSELR and bus mode pin MODE11 and MODE12 are invalid Figure 28 2 shows an example of operation timing diagram when port A is used as an input port The input data from each port can be r...

Page 1481: ...lect register 2 P2MSELR 2 When an input or input output pin is used it is necessary to set the pull up MOS for each pin by using the port pull up control registers PEPUPR PHPUPR PJPUPR PKPUPR PLPUPR PMPUPR and PNPUPR Write B 0 when the pull up MOS is off or B 1 when the pull up MOS is on to the corresponding bit When an output port is used the pull up MOS is off regardless of the settings of the p...

Page 1482: ...28 General Purpose I O Ports GPIO Rev 1 00 Jan 10 2008 Page 1452 of 1658 REJ09B0261 0100 ...

Page 1483: ... Sequential break involves two cases such that the channel 0 break condition is satisfied in a certain bus cycle and then the channel 1 break condition is satisfied in a different bus cycle and vice versa Address When 40 bits containing ASID and 32 bit address are compared with the specified value all the ASID bits can be compared or masked 32 bit address can be masked bit by bit allowing the user...

Page 1484: ...CRR0 CAR0 CAMR0 CBR1 CRR1 CAR1 CAMR1 CDR1 CDMR1 CETR1 CCMFR CBCR SAB SDB Legend ASID comparator ASID comparator ASID Match condition setting register 0 Match operation setting register 0 Match address setting register 0 Match address mask setting register 0 Match condition setting register 1 Match operation setting register 1 Match address setting register 1 Match address mask setting register 1 M...

Page 1485: ...BR1 R W H FF200020 H 1F200020 32 Match operation setting register 1 CRR1 R W H FF200024 H 1F200024 32 Match address setting register 1 CAR1 R W H FF200028 H 1F200028 32 Match address mask setting register 1 CAMR1 R W H FF20002C H 1F20002C 32 Match data setting register 1 CDR1 R W H FF200030 H 1F200030 32 Match data mask setting register 1 CDMR1 R W H FF200034 H 1F200034 32 Execution count break re...

Page 1486: ...defined Retained Retained Match data setting register 1 CDR1 Undefined Retained Retained Match data mask setting register 1 CDMR1 Undefined Retained Retained Execution count break register 1 CETR1 Undefined Retained Retained Channel match flag register CCMFR H 00000000 Retained Retained Break control register CBCR H 00000000 Retained Retained The access size must be the same as the control registe...

Page 1487: ... 0 0 0 0 0 0 0 MFE AIE MFI AIV SZ CD ID RW CE R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R W R W R W R R R R R W R W R W R W R R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 MFE 0 R W Match Flag Enable Specifies whether or not to include the match flag...

Page 1488: ... the condition of CCRMF MF0 0 23 to 16 AIV All 0 R W ASID Specify Specifies the ASID value to be included in the match conditions 15 0 R Reserved For read write in this bit refer to General Precautions on Handling of Product 14 to 12 SZ All 0 R W Operand Size Select Specifies the operand size to be included in the match conditions This bit is valid only when the operand access cycle is specified a...

Page 1489: ...erved For read write in this bit refer to General Precautions on Handling of Product 2 1 RW All 0 R W Bus Command Select Specifies the read write cycle as the match condition This bit is valid only when the operand access cycle is specified as a match condition 00 Read cycle or write cycle 01 Read cycle 10 Write cycle 11 Read cycle or write cycle 0 CE 0 R W Channel Enable Validates invalidates the...

Page 1490: ...condition is determined to be satisfied 0 The match flag is not included in the match conditions thus not checked 1 The match flag is included in the match conditions 30 AIE 0 R W ASID Enable Specifies whether or not to include the ASID specified by the AIV bit of this register in the match conditions 0 The ASID is not included in the match conditions thus not checked 1 The ASID is included in the...

Page 1491: ...t is valid only when the operand access cycle is specified as a match condition 000 The operand size is not included in the match condition thus not checked any operand size specifies the match condition 1 001 Byte access 010 Word access 011 Longword access 100 Quadword access 2 Others Reserved setting prohibited 11 ETBE 0 R W Execution Count Value Enable Specifies whether or not to include the ex...

Page 1492: ...read write cycle as the match condition This bit is valid only when the operand access cycle is specified as a match condition 00 Read cycle or write cycle 01 Read cycle 10 Write cycle 11 Read cycle or write cycle 0 CE 0 R W Channel Enable Validates invalidates the channel If this bit is 0 all the other bits in this register are invalid 0 Invalidates the channel 1 Validates the channel Notes 1 If ...

Page 1493: ... R R R R R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 14 All 0 R Reserved For read write in this bit refer to General Precautions on Handling of Product 13 1 R Reserved This bit is always read as 1 The write value should always be 1 12 to 2 All 0 R Reserved For read write in this bit refer to General Precautions on Handling of Product 1 PCB 0...

Page 1494: ...on Handling of Product 13 1 R Reserved This bit is always read as 1 The write value should always be 1 12 to 2 All 0 R Reserved For read write in this bit refer to General Precautions on Handling of Product 1 PCB 0 R W PC Break Select Specifies either before or after instruction execution as the break timing for the instruction fetch cycle This bit is invalid for breaks other than ones for the ins...

Page 1495: ...lue R W Bit Bit Name Initial Value R W Description 31 to 0 CA Undefined R W Compare Address Specifies the address to be included in the break conditions When the operand bus has been specified using the CBR0 register specify the SAB address in CA 31 0 CAR1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CA CA R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6...

Page 1496: ...3 22 21 20 19 18 17 16 CAM CAM R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 0 CAM Undefined R W Compare Address Mask Specifies the bits to be masked among the address bits which are spec...

Page 1497: ... R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 0 CAM Undefined R W Compare Address Mask Specifies the bits to be masked among the address bits which are specified using the CAR1 register Set the bits to be masked to 1 0 Address bits CA n are included in the break condition 1 Address bits CA n are masked ...

Page 1498: ...alue in CD 31 0 Table 29 3 Settings for Match Data Setting Register Bus and Size Selected Using CBR1 CD 31 24 CD 23 16 CD 15 8 CD 7 0 Operand bus byte Don t care Don t care Don t care SDB7 to SDB0 Operand bus word Don t care Don t care SDB15 to SDB8 SDB7 to SDB0 Operand bus longword SDB31 to SDB24 SDB23 to SDB16 SDB15 to SDB8 SDB7 to SDB0 Notes 1 If the data value is included in the match conditio...

Page 1499: ... R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 0 CDM Undefined R W Compare Data Value Mask Specifies the bits to be masked among the data value bits specified using the CDR1 register Set the ...

Page 1500: ...ted by one every time the channel is hit When the channel is hit after the register value reaches H 001 a break occurs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CET R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 R R R R R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initia...

Page 1501: ... 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MF1 MF0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 2 All 0 R Reserved For read write in this bit refer to General Precautions on Handling of Product 1 M...

Page 1502: ... 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBDE R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 1 All 0 R Reserved For read write in this bit refer to General Precautions on Handling of Product 0 UBDE 0 R W User Break Debuggin...

Page 1503: ...in contrast to address All types of operand access are classified into read or write access Special care must be taken in using the following instructions PREF OCBP and OCBWB Instructions for a read access MOVCA L and OCBI Instructions for a write access TAS B Instruction for a single read access or a single write access The operand access accompanying the PREF OCBP OCBWB and OCBI instructions is ...

Page 1504: ... condition is satisfied as a result of fetching the instruction using the match operation setting register CRR0 or CRR1 After having set all the bits in the match condition setting register except the CE bit and the other necessary registers set the CE bit and read the match condition setting register again This ensures that the set values in the control registers are valid for the subsequent inst...

Page 1505: ...ak is requested when the instruction is fetched and determined to be executed Therefore this function cannot be used for the instructions which are fetched through overrun i e the instructions fetched during branching or making transition to the interrupt routine but not executed For priorities of pre instruction execution break and the other exceptions refer to section 5 Exception Handling If pre...

Page 1506: ...ess to address H 00001002 Byte access to address H 00001003 2 When the data value is included in the channel 1 match conditions If the data value is included in the match conditions be sure to select the quadword longword word or byte as the operand size using the operand size select bit SZ of the match condition setting register CBR1 and also set the match data setting register CDR1 and the match...

Page 1507: ...he MFE bit of the match condition setting register and the BIE bit of the match operation setting register of the first channel in the sequence and set the MFE bit and specify the number of the second channel in the sequence using the MFI bit in the match condition setting register of the second channel in the sequence If the sequential break condition is set the condition match flag is set every ...

Page 1508: ...ondition is satisfied at the operand access cycle for the first channel in the sequence whereas the match condition is satisfied at the instruction fetch cycle for the second channel in the sequence Instruction B is 0 to five instructions after instruction A Sequential operation is not guaranteed Instruction B is six or more instructions after instruction A Sequential operation is guaranteed When ...

Page 1509: ...for the delayed branch instruction or its delayed slot these instructions are executed and the address of the branch destination is saved in the SPC 3 When the operand access address only is specified as the match condition The address of the instruction immediately after the instruction which has satisfied the break conditions is saved in the SPC The instruction which has satisfied the match cond...

Page 1510: ...s indicated by the VBR offset Figure 29 2 shows the flowchart of the user break debugging support function SPC PC SSR SR SR BL B 1 SR MD B 1 SR RB B 1 Exception interrupt is generated Exception Exception interrupt trap Trap Interrupt PC H A000 0000 PC VBR vector offset Execute RTE instruction PC SPC SR SSR SGR R15 PC DBR Debugging program R15 SGR STC instruction Reset exception CBCR UBDE 1 user br...

Page 1511: ...on fetch before executing instruction ASID data values and execution count are not included in the conditions With the above settings the user break occurs after executing the instruction at address H 00000404 or before executing the instruction at address H 00008010 to H 00008016 Example 1 2 Register settings CBR0 H 40800013 CRR0 H 00002000 CAR0 H 00037226 CAMR0 H 00000000 CBR1 H C0700013 CRR1 H ...

Page 1512: ...H 00000000 Bus cycle Instruction fetch before executing the instruction ASID data values and execution count are not included in the conditions With the above settings the user break occurs for channel 0 before executing the instruction at address H 00027128 No user break occurs for channel 1 since the instruction fetch is executed only at even addresses Example 1 4 Register settings CBR0 H 408000...

Page 1513: ... Channel 1 Address H 00001000 Address mask H 00000000 Data H 00000000 Data mask H 00000000 Execution count H 00000005 Bus cycle Instruction fetch before executing the instruction Execution count 5 ASID and data values are not included in the conditions With the above settings the user break occurs for channel 0 before executing the instruction at address H 00000500 The user break occurs for channe...

Page 1514: ... CBR1 H 4070A025 CRR1 H 00002001 CAR1 H 000ABCDE CAMR1 H 000000FF CDR1 H 0000A512 CDMR1 H 00000000 CETR1 H 00000000 CBCR H 00000000 Specified conditions Independent for channels 0 and 1 Channel 0 Address H 00123456 Address mask H 00000000 ASID H 80 Bus cycle Operand bus operand access and read operand size is not included in the conditions Channel 1 Address H 000ABCDE Address mask H 000000FF ASID ...

Page 1515: ...is not necessary At only last updating the UBC register execute one of these methods 2 The PCB bit of the CRR0 and CRR1 registers is valid only when the instruction fetch is specified as the match condition 3 If the sequential break conditions are set the sequential break conditions are satisfied when the conditions for the first and second channels in the sequence are satisfied in this order Ther...

Page 1516: ...ependently for channels 0 and 1 resulting in identical SPC values for both of the breaks the user break occurs only once However the condition match flags are set for both channels For example Instruction at address 110 post instruction execution break for instruction fetch for channel 0 SPC 112 CCMFR MF0 1 Instruction at address 112 pre instruction execution break for instruction fetch for channe...

Page 1517: ... pins and a signal MPMD for the chip mode select pin In the H UDI in this LSI the boundary scan test access port TAP controller is separated from the TAP controller for other H UDI function control When the TRST is asserted including when the power is turned on the boundary scan TAP controller is selected Therefore the switching command should be input to use the H UDI functions The boundary scan ...

Page 1518: ...0 TDO TDI TRST TMS TCK SDIR ASEBRK BRKACK Boundary scan TAP controller Break controller TAP controller Decoder SDBSR SDBPR SDINT AUDSYNC AUDCK AUDATA3 AUDATA2 AUDATA1 AUDATA0 Trace controller Pin multiplexer Peripheral bus Shift register Interrupt reset Figure 30 1 Block Diagram of H UDI ...

Page 1519: ...et Input H UDI Reset Input Pin This signal is received without relating to TCK The JTAG interface circuit is reset when this signal is at a low level Regardless of whether JTAG is used or not TRST should be set to a low level during a specific period when power is turned on This does not conform to the IEEE standard Fixed to ground or connected to the PRESET pin 3 TDI Data input Input Data Input P...

Page 1520: ... controlled independently 3 This pin should be connected to ground or connected to the same signal as the PRESET or a pin which operates in the same way as the PRESET pin When this pin is connected to ground the following problem occurs Since the TRST pin is pulled up within this LSI weak current runs when the pin is connected to ground outside the LSI The current depends on a resistance of the pu...

Page 1521: ...PR Table 30 3 Register Configuration 2 H UDI Side Register Name Abbreviation R W Size Sync Clock Instruction register SDIR R W 1 32 Pck Interrupt source register SDINT W 2 32 Pck Boundary scan register SDBSR R W Bypass register SDBPR R W 1 Notes 1 The read value from the H UDI is always fixed to H FFFF FFFD 2 1 can be written to the LSB by the H UDI interrupt command Table 30 4 Register States in ...

Page 1522: ...10 Initial state Other than above Setting prohibited 7 to 0 All 1 R Reserved These bits are always read as 1 30 3 2 Interrupt Source Register SDINT SDINT is a 16 bit register that can be read from or written to by the CPU If the H UDI interrupt command Update IR is set to SDIR the INTREQ bit is set to 1 When an H UDI interrupt command is set in SDIR SDINT is connected between the TDI and TDO pins ...

Page 1523: ...ASS command is set to the boundary scan TAP controller SDBPR is connected between the TDI and TDO pins This register cannot be accessed through the CPU This register is not initialized by a power on reset or assertion of TRST but it is initialized to 0 by the Capture DR state 30 3 4 Boundary Scan Register SDBSR SDBSR is a register that supports the JTAG boundary scan mode SDBSR is a shift register...

Page 1524: ...EQ Output 543 DACK2 TXD2 MMCCMD SIOF TXD1 Control 517 STATUS1 DRAK1 Input 542 DACK2 TXD2 MMCCMD SIOF TXD1 Output 516 STATUS1 DRAK1 Control 541 DACK1 Input 515 STATUS1 DRAK1 Output 540 DACK1 Control 514 STATUS0 DRAK0 Input 539 DACK1 Output 513 STATUS0 DRAK0 Control 538 DACK0 Input 512 STATUS0 DRAK0 Output 537 DACK0 Control 511 IRL3 Input 536 DACK0 Output 510 IRL3 Control 535 DREQ3 INTC Input 509 IR...

Page 1525: ...MCCLK Output 455 PAR Control 486 GNT2 Input 454 PAR Output 485 GNT2 Control 453 DEVSEL DCLKOUT Input 484 GNT2 Output 452 DEVSEL DCLKOUT Control 483 GNT1 Input 451 DEVSEL DCLKOUT Output 482 GNT1 Control 450 LOCK ODDF Input 481 GNT1 Output 449 LOCK ODDF Control 480 REQ3 MMCCD Input 448 LOCK ODDF Output 479 REQ3 MMCCD Control 447 IDSEL Input 478 REQ3 MMCCD Output 446 IDSEL Control 477 REQ2 Input 445 ...

Page 1526: ...Input 391 D53 AD21 Output 422 D63 AD31 Control 390 D52 AD20 Input 421 D63 AD31 Output 389 D52 AD20 Control 420 D62 AD30 Input 388 D52 AD20 Output 419 D62 AD30 Control 387 D51 AD19 Input 418 D62 AD30 Output 386 D51 AD19 Control 417 D61 AD29 Input 385 D51 AD19 Output 416 D61 AD29 Control 384 D50 AD18 Input 415 D61 AD29 Output 383 D50 AD18 Control 414 D60 AD28 Input 382 D50 AD18 Output 413 D60 AD28 C...

Page 1527: ...330 D32 AD0 DR0 Input 360 D42 AD10 DG4 Input 329 D32 AD0 DR0 Control 359 D42 AD10 DG4 Control 328 D32 AD0 DR0 Output 358 D42 AD10 DG4 Output 327 CLKOUTENB Input 357 D41 AD9 DG3 Input 326 CLKOUTENB Control 356 D41 AD9 DG3 Control 325 CLKOUTENB Output 355 D41 AD9 DG3 Output 324 CLKOUT Input 354 D40 AD8 DG2 Input 323 CLKOUT Control 353 D40 AD8 DG2 Control 322 CLKOUT Output 352 D40 AD8 DG2 Output 321 ...

Page 1528: ...267 A22 Input 298 RD Output 266 A22 Control 297 CS6 Input 265 A22 Output 296 CS6 Control 264 A21 Input 295 CS6 Output 263 A21 Control 294 CS5 Input 262 A21 Output 293 CS5 Control 261 A20 Input 292 CS5 Output 260 A20 Control 291 CS4 Input 259 A20 Output 290 CS4 Control 258 A19 Input 289 CS4 Output 257 A19 Control 288 CS3 Input 256 A19 Output 287 CS3 Control 255 A18 Input 286 CS3 Output 254 A18 Cont...

Page 1529: ...utput 203 A1 Control 234 A11 Input 202 A1 Output 233 A11 Control 201 A0 Input 232 A11 Output 200 A0 Control 231 A10 Input 199 A0 Output 230 A10 Control 198 D31 Input 229 A10 Output 197 D31 Control 228 A9 Input 196 D31 Output 227 A9 Control 195 D30 Input 226 A9 Output 194 D30 Control 225 A8 Input 193 D30 Output 224 A8 Control 192 D29 Input 223 A8 Output 191 D29 Control 222 A7 Input 190 D29 Output 2...

Page 1530: ...22 Input 139 D12 Output 170 D22 Control 138 D11 Input 169 D22 Output 137 D11 Control 168 D21 Input 136 D11 Output 167 D21 Control 135 D10 Input 166 D21 Output 134 D10 Control 165 D20 Input 133 D10 Output 164 D20 Control 132 D9 Input 163 D20 Output 131 D9 Control 162 D19 Input 130 D9 Output 161 D19 Control 129 D8 Input 160 D19 Output 128 D8 Control 159 D18 Input 127 D8 Output 158 D18 Control 126 D7...

Page 1531: ...ol 103 D0 Output 72 MODE5 SIOFMCLK1 Output 102 MRESETOUT IRQOUT Input 71 MODE4 TXD3 FCLE Input 101 MRESETOUT IRQOUT Control 70 MODE4 TXD3 FCLE Control 100 MRESETOUT IRQOUT Output 69 MODE4 TXD3 FCLE Output 99 MODE14 Input 68 MODE3 IRL7 FD7 Input 98 MODE13 TCLK IOIS16 Input 67 MODE3 IRL7 FD7 Control 97 MODE13 TCLK IOIS16 Control 66 MODE3 IRL7 FD7 Output 96 MODE13 TCLK IOIS16 Output 65 MODE2 IRL6 FD6...

Page 1532: ...RTS0 HSPI CS FSE Input 42 TXD HAC0 SDOUT SSI0 SDATA Output 13 RTS0 HSPI CS FSE Control 41 RXD HAC0 SDIN SSI0 SCK Input 12 RTS0 HSPI CS FSE Output 40 RXD HAC0 SDIN SSI0 SCK Control 11 SCK0 HSPI CLK FRE Input 39 RXD HAC0 SDIN SSI0 SCK Output 10 SCK0 HSPI CLK FRE Control 38 SYNC HAC0 SYNC SSI0 WS Input 9 SCK0 HSPI CLK FRE Output 37 SYNC HAC0 SYNC SSI0 WS Control 8 RXD0 HSPI RX FR B Input 36 SYNC HAC0...

Page 1533: ...SYNC AUDCK AUDATA3 to AUDATA0 and MPMD are out of the scope of the boundary scan test DDRIF related pins are out of the scope of the boundary scan test During the boundary scan IDCODE EXTEST SAMPLE PRELOAD BYPASS and H UDI switching command the maximum frequency of TCK is 10 MHz The access size from the H UDI to the boundary scan TAP controller is 8 bits The commands supported by the boundary scan...

Page 1534: ... H UDI is used TRST is asserted Boundary scan TAP controller External pins H UDI selection Status Note The hatched sections represent the functions connected to the external pins Status H UDI switching command B 00001000 when Shift IR state 8 cycles input of last 8 cycles is valid Switchover is determined at falling of first tck cycle after the boundary scan TAP controller has entered the Run Test...

Page 1535: ...d at the falling edge of TCK The TDO value is changed at the falling edge of TCK The TDO is in the high impedance state other than in the Shift DR or Shift IR state When TRST is changed to 0 the transition to the Test Logic Reset state is performed asynchronously with the TCK signal Test Logic Reset Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Select DR Scan Run Test Idle 1 0 0 0 0 1 1...

Page 1536: ...ommand is set the reset signal is asserted in the chip after four cycles at a peripheral clock Pck When the H UDI reset negate command is set the reset signal is negated in the chip after a reset hold period The minimum period is 17 cycles at a peripheral clock and the maximum period is 42 cycles at a peripheral clock For details see section 15 Clock Pulse Generator CPG Note The WDT RST module is ...

Page 1537: ...NTREQ bit in SDINT is set to 1 after setting the command Update IRQ Since the interrupt request signal is not negated unless the INTREQ bit is cleared to 0 by software the interrupt request cannot be missed While the H UDI interrupt command is set in SDIR SDINT is connected between the TDI and TDO pins For values read through the TDO pin and others see section 30 3 2 Interrupt Source Register SDIN...

Page 1538: ...30 User Debugging Interface H UDI Rev 1 00 Jan 10 2008 Page 1508 of 1658 REJ09B0261 0100 ...

Page 1539: ...Since this is a summary parts of the descriptions along with the notes have been omitted For details on the registers refer to the descriptions in the corresponding sections Notes 1 Access to undefined and reserved addresses is prohibited 2 Access in an access unit other than that specified in this list is prohibited 3 The register addresses are given as the P4 area address the P4 area of the virt...

Page 1540: ... register PTEA R W H FF00 0034 H 1F00 0034 32 Cache Cache control register CCR R W H FF00 001C H 1F00 001C 32 Queue address control register 0 QACR0 R W H FF00 0038 H 1F00 0038 32 Queue address control register 1 QACR1 R W H FF00 003C H 1F00 003C 32 On chip memory control register RAMCR R W H FF00 0074 H 1F00 0074 32 L memory L memory transfer source address register 0 LSA0 R W H FF000050 H 1F0000...

Page 1541: ...rrupt priority register 9 INT2PRI9 R W H FFD4 0024 H 1FD4 0024 32 Interrupt source register not affected by the mask state INT2A0 R H FFD4 0030 H 1FD4 0030 32 Interrupt source register affected by the mask state INT2A1 R H FFD4 0034 H 1FD4 0034 32 Interrupt mask register INT2MSKR R W H FFD4 0038 H 1FD4 0038 32 Interrupt mask clear register INT2MSKCLR R W H FFD4 003C H 1FD4 003C 32 On chip module i...

Page 1542: ...ter CS6WCR R W H FF80 2068 H 1F80 2068 32 CS5 PCMCIA Control Register CS5PCR R W H FF80 2070 H 1F80 2070 32 CS6 PCMCIA Control Register CS6PCR R W H FF80 2080 H 1F80 2080 32 DDR2IF DBSC2 status register DBSTATE R H FE80 000C H 1E80 000C 32 SDRAM operation enable register DBEN R W H FE80 0010 H 1E80 0010 32 SDRAM command control register DBCMDCNT R W H FE80 0014 H 1E80 0014 32 SDRAM configuration s...

Page 1543: ...ister PCISUB R W H FE04 000A H 1E04 000A 32 16 8 PCI base class code register PCIBCC R W H FE04 000B H 1E04 000B 32 16 8 PCI cache line size register PCICLS R H FE04 000C H 1E04 000C 32 16 8 PCI latency timer register PCILTM R W H FE04 000D H 1E04 000D 32 16 8 PCI header type register PCIHDR R H FE04 000E H 1E04 000E 32 16 8 PCI BIST register PCIBIST R H FE04 000F H 1E04 000F 32 16 8 PCI I O base ...

Page 1544: ... 0100 H 1E04 0100 32 16 8 PCI local space register 0 PCILSR0 R W H FE04 0104 H 1E04 0104 32 16 8 PCI local space register 1 PCILSR1 R W H FE04 0108 H 1E04 0108 32 16 8 PCI local address register 0 PCILAR0 R W H FE04 010C H 1E04 010C 32 16 8 PCI local address register 1 PCILAR1 R W H FE04 0110 H 1E04 0110 32 16 8 PCI interrupt register PCIIR R WC H FE04 0114 H 1E04 0114 32 16 8 PCI interrupt mask r...

Page 1545: ...ister PCIPDR R W H FE04 0220 H 1E04 0220 32 16 8 DMAC DMA source address register 0 SAR0 R W H FC80 8020 H 1C80 8020 32 DMA destination address register 0 DAR0 R W H FC80 8024 H 1C80 8024 32 DMA transfer count register 0 TCR0 R W H FC80 8028 H 1C80 8028 32 DMA channel control register 0 CHCR0 R W 3 H FC80 802C H 1C80 802C 32 DMA source address register 1 SAR1 R W H FC80 8030 H 1C80 8030 32 DMA des...

Page 1546: ...38 32 DMA source address register B2 SARB2 R W H FC80 8140 H 1C80 8140 32 DMA destination address register B2 DARB2 R W H FC80 8144 H 1C80 8144 32 DMA transfer count register B2 TCRB2 R W H FC80 8148 H 1C80 8148 32 DMA source address register B3 SARB3 R W H FC80 8150 H 1C80 8150 32 DMA destination address register B3 DARB3 R W H FC80 8154 H 1C80 8154 32 DMA transfer count register B3 TCRB3 R W H F...

Page 1547: ...stination address register 11 DAR11 R W H FCC0 8084 H 1CC0 8084 32 DMA transfer count register 11 TCR11 R W H FCC0 8088 H 1CC0 8088 32 DMA channel control register 11 CHCR11 R W 3 H FCC0 808C H 1CC0 808C 32 DMA source address register B6 SARB6 R W H FCC0 8120 H 1CC0 8120 32 DMA destination address register B6 DARB6 R W H FCC0 8124 H 1CC0 8124 32 DMA transfer count register B6 TCRB6 R W H FCC0 8128...

Page 1548: ...010 H 1FCC 0010 32 Watchdog timer base counter WDTBCNT R H FFCC 0018 H 1FCC 0018 32 TMU Timer start register 0 TSTR0 R W H FFD8 0004 H 1FD8 0004 8 Timer constant register 0 TCOR0 R W H FFD8 0008 H 1FD8 0008 32 Timer counter 0 TCNT0 R W H FFD8 000C H 1FD8 000C 32 Timer control register 0 TCR0 R W H FFD8 0010 H 1FD8 0010 16 Timer constant register 1 TCOR1 R W H FFD8 0014 H 1FD8 0014 32 Timer counter...

Page 1549: ... start position register VDSR R W H FFF80048 H 1FF80048 32 Vertical display end position register VDER R W H FFF8004C H 1FF8004C 32 Horizontal scan period register HCR R W H FFF80050 H 1FF80050 32 Horizontal synchronous pulse width register HSWR R W H FFF80054 H 1FF80054 32 Vertical scan period register VCR R W H FFF80058 H 1FF80058 32 Vertical synchronous position register VSPR R W H FFF8005C H 1...

Page 1550: ...tart position register P1WASPR R W H FFF80138 H 1FF80138 32 Plane 1 wrap around memory width register P1WAMWR R W H FFF8013C H 1FF8013C 32 Plane 1 blinking period register P1BTR R W H FFF80140 H 1FF80140 32 Plane 1 transparent color 1 register P1TC1R R W H FFF80144 H 1FF80144 32 Plane 1 transparent color 2 register P1TC2R R W H FFF80148 H 1FF80148 32 Plane 1 memory length register P1MLR R W H FFF8...

Page 1551: ...area start address 1 register P3DSA1R R W H FFF80324 H 1FF80324 32 Plane 3 start position X register P3SPXR R W H FFF80330 H 1FF80330 32 Plane 3 start position Y register P3SPYR R W H FFF80334 H 1FF80334 32 Plane 3 wrap around start position register P3WASPR R W H FFF80338 H 1FF80338 32 Plane 3 wrap around memory width register P3WAMWR R W H FFF8033C H 1FF8033C 32 Plane 3 blinking period register ...

Page 1552: ...y position X register P5DPXR R W H FFF80518 H 1FF80518 32 Plane 5 display position Y register P5DPYR R W H FFF8051C H 1FF8051C 32 Plane 5 display area start address 0 register P5DSA0R R W H FFF80520 H 1FF80520 32 Plane 5 display area start address 1 register P5DSA1R R W H FFF80524 H 1FF80524 32 Plane 5 start position X register P5SPXR R W H FFF80530 H 1FF80530 32 Plane 5 start position Y register ...

Page 1553: ...H FFF80648 H 1FF80648 32 Plane 6 memory length register P6MLR R W H FFF80650 H 1FF80650 32 Color palette 1 register 000 CP1_000R R W H FFF81000 H 1FF81000 32 Color palette 1 register 255 CP1_255R R W H FFF813FC H 1FF813FC 32 Color palette 2 register 000 CP2_000R R W H FFF82000 H 1FF82000 32 Color palette 2 register 255 CP2_255R R W H FFF823FC H 1FF823FC 32 Color palette 3 register 000 CP3_000R R W...

Page 1554: ...input UV padding size setting register CLIUVPR R W H FE40 1018 H 1E40 1018 32 CL output padding size setting register CLOPR R W H FE40 101C H 1E40 101C 32 CL palette pointer setting register CLPLPR R W H FE40 1020 H 1E40 1020 32 MC command FIFO MCCF W H FE40 2000 H 1E40 2000 32 MC status register MCSR R H FE40 2004 H 1E40 2004 32 MC frame width setting register MCWR R W H FE40 2008 H 1E40 2008 32 ...

Page 1555: ... register 1 SCSMR1 R W H FFEB 0000 H 1FEB 0000 16 Bit rate register 1 SCBRR1 R W H FFEB 0004 H 1FEB 0004 8 Serial control register 1 SCSCR1 R W H FFEB 0008 H 1FEB 0008 16 Transmit FIFO data register 1 SCFTDR1 W H FFEB 000C H 1FEB 000C 8 Serial status register 1 SCFSR1 R W 5 H FFEB 0010 H 1FEB 0010 16 Receive FIFO data register 1 SCFRDR1 R H FFEB 0014 H 1FEB 0014 8 FIFO control register 1 SCFCR1 R ...

Page 1556: ... 1FED 0018 16 Transmit FIFO data count register 3 SCTFDR3 R H FFED 001C H 1FED 001C 16 Receive FIFO data count register 3 SCRFDR3 R H FFED 0020 H 1FED 0020 16 Serial port register 3 SCSPTR3 R W H FFED 0024 H 1FED 0024 16 Line status register 3 SCLSR3 R W 6 H FFED 0028 H 1FED 0028 16 Serial error register 3 SCRER3 R H FFED 002C H 1FED 002C 16 Serial mode register 4 SCSMR4 R W H FFEE 0000 H 1FEE 000...

Page 1557: ...egister SIMDR R W H FFE2 0000 H 1FE2 0000 16 Clock select register SISCR R W H FFE2 0002 H 1FE2 0002 16 Transmit data assign register SITDAR R W H FFE2 0004 H 1FE2 0004 16 Receive data assign register SIRDAR R W H FFE2 0006 H 1FE2 0006 16 Control data assign register SICDAR R W H FFE2 0008 H 1FE2 0008 16 Control register SICTR R W H FFE2 000C H 1FE2 000C 16 FIFO control register SIFCTR R W H FFE2 ...

Page 1558: ...1 R W H FFE6 000F H 1FE6 000F 8 Transfer clock control register CLKON R W H FFE6 0010 H 1FE6 0010 8 Command timeout control register CTOCR R W H FFE6 0011 H 1FE6 0011 8 Transfer byte number count register TBCR R W H FFE6 0014 H 1FE6 0014 8 Mode register MODER R W H FFE6 0016 H 1FE6 0016 8 Command type register CMDTYR R W H FFE6 0018 H 1FE6 0018 8 Response type register RSPTYR R W H FFE6 0019 H 1FE...

Page 1559: ...atus register 0 HACCR0 R W H FFE3 0008 H 1FE3 0008 32 Command status address register 0 HACCSAR0 R W H FFE3 0020 H 1FE3 0020 32 Command status data register 0 HACCSDR0 R W H FFE3 0024 H 1FE3 0024 32 PCM left channel register 0 HACPCML0 R W H FFE3 0028 H 1FE3 0028 32 PCM right channel register 0 HACPCMR0 R W H FFE3 002C H 1FE3 002C 32 TX interrupt enable register 0 HACTIER0 R W H FFE3 0050 H 1FE3 0...

Page 1560: ...FFE9 0004 H 1FE9 0004 32 Command code register FLCMCDR R W H FFE9 0008 H 1FE9 0008 32 Address register FLADR R W H FFE9 000C H 1FE9 000C 32 Data register FLDATAR R W H FFE9 0010 H 1FE9 0010 32 Data counter register FLDTCNTR R W H FFE9 0014 H 1FE9 0014 32 Interrupt DMA control register FLINTDMACR R W H FFE9 0018 H 1FE9 0018 32 Ready busy timeout setting register FLBSYTMR R W H FFE9 001C H 1FE9 001C...

Page 1561: ...26 H 1FE7 0026 8 Port E data register PEDR R W H FFE7 0028 H 1FE7 0028 8 Port F data register PFDR R W H FFE7 002A H 1FE7 002A 8 Port G data register PGDR R W H FFE7 002C H 1FE7 002C 8 Port H data register PHDR R W H FFE7 002E H 1FE7 002E 8 Port J data register PJDR R W H FFE7 0030 H 1FE7 0030 8 Port K data register PKDR R W H FFE7 0032 H 1FE7 0032 8 Port L data register PLDR R W H FFE7 0034 H 1FE...

Page 1562: ...28 32 Match address mask setting register 1 CAMR1 R W H FF20002C H 1F20002C 32 Match data setting register 1 CDR1 R W H FF200030 H 1F200030 32 Match data mask setting register 1 CDMR1 R W H FF200034 H 1F200034 32 Execution count break register 1 CETR1 R W H FF200038 H 1F200038 32 Channel match flag register CCMFR R W H FF200600 H 1F200600 32 Break control register CBCR R W H FF200620 H 1F200620 32...

Page 1563: ...ter EXPMASK H 0000 0013 H 0000 0013 Retained MMU Page table entry high register PTEH Undefined Undefined Retained Page table entry low register PTEL Undefined Undefined Retained Translation table base register TTB Undefined Undefined Retained TLB exception address register TEA Undefined Retained Retained MMU control register MMUCR H 0000 0000 H 0000 0000 Retained Physical address space control reg...

Page 1564: ...K H 0000 0000 H 0000 0000 Retained Interrupt priority register 0 INT2PRI0 H 0000 0000 H 0000 0000 Retained Interrupt priority register 1 INT2PRI1 H 0000 0000 H 0000 0000 Retained Interrupt priority register 2 INT2PRI2 H 0000 0000 H 0000 0000 Retained Interrupt priority register 3 INT2PRI3 H 0000 0000 H 0000 0000 Retained Interrupt priority register 4 INT2PRI4 H 0000 0000 H 0000 0000 Retained Inter...

Page 1565: ... Retained Retained CS2 Bus Control Register CS2BCR H 7777 77F0 Retained Retained CS3 Bus Control Register CS3BCR H 7777 77F0 Retained Retained CS4 Bus Control Register CS4BCR H 7777 77F0 Retained Retained CS5 Bus Control Register CS5BCR H 7777 77F0 Retained Retained CS6 Bus Control Register CS6BCR H 7777 77F0 Retained Retained CS0 Wait Control Register CS0WCR H 7777 770F Retained Retained CS1 Wait...

Page 1566: ...03 FFFF PCIC enable control register PCIECR H 0000 0000 Retained Retained PCI configuration register space physical address H FE04 0000 to H FE04 00FF PCI vendor ID register PCIVID H 1912 Retained Retained PCI device ID register PCIDID H 0007 Retained Retained PCI command register PCICMD H 0080 Retained Retained PCI status register PCISTATUS H 0290 Retained Retained PCI revision ID register PCIRID...

Page 1567: ...n dissipation data register PCIPCDD H 00 Retained Retained PCI local register space physical address H FE04 0100 to H FE04 03FF PCI control register PCICR H 0000 00xx Retained Retained PCI local space register 0 PCILSR0 H 0000 0000 Retained Retained PCI local space register 1 PCILSR1 H 0000 0000 Retained Retained PCI local address register 0 PCILAR0 H 0000 0000 Retained Retained PCI local address ...

Page 1568: ... PCI memory bank register 2 PCIMBR2 H 0000 0000 Retained Retained PCI memory bank mask register 2 PCIMBMR2 H 0000 0000 Retained Retained PCI I O bank register PCIIOBR H 0000 0000 Retained Retained PCI I O bank master register PCIIOBMR H 0000 0000 Retained Retained PCI cache snoop control register 0 PCICSCR0 H 0000 0000 Retained Retained PCI cache snoop control register 1 PCICSCR1 H 0000 0000 Retai...

Page 1569: ...ndefined Retained Retained DMA channel control register 2 CHCR2 H 4000 0000 H 4000 0000 Retained Retained DMA source address register 3 SAR3 Undefined Undefined Retained Retained DMA destination address register 3 DAR3 Undefined Undefined Retained Retained DMA transfer count register 3 TCR3 Undefined Undefined Retained Retained DMA channel control register 3 CHCR3 H 4000 0000 H 4000 0000 Retained ...

Page 1570: ...H 0000 H 0000 Retained Retained DMA source address register 6 SAR6 Undefined Undefined Retained Retained DMA destination address register 6 DAR6 Undefined Undefined Retained Retained DMA transfer count register 6 TCR6 Undefined Undefined Retained Retained DMA channel control register 6 CHCR6 H 4000 0000 H 4000 0000 Retained Retained DMA source address register 7 SAR7 Undefined Undefined Retained R...

Page 1571: ...efined Undefined Retained Retained DMA destination address register B6 DARB6 Undefined Undefined Retained Retained DMA transfer count register B6 TCRB6 Undefined Undefined Retained Retained DMA source address register B7 SARB7 Undefined Undefined Retained Retained DMA destination address register B7 DARB7 Undefined Undefined Retained Retained DMA transfer count register B7 TCRB7 Undefined Undefine...

Page 1572: ...l register 0 MSTPCR0 H 0000 0000 Retained Retained Retained Standby control register 1 MSTPCR1 H 0000 0000 Retained Retained Retained Standby display register MSTPMR H 00x0 0000 1 Retained Retained Retained WDT Watchdog timer stop time register WDTST H 0000 0000 Retained Retained Retained Watchdog timer control status register WDTCSR H 0000 0000 Retained Retained Retained Watchdog timer base stop ...

Page 1573: ...ut capture register 2 TCPR2 Retained Retained Retained Retained Timer start register 1 TSTR1 H 00 H 00 Retained Retained Timer constant register 3 TCOR3 H FFFF FFFF H FFFF FFFF Retained Retained Timer counter 3 TCNT3 H FFFF FFFF H FFFF FFFF Retained Retained Timer control register 3 TCR3 H 0000 H 0000 Retained Retained Timer constant register 4 TCOR4 H FFFF FFFF H FFFF FFFF Retained Retained Timer...

Page 1574: ...WR Undefined Retained Retained Retained Vertical scan period register VCR Undefined Retained Retained Retained Vertical synchronous position register VSPR Undefined Retained Retained Retained Equivalent pulse width register EQWR Undefined Retained Retained Retained Separation width register SPWR Undefined Retained Retained Retained CLAMP signal start position register CLAMPSR Undefined Retained Re...

Page 1575: ...ne 1 display area start address 1 register P1DSA1R Undefined Retained Retained Retained Plane 1 start position X register P1SPXR Undefined Retained Retained Retained Plane 1 start position Y register P1SPYR Undefined Retained Retained Retained Plane 1 wrap around start position register P1WASPR Undefined Retained Retained Retained Plane 1 wrap around memory width register P1WAMWR Undefined Retaine...

Page 1576: ...ne 2 memory length register P2MLR H 00000000 Retained Retained Retained Plane 3 mode register P3MR H 00000000 Retained Retained Retained Plane 3 memory width register P3MWR Undefined Retained Retained Retained Plane 3 blend ratio register P3ALPHAR Undefined Retained Retained Retained Plane 3 display size X register P3DSXR Undefined Retained Retained Retained Plane 3 display size Y register P3DSYR ...

Page 1577: ...ed Retained Plane 4 display area start address 1 register P4DSA1R Undefined Retained Retained Retained Plane 4 start position X register P4SPXR Undefined Retained Retained Retained Plane 4 start position Y register P4SPYR Undefined Retained Retained Retained Plane 4 wrap around start position register P4WASPR Undefined Retained Retained Retained Plane 4 wrap around memory width register P4WAMWR Un...

Page 1578: ...ne 5 memory length register P5MLR H 00000000 Retained Retained Retained Plane 6 mode register P6MR H 00000000 Retained Retained Retained Plane 6 memory width register P6MWR Undefined Retained Retained Retained Plane 6 blend ratio register P6ALPHAR Undefined Retained Retained Retained Plane 6 display size X register P6DSXR Undefined Retained Retained Retained Plane 6 display size Y register P6DSYR ...

Page 1579: ...ster 255 CP3_255R Undefined Retained Retained Retained Color palette 4 register 000 CP4_000R Undefined Retained Retained Retained Color palette 4 register 255 CP4_255R Undefined Retained Retained Retained External synchronization control register ESCR H 00000000 Retained Retained Retained Output signal timing adjustment register OTAR H 00000000 Retained Retained Retained GDTA GA mask register GACM...

Page 1580: ...ined Retained CL output padding size setting register CLOPR H 0000 0000 H 0000 0000 Retained Retained CL palette pointer setting register CLPLPR H 0000 0000 H 0000 0000 Retained Retained MC command FIFO MCCF H 0000 0000 H 0000 0000 Retained Retained MC status register MCSR H 0000 0000 H 0000 0000 Retained Retained MC frame width setting register MCWR H 0000 0000 H 0000 0000 Retained Retained MC fr...

Page 1581: ...00 Retained Retained Serial port register 0 SCSPTR0 H 000x 1 H 000x 1 Retained Retained Line status register 0 SCLSR0 H 0000 H 0000 Retained Retained Serial error register 0 SCRER0 H 0000 H 0000 Retained Retained Serial mode register 1 SCSMR1 H 0000 H 0000 Retained Retained Bit rate register 1 SCBRR1 H FF H FF Retained Retained Serial control register 1 SCSCR1 H 0000 H 0000 Retained Retained Trans...

Page 1582: ...ed Transmit FIFO data register 3 SCFTDR3 Undefined Undefined Retained Retained Serial status register 3 SCFSR3 H 0060 H 0060 Retained Retained Receive FIFO data register 3 SCFRDR3 Undefined Undefined Retained Retained FIFO control register 3 SCFCR3 H 0000 H 0000 Retained Retained Transmit FIFO data count register 3 SCTFDR3 H 0000 H 0000 Retained Retained Receive FIFO data count register 3 SCRFDR3 ...

Page 1583: ...O control register 5 SCFCR5 H 0000 H 0000 Retained Retained Transmit FIFO data count register 5 SCTFDR5 H 0000 H 0000 Retained Retained Receive FIFO data count register 5 SCRFDR5 H 0000 H 0000 Retained Retained Serial port register 5 SCSPTR5 H 000x 2 H 000x 2 Retained Retained Line status register 5 SCLSR5 H 0000 H 0000 Retained Retained Serial error register 5 SCRER5 H 0000 H 0000 Retained Retain...

Page 1584: ...00 0000 H 0000 0000 Retained Retained Retained Status register SPSR H xxxx x120 H xxxx x120 Retained Retained H xxxx x1xx System control register SPSCR H 0000 0040 H 0000 0040 Retained Retained Retained Transmit buffer register SPTBR H 0000 0000 H 0000 0000 Retained Retained Retained Receive buffer register SPRBR H 0000 0000 H 0000 0000 Retained Retained Retained Note x represents an undefined val...

Page 1585: ... H 00 H 00 Retained Retained Interrupt control register 1 INTCR1 H 00 H 00 Retained Retained Interrupt status register 0 INTSTR0 H 00 H 00 Retained Retained Interrupt status register 1 INTSTR1 H 00 H 00 Retained Retained Transfer clock control register CLKON H 00 H 00 Retained Retained Command timeout control register CTOCR H 01 H 01 Retained Retained Transfer byte number count register TBCR H 00 ...

Page 1586: ...ster FIFOCLR H 00 H 00 Retained Retained DMA control register DMACR H 00 H 00 Retained Retained Interrupt control register 2 INTCR2 H 00 H 00 Retained Retained Interrupt status register 2 INTSTR2 H 0x H 0x Retained Retained HAC Control and status register 0 HACCR0 H 0000 0200 H 0000 0200 Retained Retained Command status address register 0 HACCSAR0 H 0000 0000 H 0000 0000 Retained Retained Command ...

Page 1587: ...er 0 SSIRDR0 H 0000 0000 H 0000 0000 Retained Retained Control register 1 SSICR1 H 0000 0000 H 0000 0000 Retained Retained Status register 1 SSISR1 H 0200 0003 H 0200 0003 Retained Retained Transmit data register 1 SSITDR1 H 0000 0000 H 0000 0000 Retained Retained Receive data register 1 SSIRDR1 H 0000 0000 H 0000 0000 Retained Retained FLCTL Common control register FLCMNCR H 0000 0000 H 0000 0000...

Page 1588: ...F Retained Retained Retained Port M control register PMCR H FFF0 Retained Retained Retained Port N control register PNCR H FFFF Retained Retained Retained Port P control register PPCR H 0000 Retained Retained Retained Port Q control register PQCR H 0000 Retained Retained Retained Port R control register PRCR H 0000 Retained Retained Retained Port A data register PADR H 00 Retained Retained Retaine...

Page 1589: ...er PHPUPR H FF Retained Retained Retained Port J pull up control register PJPUPR H FF Retained Retained Retained Port K pull up control register PKPUPR H FF Retained Retained Retained Port L pull up control register PLPUPR H FF Retained Retained Retained Port M pull up control register PMPUPR H FF Retained Retained Retained Port N pull up control register PNPUPR H FF Retained Retained Retained Inp...

Page 1590: ...egister 1 CRR1 H 00002000 Retained Retained Match address setting register 1 CAR1 Undefined Retained Retained Match address mask setting register 1 CAMR1 Undefined Retained Retained Match data setting register 1 CDR1 Undefined Retained Retained Match data mask setting register 1 CDMR1 Undefined Retained Retained Execution count break register 1 CETR1 Undefined Retained Retained Channel match flag ...

Page 1591: ...DD PLL1 2 Internal power supply voltage VDDA PLL1 0 3 to 1 4 V DDR power supply VDD DDR 0 3 to 2 5 V Vin 3 3V type 0 3 to VDDQ 0 3 V Input voltage Vin 1 8V type 0 3 to VDD DDR 0 3 Operating temperature Topr 20 to 85 C 40 to 85 3 Storage temperature Tstg 55 to 125 C Notes 1 The LSI may be permanently damaged if the maximum ratings are exceeded 2 The LSI may be permanently damaged if any of the VSS ...

Page 1592: ... voltage Vref 0 49 VDD DDR 0 50 VDD DDR 0 51 VDD DDR V Normal mode sleep mode module standby mode Current dissipation Normal operation 1800 3000 Sleep mode IDD 900 1700 Ick 600 MHz Bck 100 MHz Pck 50 MHz DDRck 300 MHz PCICLK 66 MHz Normal operation 70 145 Sleep mode IDDQ 50 100 Ick 600 MHz Bck 100 MHz Pck 50 MHz DDRck 300 MHz PCICLK 66 MHz ΣIDD PLL 3 7 Normal operation ΣIDDQ PLL 2 4 mA DDR Normal ...

Page 1593: ...67MHz External clock input VIH DC Vref 0 125 VDD DDR 0 3 DDR pins VIH AC Vref 0 2 PCICLK VIH VDDQ 0 6 VDDQ 0 3 Other PCI pins VDDQ 0 5 VDDQ 0 3 V Other input pins 2 0 VDDQ 0 3 PRESET NMI TRST VIL 0 3 VDDQ 0 1 VDDQ 3 0 to 3 6 V 0 3 VDDQ 0 2 34MHz External clock input EXTAL 0 3 VDDQ 0 2 34MHz 67MHz External clock input VIL DC 0 3 Vref 0 125 DDR pins VIL AC Vref 0 2 PCICLK 0 3 VDDQ 0 3 Input voltage ...

Page 1594: ...nit Item AC differential input voltage VID AC 0 5 VDD DDR 0 6 AC differential cross point voltage VIX AC VDD DDR 0 5 0 175 VDD DDR 0 5 0 175 V Input leak current DDR pins L 5 μA Three state leak current All input pins lin 1 μA VIN 0 5 to VDDQ 0 5 V I O all output pins off condition lsti 1 VIN 0 5 to VDDQ 0 5 V ...

Page 1595: ... IOL 13 4 mA Output voltage Other output pins VOL 0 55 V VDDQ 3 0 V IOL 2 mA AC differential cross point voltage VOX AC VDD DDR 0 5 0 125 VDD DDR 0 5 0 125 V PCI pins 2 10 18 Pull up resistance Other pins Rpull 20 100 180 kΩ DDR pins 10 Pin capacitance AUDCK AUDSYNC AUDATA0 AUDATA1 AUDATA2 AUDATA3 CL 10 pF Other pins 10 Notes 1 Regardless of whether or not the PLL is used connect VDD PLL1 2 VDDA P...

Page 1596: ...issible output low current total ΣIOL 120 Permissible output high current per pin DDR pins 13 4 Permissible output high current per pin PCI pins 4 Permissible output high current per pin other than DDR and PCI pins IOH 2 Permissible output high current total Σ IOH 40 Note To protect chip reliability do not exceed the output current values in table 32 3 Table 32 4 ODT Characteristics Item Symbol Mi...

Page 1597: ...his LSI s input should be synchronous Unless specified otherwise ensure that the setup time and hold times for each input signal are observed Table 32 5 Clock Timing Item Symbol Min Typ Max Unit CPU FPU cache TLB f 1 603 MHz DDR2 SDRAM bus 200 302 External bus 1 101 Operating frequency PCI bus DC 67 Peripheral modules 1 51 ...

Page 1598: ...tEXH 3 5 ns 32 1 EXTAL clock input rise time tEXr 4 ns 32 1 EXTAL clock input fall time tEXf 4 ns 32 1 CLKOUT clock output with use of PLL1 PLL2 fOP 25 101 MHz CLKOUT clock output cycle time tCKOcyc 10 1000 ns 32 2 CLKOUT clock output low pulse width tCKOL1 1 ns 32 2 CLKOUT clock output high pulse width tCKOH1 1 ns 32 2 CLKOUT clock output rise time tCKOr 3 ns 32 2 CLKOUT clock output fall time tC...

Page 1599: ...al resonator connected on EXTAL and XTAL the maximum frequency is 34 MHz When using a third order overtone crystal resonator a tank circuit must be connected externally 2 The load capacitance connected on the CLKOUT pin should be not greater than 50 pF 3 tcyc is the period of one CLKOUT clock cycle 4 This applies to clock operating modes 0 1 2 and 3 see table 15 2 5 This applies to clock operating...

Page 1600: ...v 1 00 Jan 10 2008 Page 1570 of 1658 REJ09B0261 0100 tCKOcyc tCKOH1 tCKOL1 tCKOr tCKOf 1 2VDDQ VOH VOH VOL VOL VOH 1 2VDDQ Figure 32 2 CLKOUT Clock Output Timing 1 tCKOH2 1 5V 1 5V 1 5V tCKOL2 Figure 32 3 CLKOUT Clock Output Timing 2 ...

Page 1601: ...tRESW CLKOUT Notes 1 Oscillation settling time for the case when the on chip resonator is used 2 PLL2 is operating PRESET MODE14 MODE10 MODE9 MODE4 to MODE0 TRST Oscillation settling time Internal clock Figure 32 4 Power On Oscillation Settling Time CLKOUT output EXTAL input tPLL Figure 32 5 PLL Synchronization Settling Time ...

Page 1602: ...rol Signal Timing Table 32 7 Control Signal Timing Conditions VDDQ 3 0 to 3 6 V VDD 1 1 V Ta 20 to 85 40 to 85 C CL 30 pF Item Symbol Min Max Unit Figure BREQ setup time tBREQS 3 ns BREQ hold time tBREQH 1 5 ns BREQ delay time tBACKD 6 ns Bus tri state delay time tBOFF1 12 ns Bus buffer on time tBON1 12 ns 32 7 STATUS0 STATUS1 delay time tSTD 6 ns 32 8 Note tcyc is the period of one CLKOUT cycle ...

Page 1603: ... tBREQH tBREQS tBREQH tBREQS tBACKD tBACKD tBOFF1 tBON1 CKIO BREQ BACK A 25 0 CSn BS RD WR CE2A CE2B RAS WEn RD CASn Figure 32 7 Control Signal Timing CLKOUT tSTD STATUS1 STATUS0 Reset Power on reset Normal operation Normal PRESET Figure 32 8 STATUS Pin Output Timing at Power On Reset ...

Page 1604: ...s Read data setup time tRDS 2 5 ns Read data hold time tRDH 1 5 ns WE delay time falling edge tWEDF 1 5 6 ns Relative to CLKOUT falling edge WE delay time tWED1 1 5 6 ns Write data delay time tWDD 1 5 6 ns RDY setup time tRDYS 2 5 ns RDY hold time tRDYH 1 5 ns FRAME delay time tFMD 1 5 6 ns MPX IOIS16 setup time tIO16S 2 5 ns PCMCIA IOIS16 hold time tIO16H 1 5 ns PCMCIA IOWR delay time falling edg...

Page 1605: ...mory SA IO memory DACKn DACKn DA Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer Note DACK is configured as active high T1 T2 tAD tAD WEn BS RDY tDACD tDACD tDACD tDACD tDACDF tDACDF tDACD tWDD tWDD tWDD tBSD tBSD tWED1 tWEDF tWEDF tRDH tRDS tRSD tRSD tRSD tCSD tCSD tRWD tRWD Figure 32 9 SRAM Bus Cycle Basic Bus Cycle No Wait ...

Page 1606: ... Single address DMA transfer DA Dual address DMA transfer Note DACK is configured as active high tWDD tWDD tWDD tDACDF tDACDF CLKOUT CSn RD WEn BS RDY RD WR DACKn DA T1 tAD Tw T2 tAD tRDH tRDS tCSD tRWD tRWD tCSD tRSD tRSD tRSD tWED1 tWEDF tWEDF tRDYH tRDYS tBSD tBSD tDACD tDACD tDACD tDACD tDACD DACKn DACKn Figure 32 10 SRAM Bus Cycle Basic Bus Cycle One Internal Wait Cycle ...

Page 1607: ...transfer DA Dual address DMA transfer Note DACK is configured as active high tWDD tWDD tWDD tDACDF tDACDF CLKOUT RD WR RD CSn RDY BS WEn DACKn DA T1 tAD Tw Twe T2 tAD tRDH tRDS tCSD tRWD tRWD tCSD tRSD tRSD tRSD tWED1 tWEDF tWEDF tRDYH tRDYS tRDYH tRDYS tBSD tBSD tDACD tDACD tDACD tDACD tDACD DACKn DACKn Figure 32 11 SRAM Bus Cycle Basic Bus Cycle One Internal Wait Cycle One External Wait Cycle ...

Page 1608: ...ansfer DA Dual address DMA transfer Note DACK is configured as active high tWDD tWDD tWDD tDACDF tDACDF tDACD tDACD tDACD TS1 tAD T1 T2 TH1 tAD tRDH tRDS tCSD tRWD tRWD tCSD tRSD tRSD tRSD tWED1 tWEDF tWEDF tBSD tBSD tDACD tDACD CLKOUT RD WR CSn WEn BS RDY RD DACKn DACKn DACKn DA Figure 32 12 SRAM Bus Cycle Basic Bus Cycle CSnWCR IW 0000 CSnWCR RDS 001 CSnWCR WTS 001 CSnWCR RDH 001 CSnWCR WTH 001 ...

Page 1609: ...SA Single address DMA transfer DA Dual address DMA transfer Note DACK is configured as active high CLKOUT A25 to A5 T1 T2 RD WR CSn BS RDY RD A4 to A0 TB2 TB1 TB2 TB1 TB2 TB1 tCSD tAD tRWD tBSD tRDS tBSD tRSD tRSD tRDH tAD tAD tCSD tRWD tRDH tRSD tRDS DACKn DACKn DA tDACD tDACD tDACD tDACD tDACD Figure 32 13 Burst ROM Bus Cycle No Wait ...

Page 1610: ...nfigured as active high A25 to A5 A4 to A0 T1 T2 TB2 TB1 TB2 TB1 TB2 TB1 Twb Twb Twb Twe Tw tAD tCSD tRSD tRDH tRDS tBSD tAD tRDH tRSD tRDS tAD tCSD tRDYH tRDYS tRDYH tRDYS tRDYH tRDYS tDACD tDACD tDACD tDACD tRWD tRWD CLKOUT CSn RD WR BS RDY RD DACKn DACKn DA Figure 32 14 Burst ROM Bus Cycle One Internal Wait Cycle One External Wait Cycle for the 1st Datum One Internal Wait Cycle for the 2nd 3rd ...

Page 1611: ...DMA transfer Note DACK is configured as active high A25 to A5 A4 to A0 T1 TB2 tCSD tRWD tBSD tRDS tBSD tRSD tAD TS1 tDACD TB1 TB2 tAD tRDH tDACD tDACD TB1 TB2 T2 TB1 tAD tCSD tRWD tRDH tRSD tRDS TH1 TS1 TH1 TS1 TH1 TS1 TH1 CLKOUT DACKn DA DACKn CSn RD WR RD BS RDY tDACD tDACD Figure 32 15 Burst ROM Bus Cycle CSnWCR IW 0000 CSnWCR RDS 001 CSnWCR WTS 001 CSnWCR RDH 001 CSnWCR WTH 001 ...

Page 1612: ...ACK is configured as active high A25 to A5 A4 to A0 Tw T1 Twe TB2 TB1 Twb Twbe TB1 TB2 Twb Twbe Twb T2 TB2 Twbe TB1 tAD tAD tAD tRDH tRDS tRDH tRDS tDACD tDACD tDACD tBSD tBSD tBSD tBSD tRSD tRSD tRWD tCSD tRWD tCSD tDACD tDACD tRSD tRDYH tRDYS tRDYH tRDYS tRDYH tRDYS tRDYH tRDYS CLKOUT DACKn DA DACKn CSn RD WR RD BS RDY Figure 32 16 Burst ROM Bus Cycle One Internal Wait Cycle One External Wait Cy...

Page 1613: ... Tpcm1 Tpcm2 Tpcm1w Tpcm1w Tpcm2w tAD tAD tWDD tBSD tBSD tBSD tBSD tWDD tWDD tRWD tCSD tCSD tRWD tRSD tRSD tRSD tWEDF tWED1 tWEDF tDACD tRDH tRDS tRDYH tRDYS tRDYH tRDYS tDACD tAD tAD tWDD tWDD tWDD tRWD tCSD tCSD tRWD tRSD tRSD tRSD tWEDF tWED1 tWEDF tDACD TED TEH tRDH tRDS tDACD A25 to A0 CLKOUT CExx REG WE0 RD WR WE1 RD BS RDY DACKn DA 1 TED 0 THE 0 no wait 2 TED 1 THE 1 one internal wait one e...

Page 1614: ...pci2 Tpci1w Tpci1w Tpci2w CLKOUT tAD tAD tBSD tBSD tBSD tBSD tWDD tWDD tRWD tCSD tCSD tRWD tICRSD tICRSD tICWSDF tICWSDF tDACD tRDH tRDS tRDYH tRDYS tRDYH tRDYS tIO16H tIO16S tIO16H tIO16S tDACD tAD tAD tWDD tWDD tWDD tRWD tCSD tCSD tRWD tICRSD tICRSD tICRSD tICWSDF tICWSDF tICWSDF tDACD tRDH tRDS tDACD 1 TED 0 THE 0 no wait 2 TED 1 THE 1 internal wait external wait cycles CExx REG WE0 RD WR ICIOW...

Page 1615: ...BSD tAD tAD tWDD tWDD tWDD tWDD tWDD tRWD tRWD tAD tCSD tCSD tCSD tICRSD tICRSD tICRSD tICWSDF tICWSDF tICWSDF tICWSDF tICWSDF tRDH tRDS tRDYS tRDYS tIO16S tIO16H tRDYS tRDYH D15 to D0 D15 to D0 Write Read Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer Note DACK is configured as active high A25 to A1 Figure 32 19 PCMCIA I O Bus Cycle TED 1 TEH 1 One Internal Wait...

Page 1616: ...RDYS 1 1st data One internal wait cycle Information in the first data bus cycle D31 to D29 Access size 000 Byte 001 Word 2 bytes 010 Longword 4 bytes 011 Quadword 8 bytes 1xx Burst 32 bytes D25 to D0 Address 2 1st data One internal wait one external wait cycles Information in the first data bus cycle D31 to D29 Access size 000 Byte 001 Word 2 bytes 010 Longword 4 bytes 011 Quadword 8 bytes 1xx Bur...

Page 1617: ...t data bus cycle D31 to D29 Access size 000 Byte 001 Word 2 bytes 010 Longword 4 bytes 011 Quadword 8 bytes 1xx Burst 32 bytes D25 to D0 Address 2 1st data One internal wait cycle Information in the first data bus cycle D31 to D29 Access size 000 Byte 001 Word 2 bytes 010 Longword 4 bytes 011 Quadword 8 bytes 1xx Burst 32 bytes D25 to D0 Address 3 1st data One internal wait one external wait cycle...

Page 1618: ...s size 000 Byte 001 Word 2 bytes 010 Longword 4 bytes 011 Quadword 8 bytes 1xx Burst 32 bytes D25 to D0 Address Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer Note DACK is configured as active high Tm1 CLKOUT RD FRAME CSn RD WR RDY BS DACKn DA CLKOUT RD FRAME CSn RD WR RDY BS DACKn DA tFMD Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 D1 A D2 D3 D4 D5 D6 D7 D8 tF...

Page 1619: ... Byte 001 Word 2 bytes 010 Longword 4 bytes 011 Quadword 8 bytes 1xx Burst 32 bytes D25 to D0 Address Legend IO DACK device SA Single address DMA transfer DA Dual address DMA transfer Note DACK is configured as active high Tm1 CLKOUT RD FRAME CSn RD WR RDY BS DACKn DA CLKOUT RD FRAME CSn RD WR RDY BS DACKn DA tFMD Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 A D1 D2 D3 D4 D5 D6 D7 D8 tFMD tWDD tCSD tCS...

Page 1620: ...tCSD tCSD tDACD tDACD tWED1 tDACD tRWD tRWD tRDYH tRDYS tRDYH tRDYS tAD tAD tAD tAD T1 Tw Twe T2 tDACD tDACD tRSD tRSD tRSD tRSD tRSD tRSD tRSD tRSD tWED1 tWED1 tWEDF tWED1 tWEDF tWED1 tWEDF tWED1 tCSD tCSD tDACD tBSD tBSD tBSD tBSD tBSD tBSD tDACD tDACD tRWD tRWD tRSD tAD tAD tRDH tRDS tRDH tRDS tRDH tRDS CLKOUT RD RD WR WEn RDY BS CSn DACKn DA DACKn 1 Basic read cycle no wait 2 Basic read cycle ...

Page 1621: ...er DA Dual address DMA transfer Note DACK is configured as active high CLKOUT RD WR CSn RD WEn BS RDY DACKn DA TS1 T1 T2 TH1 tRSD tRSD tWED1 tWEDF tWED1 tCSD tCSD tDACD tBSD tBSD tDACD tRWD tRWD tRSD tAD tAD tRDH tRDS DACKn tDACD tDACD Figure 32 25 Memory Byte Control SRAM Bus Cycle Basic Read Cycle CSnWCR IW 0000 CSnWCR RDS 001 CSnWCR WTS 001 CSnWCR RDH 001 CSnWCR WTH 001 ...

Page 1622: ...55 tMCK 880 ps DDR2 600 Address and control signal setup time to MCK rising edge tIS 1290 DDR2 400 880 ps DDR2 600 Address and control signal hold time to MCK rising edge tIH 1290 DDR2 400 Address and control signal width tIPW 0 6 tMCK MCLK to MDQS skew time Read tRDQSDLY 0 2 1 4 ns MDQS high level pulse width Read tRDQSH 0 35 0 65 tMCK MDQS low level pulse width Read tRDQSL 0 35 0 65 tMCK MDQS pr...

Page 1623: ...te tWDSH 0 27 tMCK MDQS high level pulse width Write tWDQSH 0 35 0 9 tMCK MDQS low level pulse width Write tWDQSL 0 35 0 9 tMCK MDQS preamble Write tWPRE 0 35 tMCK MDQS postamble write tWPST 0 4 tMCK 430 DDR2 600 MDQ MDM setup time to MDQS Write tWDS 630 ps DDR2 400 430 DDR2 600 MDQ MDM hold time to MDQS Write tWDH 630 ps DDR2 400 MDQ MDM signal width Write tWDIPW 0 35 tMCK MDQ high impedance time...

Page 1624: ...4 0 tIS tIPW Figure 32 27 Command Signal and MCK Output Clock MCK0 MCK1 solid line MCK0 MCK1 dotted line MCKE MCS MRAS MCAS MWE MBA 2 0 MA 14 0 READ Command MDQS 3 0 solid line MDQS 3 0 dotted line tRDQSCK Min MDQS 3 0 solid line MDQS 3 0 dotted line tRDQSCK Max tRDQSCK min tRDQSCK min tRDQSCK max tRDQSCK max CL Cas Latency Figure 32 28 MDQS Input Timing at Data Read ...

Page 1625: ... 0 solid line MDQS 3 0 dotted line tWDQSS Min MDQS 3 0 solid line MDQS 3 0 dotted line tWDQSS Max tWDQSS min tWDSH tWDQSS max WL CL 1 HiZ HiZ HiZ HiZ tWDSS tWDSH tWDSS tWDSH tWDSS tWDSH tWDSS MCK0 MCK1 solid line MCK0 MCK1 dotted line MCKE MCS MRAS MCAS MWE MBA 2 0 MA 14 0 Figure 32 30 MDQS Output Waveform to MCK Write MDQS 3 0 solid line MDQS 3 0 dotted line tWDQSH tWDQSL tWPRE HiZ HiZ tWPST Figu...

Page 1626: ...9B0261 0100 MDQS 3 0 solid line MDQS 3 0 dotted line MDQ 31 0 MDM 3 0 tWDS tWDH tWDS tWDH tWDIPW tWDIPW Figure 32 32 MDQS and MDQ MDM Output Waveform Write MDQS 3 0 solid line MDQS 3 0 dotted line tHZ HiZ HiZ HiZ MDQ 31 0 Figure 32 33 MDQ High Impedance Time from MDQS Write ...

Page 1627: ...time tNMIH 1 5 ns 32 34 NMI pulse width high level tNMIIS 5 tcyc 32 35 NMI pulse width low level tNMIIH 5 tcyc 32 35 Edge sense IRQ pulse width high level tIRQIH 5 tcyc 32 35 Edge sense IRQ pulse width low level tIRQIL 5 tcyc 32 35 IRL7 to IRL0 setup time tIRLS 4 ns 32 34 IRL7 to IRL0 hold time tIRLH 1 5 ns 32 34 IRQOUT delay time tIRQOD 1 5 6 ns 32 36 Note tcyc is the period of one CLKOUT cycle C...

Page 1628: ...ical Characteristics Rev 1 00 Jan 10 2008 Page 1598 of 1658 REJ09B0261 0100 NMI IRQ tNMIIH tNMIIL tIRQIH tIRQIL Figure 32 35 Interrupt Signal Input Timing 2 CLKOUT tIRQOD tIRQOD IRQOUT Figure 32 36 IRQOUT Timing ...

Page 1629: ...tPCIVAL 10 10 ns 32 38 Input setup time tPCISU 3 3 ns 32 39 IDSEL Input hold time tPCIH 1 5 1 5 Output data delay time tPCIVAL 2 10 2 6 ns 32 38 Tri state drive delay time tPCION 2 10 2 6 Tri state Hi Z delay time tPCIOFF 2 12 2 6 Input setup time tPCISU 3 3 32 39 AD31 to AD0 C BE3 to C BE0 PCIFRAME PAR IRDY TRDY STOP LOCK PERR DEVSEL Input hold time tPCIH 1 5 1 5 Output data delay time tPCIVAL 2 ...

Page 1630: ... Page 1600 of 1658 REJ09B0261 0100 0 5VDDQ 0 5VDDQ tPCICYC tPCIHIGH tPCILOW tPCIf tPCIr VL VL VH VH VH Figure 32 37 PCI Clock Input Timing tPCIVAL 0 4VDDQ 0 4VDDQ PCICLK Tri state output Output delay tPCION tPCIOFF Figure 32 38 PCI Output Signal Timing ...

Page 1631: ...Module Signal Timing Table 32 12 DMAC Module Signal Timing Conditions VDDQ 3 0 to 3 6 V VDD 1 5 V Ta 40 to 85 C CL 30 pF PLL2 on Module Item Symbol Min Max Unit Figure Remarks DMAC DREQ setup time tDRQS 2 5 ns 32 40 DREQ hold time tDRQH 1 5 DRAK delay time tDRAKD 1 5 6 DACK delay time tDAKD 1 5 6 tDRQS CLKOUT DRAK DREQ tDRQH tDRAKD tDRAKD Figure 32 40 DREQ DRAK Signal Timing ...

Page 1632: ... 3 6 V VDD 1 1 V Ta 40 to 85 C CL 30 pF PLL2 on Module Item Symbol Min Max Unit Figure Remarks TMU Timer clock pulse width high tTCLKWH 4 tPcyc 32 41 Timer clock pulse width low tTCLKWL 4 Timer clock rise time tTCLKr 0 8 Timer clock fall time tTCLKf 0 8 Note tPcyc is the period of one peripheral clock Pck cycle tTCLKWH tTCLKWL tTCLKf tTCLKr TCLK Figure 32 41 TCLK Input Timing ...

Page 1633: ...cle asynchronous tScyc 4 tPcyc Input clock cycle clock synchronous 10 tPcyc Input clock pulse width tSCKW 0 4 0 6 tScyc Input clock rise time tSCKr 0 8 tPcyc Input clock fall time tSCKf 0 8 tPcyc 32 42 Transfer data delay time tTXD 6 tPcyc 32 43 Receive data setup time clock synchronous tRXS 16 ns Receive data hold time clock synchronous tRXH 16 ns Note tpcyc means one cycle time of the peripheral...

Page 1634: ...32 Electrical Characteristics Rev 1 00 Jan 10 2008 Page 1604 of 1658 REJ09B0261 0100 tScyc tTXD tRXS tRXH SCIFn_CLK SCIFn_TXD SCIFn_RXD tTXD Figure 32 43 Clock Timing in SCIF I O Synchronous Mode ...

Page 1635: ...e time tTCKr 10 ns Input clock fall time tTCKf 10 ns ASEBRK setup time tASEBRKS 10 tcyc 32 45 ASEBRK hold time tASEBRKH 1 ms TDI TMS setup time tTDIS 15 ns 32 46 TDI TMS hold time tTDIH 15 ns TDO data delay time tTDO 0 12 ns ASE PINBRK pulse width tPINBRK 2 tPcyc 32 47 Notes 1 During a boundary scan tTCKcyc is the period corresponding to a frequency of 10 MHz i e 0 1 μs 2 tcyc is the period of one...

Page 1636: ...Jan 10 2008 Page 1606 of 1658 REJ09B0261 0100 ASEBRK BRKACK RESET tASEBRKH tASEBRKS Figure 32 45 RESET Hold Timing TDI TMS TCK TDO tTCKcyc tTDO tTDIH tTDIS Figure 32 46 H UDI Data Transfer Timing tPINBRK ASEBRK Figure 32 47 Pin Break Timing ...

Page 1637: ...0 32 3 11 GPIO Signal Timing Table 32 16 GPIO Signal Timing Item Symbol Min Max Unit Figure GPIO output delay time tIOPD 8 ns 32 48 GPIO input setup time tIOPS 3 5 ns GPIO input hold time tIOPH 1 5 ns tIOPD tIOPS tIOPH CLKOUT GPIO n OUTPUT GPIO n INPUT Figure 32 48 GPIO Signal Timing ...

Page 1638: ...ock low level width tSPILW 60 ns HSPI_TX setup time tSUSPITX 20 ns HSPI_TX delay time tDSPITX 20 ns HSPI_RX setup time tSUSPIRX 20 ns HSPI_RX hold time tHLSPIRX 20 ns HSPI_CS lead time tcCSLEAD 100 ns Note Pck is the frequency of the peripheral clock HSPI_CS tSPICYC tCSLEAD tSUSPITX tSUSPIRX tSUSPIRX tHLSPIRX tSUSPITX tDSPITX tHLSPIRX tDSPITX tSPILW tSPIHW CLKP 0 HSPI_CLK CLKP 1 HSPI_CLK LMSB 0 HS...

Page 1639: ...ime tSICYC tpcyc ns 32 51 to 32 55 SIOF_SCK output high level width tSWHO 0 4 tSICYC ns 32 51 to 32 54 SIOF_SCK output low level width tSWLO 0 4 tSICYC ns SIOF_SYNC output delay time tFSD 10 ns SIOF_SCK input high level width tSWHI 0 4 tSICYC ns 32 55 SIOF_SCK input low level width tSWLI 0 4 tSICYC ns SIOF_SYNC input setup time tFSS 10 ns SIOF_SYNC input hold time tFSH 10 ns SIOF_TXD output delay ...

Page 1640: ...XD tFSD tFSD tSICYC tSWHO tSWLO tSTDD tSTDD tSRDS tSRDH Figure 32 51 SIOF Transmission Reception Timing Master Mode 1 Sampling on Falling Edges SIOF_SCK Output SIOF_SYNC Output SIOF_TXD SIOF_RXD tSICYC tSWHO tSWLO tFSD tFSD tSTDD tSTDD tSRDS tSRDH Figure 32 52 SIOF Transmission Reception Timing Master Mode 1 Sampling on Rising Edges ...

Page 1641: ... tSICYC tSWHO tSWLO tSTDD tSTDD tSTDD tSTDD tSRDS tSRDH Figure 32 53 SIOF Transmission Reception Timing Master Mode 2 Sampling on Falling Edges SIOF_SCK Output SIOF_SYNC Output SIOF_TXD SIOF_RXD tSICYC tSWLO tFSD tSTDD tSTDD tSRDS tSRDH tSTDD tFSD tSTDD tSWHO Figure 32 54 SIOF Transmission Reception Timing Master Mode 2 Sampling on Rising Edges ...

Page 1642: ...Rev 1 00 Jan 10 2008 Page 1612 of 1658 REJ09B0261 0100 SIOF_SCK Output SIOF_SYNC Output SIOF_TXD SIOF_RXD tSICYC tSWHI tSWLI tFSH tFSS tSTDD tSTDD tSRDS tSRDH Figure 32 55 SIOF Transmission Reception Timing Slave Mode 1 Slave Mode 2 ...

Page 1643: ...lock low level width tMMWL 0 4 tMMcyc ns MMCCMD output data delay time tMMTCD 10 ns 32 56 MMCCMD input data hold time tMMRCS 10 ns MMCCMD input data setup time tMMRCH 10 ns 32 57 32 58 MMCD output data delay time tMMTDD 10 ns 32 56 MMCD input data setup time tMMRDS 10 ns 32 57 32 58 MMCD input data hold time tMMRDH 10 ns Note tMmcyc is the period of one MMCCLK cycle tMMcyc tMMWH tMMTDD tMMTDD tMMT...

Page 1644: ...t Figure HAC_RES active low pulse width tRST_LOW 1000 ns 32 58 HAC_SYNC active pulse width tSYN_HIGH 1000 ns 32 59 HAC_SYNC delay time 1 tSYNCD1 15 ns HAC_SYNC delay time 2 tSYNCD2 15 ns HAC_SDOUT delay time tSDOUTD 15 ns HAC_SDIN setup time tSDIN0S 10 ns HAC_SDIN hold time tSDIN0H 10 ns 32 61 HAC_BITCLK input high level width tICL0_HIGH tPcyc 2 ns 32 60 HAC_BITCLK input low level width tICL0_LOW ...

Page 1645: ...9B0261 0100 HACn_SYNC HACn_BITCLK tSYN_HIGH Figure 32 59 HAC Warm Reset Timing HACn_BITCLK tICL_HIGH tICL_LOW Figure 32 60 HAC Clock Input Timing HACn_BITCLK HACn_SDIN HACn_SDOUT tSDNHD tSDNSU tSDCUTD tSYNCD1 tSYNCD2 HACn_SYNC Figure 32 61 HAC Interface Module Signal Timing ...

Page 1646: ...ut low level width tIHC tILC 30 ns Input 32 62 Output high level width output low level width TOHC tOLC 13 ns Output SCK output rise time tRC 60 ns Output SDATA output delay time tDTR 50 ns Transmit 32 63 32 64 SDATA WS input setup time tSR 10 ns Receive SDATA WS input hold time tHTR 10 ns Receive 32 65 32 66 tOHC tIHC tRC VIH VOH VIH VOH VIL VOH tOLC tISCK tOSCK tILC SSIn_SCK VIH VOH VIH VOH VIL ...

Page 1647: ...ge 1617 of 1658 REJ09B0261 0100 tDTR tHTR SSIn_SCK SSIn_WS SSIn_SDATA Figure 32 64 SSI Transmission Timing 2 tSR tHTR SSIn_SCK SSIn_WS SSIn_SDATA Figure 32 65 SSI Reception Timing 1 tHTR tSR SSIn_SCK SSIn_WS SSIn_SDATA Figure 32 66 SSI Reception Timing 2 ...

Page 1648: ...P 0 5 tfcyc 5 ns 32 67 32 68 32 70 32 71 FWE high pulse width tNWH 0 5 tfcyc 5 ns 32 68 32 70 Address to ready busy transition time tNADRB 32 tpcyc ns 32 68 32 69 Ready busy to data read transition time 1 tNRBDR1 1 5 tfcyc ns Ready busy to data read transition time 2 tNRBDR2 32 tpcyc ns FSC cycle time tNSCC tfcyc ns FSC high pulse width tNSPH 0 5 tfcyc 5 ns 32 69 FSC low pulse width tNSP 0 5 tfcyc...

Page 1649: ...FALE Command tNCDAD1 tNCDS tNWP tNDOS tNDOH tNCDH Figure 32 67 Command Issue Timing of NAND Type Flash Memory FD7 to FD0 FCE Low High High FCLE FALE FWE FRE FR B tNWC tNCDAD2 tNDOS tNDOH tNDOH tNDOS tNDOH tNDOS tNCDAD1 tNADRB tNWP tNWH tNWH tNWP tNWP Address Address Address Figure 32 68 Address Issue Timing of NAND Type Flash Memory ...

Page 1650: ...R B tNRBDR2 tNADRB tNRBDR1 tNSP tNRDS tNRDS tNRDH tNRDS tNRDH tNSCC tNSPH tNSP tNSP Data Data Figure 32 69 Data Read Timing of NAND Type Flash Memory FD7 to FD0 FCE FCLE FALE FRE FR B FWE Low Low High High tNDWS tNWP tNWC tNDOS tNDOH tNDOS tNDOH tNDOS tNWH tNWP tNWP Data Data Figure 32 70 Data Write Timing of NAND Type Flash Memory ...

Page 1651: ...0 Jan 10 2008 Page 1621 of 1658 REJ09B0261 0100 FCE FCLE FALE FRE FR B FD7 to FD0 FWE Low Low High tNCDS tNDOS tNRDS tNRDH tNDOH tNWP tNCDH tNSTS tNCDSR tNCDFSR tNSP Command Status Figure 32 71 Status Read Timing of NAND Type Flash Memory ...

Page 1652: ...ymbol Min Typ Max Unit Figures Display input control signal setup time tDS 5 ns Display input control signal hold time tDH 3 ns Figure 32 73 with respect to PCICLK DCLKIN DEVSEL DCLKOUT output cycle time tDCYC 20 ns DEVSEL DCLKOUT output high level width tDCKH 6 ns Delay time of display output control signal output tDD 2 8 ns Display digital data output delay time tDD 2 8 ns Figure 32 74 with resp...

Page 1653: ...RAME VSYNC IRDY HSYNC LOCK ODDF TRDY DISP STOP CDE D32 AD0 DR0 D33 AD1 DR1 D34 AD2 DR2 D35 AD3 DR3 D36 AD4 DR4 D37 AD5 DR5 D38 AD6 DG0 D39 AD7 DG1 D40 AD8 DG2 D41 AD9 DG3 D42 AD10 DG4 D43 AD11 DG5 D44 AD12 DB0 D45 AD13 DB1 D46 AD14 DB2 D47 AD15 DB3 D48 AD16 DB4 D49 AD17 DB5 Note 1 2 and 3 correspond to the numbers with asterisk in figures 32 73 and 32 74 tDICYC tDCKIH VIH VIL VIL VIH VIH 1 2VDDQ 1...

Page 1654: ... PCICLK DCLKIN Input Display input control signal 1 Input Figure 32 73 Display Timing with Respect to PCICLK DCLKIN Display output control signal 2 Output Digital data for display 3 Output tDD tDCKH tDCYC tDD tDD DEVSEL DCLKOUT Output Figure 32 74 Display Timing with Respect to DEVSEL DCLKOUT ...

Page 1655: ...Synchronous Mode 32 4 AC Characteristic Test Conditions The AC characteristic test conditions are as follows DDR pin only Input output signal reference level MDQS MDQS cross point MCK MCK cross point Other than above VDDQ DDR 2 Input pulse level VSSQ to VDDQ DDR Input rise fall time 0 25 ns Other pins Input output signal reference level VDDQ 2 Input pulse level VSSQ to VDDQ Input rise fall time 1 ...

Page 1656: ... IOH CL RT Reference level LSI output pin DUT output Figure 32 76 Output Load Circuit Notes 1 CL is the total value including the capacitance of the test jig The capacitance of each pin is set to 30 pF 2 RT 50Ω DDR pin AUD pin 3 IOL 24 5 mA DDR pin AUD pin 4 mA PC pin 2 mA other pins IOH 24 5 mA DDR pin AUD pin 4 mA PC pin 2 mA other pins ...

Page 1657: ...8 REJ09B0261 0100 Appendix A Package Dimensions Figure A 1 Package Dimensions 436 Pin BGA Note The Tj junction temperature of this LSI becomes over 125 C So a careful thermal design is necessary Use a heat sink or forced air cooling to lower the Tj ...

Page 1658: ... MHz Frequency vs Input Clock Clock Operating Mode 4 3 2 1 0 Min Max Divider 1 PLL 1 Ick Uck SHck GAck DUck Pck DDRck Bck 0 L L L L L 36 18 18 9 9 3 18 6 1 L L L L H 36 18 18 9 9 3 2 18 3 2 2 L L L H L 36 12 12 6 6 3 12 6 3 L L L H H 12 17 1 36 12 12 6 6 3 2 12 3 2 16 H L L L L 23 34 1 36 18 9 9 9 2 9 2 3 2 9 3 17 H L L L H 18 9 9 9 2 9 2 3 4 9 3 4 18 H L L H L 18 6 6 3 3 3 2 6 3 19 H L L H H 18 6...

Page 1659: ...rohibited Setting prohibited H MPX interface 32 bits H L L SRAM interface 64 bits H SRAM interface 8 bits H L SRAM interface 16 bits H SRAM interface 32 bits Note The MODE6 pin is output state after power on reset Table B 3 Endian Pin Value MODE8 Endian L Big endian H Little endian Table B 4 Master Slave Pin Value MODE9 Master Slave L Slave H Master Table B 5 Clock Input Pin Value MODE10 Clock Inp...

Page 1660: ...splay unit Table B 7 Boot Address Mode Pin Value MODE13 Boot address Mode L 29 bit address mode H 32 bit address extended mode Table B 8 Mode Control Pin Value MODE14 Mode L Setting prohibited H Normal operation Table B 9 Mode Control Pin Value MPMD Mode L Emulation support mode H LSI operation mode Note When using emulation support mode refer to the emulator manual of the SH7785 ...

Page 1661: ...23 16 default LBSC I O Z K K Z D 23 16 Port G 7 0 GPIO I O K K Z D 15 0 D 15 0 LBSC I O Z K K Z CS 6 0 CS 6 0 LBSC O H m PZ s 1 K K PZ Z BACK BSREQ default LBSC I O H 2 K K O BACK BSREQ Port M0 GPIO I O K K O BREQ BSACK default LBSC I O PZ K K I BREQ BSACK Port M1 GPIO I O K K I BS BS LBSC O H m PZ s 1 K K PZ Z R W R W LBSC O H m PZ s 1 K K PZ Z RD FRAME RD FRAME LBSC O H m PZ s 1 K K PZ Z RDY RDY...

Page 1662: ... O SCIF2_TXD SCIF O PZ Z O O O MMCCMD MMCIF I O PI I K K K DACK2 SCIF2_TXD MMCCMD SIOF_TXD SIOF_TXD SIOF O H K K K Port K4 default GPIO I O PI K K K DACK3 DMAC O O O O O SCIF2_SCK SCIF I O I K K K MMCDAT MMCIF I O I K K K DACK3 SCIF2_SCK MMCDAT SIOF_SCK SIOF_SCK SIOF I O L K K K STATUS0 default RESET O H H L H L DRAK0 DMAC O O O O O STATUS0 DRAK0 Port K7 GPIO I O K K K K STATUS1 default RESET O H ...

Page 1663: ...I PI I DREQ2 INTB INTB PCIC I K K K Port L6 default GPIO I O PI K K K DREQ3 DMAC I PI I PI I PI I PI I DREQ3 INTC INTC PCIC I K K K MCLK 1 0 MCLK 1 0 DBSC2 O L K K K MCLK 1 0 MCLK 1 0 DBSC2 O L K K K MDQS 3 0 MDQS 3 0 DBSC2 I O Z K K K MDQS 3 0 MDQS 3 0 DBSC2 I O Z K K K MDM 3 0 MDQ 3 0 DBSC2 O H K K K MDQ 31 0 MDQ 31 0 DBSC2 I O Z K K K MCKE MCKE DBSC2 O L K K K MCAS MCAS DBSC2 O L K K K MRAS MRA...

Page 1664: ...t B 1 0 GPIO I O K K K AD 15 12 PCIC I O PZ K K K D 47 44 LBSC I O PZ K K Z DB 3 0 DU O PZ K K K K D 47 44 AD 15 12 DB 3 0 3 Port C 7 4 GPIO I O K K K AD 11 8 PCIC I O PZ K K K D 43 40 LBSC I O PZ K K Z DG 5 2 DU O PZ K K K K D 43 40 AD 11 8 DG 5 2 3 Port C 3 0 GPIO I O K K K AD 7 6 PCIC I O PZ K K K D 39 38 LBSC I O PZ K K Z DG 1 0 DU O PZ K K K K D 39 38 AD 7 6 DG 1 0 3 Port D 7 6 GPIO I O K K K...

Page 1665: ... K K REQ3 3 Port E3 GPIO I O PZ K K K REQ 2 1 PCIC I PZ K K K REQ 2 1 3 Port E4 E5 GPIO I O PZ K K K DEVSEL PCIC I O PZ K K K DCLKOUT DU O PZ K K K DEVSEL DCLKOUT 3 Port P5 GPIO I O PZ K K K PCIFRAME PCIC I O PZ K K K VSYNC DU I O PZ K K K PCIFRAME VSYNC 3 Port P0 GPIO I O PZ K K K IDSEL IDSEL PCIC I I I K I INTA PCIC I O PZ K K K INTA 3 Port Q4 GPIO I O PZ K K K IRDY PCIC I O PZ K K K HSYNC DU I ...

Page 1666: ...4 GPIO I O PZ K K K TRDY PCIC I O PZ K K K DISP DU O PZ K K K TRDY DISP 3 Port P2 GPIO I O PZ K K K CLKOUT CLKOUT CPG O O K K K CLKOUTENB CLKOUTENB CPG O H K K K PRESET PRESET RESET I I I I I NMI NMI INTC I PI PI I PI I PI I MRESETOUT default RESET O H L O O MRESETOUT IRQOUT IRQOUT INTC O H O O O IRQ IRL 3 0 IRQ IRL 3 0 INTC I PI I I I MODE0 power on reset CPG I I Port L4 default GPIO I O K K K IR...

Page 1667: ...MODE3 IRQ IRL7 FD7 FD7 FLCTL I O K K K K MODE4 power on reset CPG I I Port N5 default GPIO I O K K K SCIF3_TXD SCIF O Z O O O MODE4 SCIF3_TXD FCLE FCLE FLCTL O K K K K MODE5 power on reset LBSC I I MODE5 SIOF_MCLK SIOF_MCLK default SIOF I I I I I MODE6 power on reset LBSC I I MODE6 SIOF_SYNC SIOF_SYNC default SIOF I O O 2 K K K MODE7 power on reset LBSC I I Port N4 default GPIO I O K K K SCIF3_RXD...

Page 1668: ... I I I I I FD2 FLCTL I O K K K K MODE11 power on reset LBSC I I Port N0 default GPIO I O K K K SCIF4_SCK SCIF I O I K K K MODE11 SCIF4_SCK FD3 FD3 FLCTL I O K K K K MODE12 power on reset LBSC I I Port L0 default GPIO I O K K K DRAK3 DMAC O O O O O MODE12 DRAK3 CE2B CE2B LBSC O K K K K MODE13 MMU I I Port J0 default GPIO I O K K K TCLK TMU I I I I I MODE13 power on reset TCLK IOIS16 IOIS16 LBSC I K...

Page 1669: ... H2 default GPIO I O PI K K K SCIF0_SCK SCIF I O I K K K HSPI_CLK HSPI I O Z K K K SCIF0_SCK HSPI_CLK FRE FRE FLCTL O O K K K Port H0 default GPIO I O PI K K K SCIF0_TXD SCIF O Z O K O HSPI_TX HSPI O Z K K K SCIF0_TXD HSPI_TX FWE FWE FLCTL O O K K K Port H6 default GPIO I O PI K K K SCIF1_RXD SCIF1_RXD SCIF I I I I I Port H7 default GPIO I O PI K K K SCIF1_SCK SCIF1_SCK SCIF I O I K K K Port H5 de...

Page 1670: ... Port J4 default GPIO I O PI K K K SIOF_SYNC SIOF I O L K K K HAC0_SYNC HAC O O O O O SIOF_SYNC HAC0_SYNC SSI0_WS SSI0_WS SSI I O I K K K Port J6 default GPIO I O PI K K K SIOF_TXD SIOF O H K K K HAC0_SDOUT HAC O O O O O SIOF_TXD HAC0_SDOUT SSI0_SDATA SSI0_SDATA SSI I O I K K K Port J1 default GPIO I O PI K K K HAC1_BITCLK HAC I I I I I HAC1_BITCLK SSI1_CLK SSI1_CLK SSI I I I I I Port J7 default G...

Page 1671: ... UDI I I I I I Legend Disabled not selected or not supported m LBSC master mode s LBSC slave mode I Input O Output H High level output L Low level output Z High impedance state PI Input and pulled up with a built in pull up resistance PZ High impedance and pulled up with a built in pull up resistance K Retain the previous pin state POR Power on reset Notes 1 Depends on the MODE9 pin setting 2 Afte...

Page 1672: ...15 8 LBSC I O Open D 7 0 D 7 0 LBSC I O Must be used CS 6 1 CS 6 1 LBSC O Open CS0 CS0 LBSC O Must be used BACK BSREQ default LBSC I O BACK BSREQ Port M0 GPIO I O Open BREQ BSACK default LBSC I O BREQ BSACK Port M1 GPIO I O Pulled to VDDQ BS BS LBSC O Open R W R W LBSC O Open RD FRAME RD FRAME LBSC O Open RDY RDY LBSC I Pulled down to VSS 1 WE0 REG WE0 REG LBSC O Open WE1 WE1 LBSC O Open WE2 IORD ...

Page 1673: ... MMCDAT MMCIF I O DACK3 SCIF2_SCK MMCDAT SIOF_SCK SIOF_SCK SIOF I O Open STATUS0 default RESET O DRAK0 DMAC O STATUS0 DRAK0 Port K7 GPIO I O Open STATUS1 default RESET O DRAK1 DMAC O STATUS1 DRAK1 Port K6 GPIO I O Open Port L5 default GPIO I O DRAK2 DMAC O DRAK2 CE2A CE2A LBSC O Open Port K3 default GPIO I O DREQ0 DREQ0 DMAC I Open Port K2 default GPIO I O DREQ1 DREQ1 DMAC I Open Port L7 default G...

Page 1674: ... MCAS DBSC2 O Open MRAS MRAS DBSC2 O Open MCS MCS DBSC2 O Open MWE MWE DBSC2 O Open MODT MODT DBSC2 O Open MA 14 0 MA 14 0 DBSC2 O Open MBA 2 0 MBA 2 0 DBSC2 O Open MBKPRST MBKPRST DBSC2 I Pulled up to VDD DDR AD 31 24 PCIC I O D 63 56 LBSC I O D 63 56 AD 31 24 Port A 7 0 GPIO I O Open 2 AD 23 18 PCIC I O D 55 50 LBSC I O D 55 50 AD 23 18 Port B 7 2 GPIO I O Open 2 AD 17 16 PCIC I O D 49 48 LBSC I...

Page 1675: ...D 5 0 DR 5 0 Port D 5 0 GPIO I O Open 2 CBE 3 0 PCIC I O WE 7 4 LBSC O WE 7 4 CBE 3 0 Port R 3 0 GPIO I O Open 2 GNT0 GNTIN PCIC I O GNT0 GNTIN Port Q3 GPIO I O Open 2 GNT3 PCIC O MMCCLK MMCIF O GNT3 MMCCLK Port E0 GPIO I O Open GNT 2 1 PCIC O GNT 2 1 Port E1 E2 GPIO I O Open REQ0 REQOUT PCIC I O REQ0 REQOUT Port Q2 GPIO I O Open 2 REQ3 PCIC I REQ3 Port E3 GPIO I O Open 2 or pulled up to VDDQ when...

Page 1676: ...LOCK PCIC I O ODDF DU I O LOCK ODDF Port P3 GPIO I O Open 2 PAR PAR PCIC I O Open 2 PCICLK PCIC I PCICLK DCLKIN DCLKIN DU I When the bus mode selected by MODE11 and MODE12 pins is a PCI host bus bridge or a PCI normal non host mode clock must be input to the PCICLK pin When the bus mode selected by MODE11 and MODE12 pins is a Local bus or Display Unit mode PCICLK pin must be pulled up to VDDQ or p...

Page 1677: ...0 INTC I Pulled up to VDDQ MODE0 power on reset CPG I Must be used during power on reset Port L4 default GPIO I O IRQ IRL4 INTC I MODE0 IRQ IRL4 FD4 FD4 FLCTL I O Open MODE1 power on reset CPG I Must be used during power on reset Port L3 default GPIO I O IRQ IRL5 INTC I MODE1 IRQ IRL5 FD5 FD5 FLCTL I O Open MODE2 power on reset CPG I Must be used during power on reset Port L2 default GPIO I O IRQ ...

Page 1678: ...r on reset MODE6 SIOF_SYNC SIOF_SYNC SIOF I O Open MODE7 power on reset LBSC I Must be used during power on reset Port N4 default GPIO I O SCIF3_RXD SCIF I MODE7 SCIF3_RXD FALE FALE FLCTL O Open MODE8 power on reset LBSC I Must be used during power on reset Port N3 default GPIO I O SCIF3_SCK SCIF I O MODE8 SCIF3_SCK FD0 FD0 FLCTL I O Open MDOE9 power on reset LBSC I Must be used during power on re...

Page 1679: ...DMAC O MODE12 DRAK3 CE2B CE2B LBSC O Open MODE13 MMU I Must be used during power on reset Port J0 default GPIO I O TCLK TMU I MODE13 TCLK IOIS16 IOIS16 LBSC I Open MODE14 MODE14 CPG I Must be used during power on reset Pulled up to VDDQ EXTAL EXTAL CPG I Must be used XTAL XTAL CPG O Open Port H4 default GPIO I O SCIF0_CTS SCIF I O INTD PCIC I SCIF0_CTS INTD FCE FCE FLCTL O Open Port H3 default GPI...

Page 1680: ... Port H7 default GPIO I O SCIF1_SCK SCIF1_SCK SCIF I O Open Port H5 default GPIO I O SCIF1_TXD SCIF1_TXD SCIF O Open SCIF2_RXD default SCIF I SCIF2_RXD SIOF_RXD SIOF_RXD SIOF I Open Port J3 default GPIO I O SIOF_MCLK SIOF I SIOF_MCLK HAC_RES HAC_RES HAC O Open Port J5 default GPIO I O SIOF_RXD SIOF I HAC0_SDIN HAC I SIOF_RXD HAC0_SDIN SSI0_SCK SSI0_SCK SSI I O Open Port J2 default GPIO I O SIOF_SC...

Page 1681: ... HAC1_SYNC SSI1_WS SSI1_WS SSI I O Open Port N7 GPIO I O SCIF5_RXD SCIF I HAC1_SDIN HAC I SCIF5_RXD HAC1_SDIN SSI1_SCK SSI1_SCK SSI I O Open Port N6 GPIO I O SCIF5_SCK SCIF I O HAC1_SDOUT HAC O SCIF5_SCK HAC1_SDOUT SSI1_SDATA SSI1_SDATA SSI I O Open THDAG THDAG Connected to VSS THDAS THDAS Connected to VSS THDCTL THDCTL Connected to VSS THDCD THDCD Connected to VSS VDDQ TD VDDQ TD Connected to VSS...

Page 1682: ...it in PPUPR1 GPIO to 1 to pull up off the RDY pin s pulled up 2 The MODE 12 11 pin settings should be LBSC mode to be open these pins 3 Specify LBSC mode or DU mode by the MODE 12 11 pins 4 When not using emulator the pin should be fixed to ground or connected to another pin which operates in the same manner as PRESET However when fixed to a ground pin the following problem occurs Since the TRST p...

Page 1683: ...D18 VDD33 Within 300 ms after turning on one power supply series turn on all the other power supply series Turning Off Power Supply There is no restriction for the order of the power supply between each power supply series VDD10 VDD18 VDD33 Within 300 ms after turning off the one power supply series turn off all the other power supply series 300 t or 0 ms 0 1 V V min 0 9 V 0 2 V V VDD10 VDD18 tran...

Page 1684: ... restriction on the sequence in which the above power supplies are powered on Ensure that all the power supplies start within 300 ms of the start of a power supply other than VDD DDR Power Off Sequence There is no restriction on the sequence in which the above power supplies are powered off Ensure that all the power supplies stop within 300 ms of the stop of a power supply other than VDD DDR 300ms...

Page 1685: ... VDD33 Turning On Power Supply There is no restriction for the order of the power supply between each power supply series except that the potential difference of the one power supply series is less than 0 3V Turning Off Power Supply There is no restriction for the order of the power supply between each power supply series except that the potential difference of the one power supply series is less ...

Page 1686: ...ble E 1 Register Configuration Register Name Abbrev R W Initial Value P4 Address Area 7 Address Access Size Processor Version Register PVR R H 1030 07xx H FF00 0030 H 1F00 0030 32 Product Register PRR R H 0000 02xx H FF00 0044 H 1F00 0044 32 Legend x Undefined Processor Version Register PVR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit version information version information 0 0 0 1 0 0 0 0 ...

Page 1687: ... Table F 1 SH7785 Product Lineup Product Type Voltage Operating Frequency Part Number Operating Temperature Package SH7785 1 1 V 600 MHz R8A77850AADBG 40 to 85 C 436 pin BGA R8A77850AADBGV 436 pin BGA Lead Free R8A77850ANBG 20 to 85 C 436 pin BGA R8A77850ANBGV 436 pin BGA Lead Free ...

Page 1688: ...Appendix Rev 1 00 Jan 10 2008 Page 1658 of 1658 REJ09B0261 0100 ...

Page 1689: ...cation Date Rev 1 00 January 10 2008 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solutions Corp 2008 Renesas Technology Corp All rights reserved Printed in Japan ...

Page 1690: ... 7898 Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2377 3473 Renesas Technology Taiwan Co Ltd 10th Floor No 99 Fushing North Road Taipei Taiwan Tel 886 2 2715 2888 Fax 886 2 3518 3399 Renesas Technology Singapore Pte Ltd 1 Harbour Front Avenue 06 10 Keppel Bay Tower Singapore 098632 Tel ...

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Page 1692: ...SH7785 Hardware Manual ...

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