Renesas QB-78F1030, User Manual

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QB-78F1030 CHAPTER 4 CAUTIONS
R20UT0289JJ0100 Rev. 1.00 Page 27 of 28
Sep 30, 2010
4.1.7 Absolute maximum rating of p62 pin
The absolute maximum rating of the P62 pin differs between the target device and emulator.
IECUBE may be damaged if a voltage greater than 5.5 V is applied.
Table 4-3. Absolute maximum rating of P62 pin
Item Absolute maximum rating of P62 pin
Target device 6.5 V
IECUBE 5.5 V
4.1.8 FLMD0 pin
The processing for the FLMD0 pin differs from that of the target device.
Table 4-4. FLMD0 Pin Processing
Item FLMD0 Pin Processing
Target device Protection resistance: 4.5 k
Ω
(TYP.)
Pull-up/pull-down resistors: 10 k
Ω
(MIN.), 20 k
Ω
(TYP.), 100 k
Ω
(MAX.)
IECUBE Protection resistance: 4.7 k
Ω
(TYP.)
Pull-up/pull-down resistors: 29 k
Ω
(MIN.), 30 k
Ω
(TYP.), 32 k
Ω
(MAX.)
4.1.9 Power-on-clear (POC) voltage value
The power-on-clear (POC) voltage value differs from that of the target device.
Table 4-5. Power-on-clear (POC) voltage value
Item MIN. TYP. MAX.
VPOR 1.52 V 1.61 V 1.70 V Target device
VPDR 1.50 V 1.59 V 1.68 V
VPOR
−
1.65 V
−
IECUBE
VPDR
−
1.55 V
−
4.1.10 TTL input buffer characteristics
If the port input mode register (PIM) is used to set the input of a pin that can be set for the TTL buffer to the TTL level,
the high-level input voltage characteristics differ between the target device and emulator. See Table 4-6 for details.
The following pins can be set for the TTL buffer.
Target pins: P03, P04, P10, P11, P142, P143
Table 4-6. High-Level Input Voltage Characteristics
Item Conditions MIN
4.0 V
≤
V
DD
≤
5.5 V 2.2 V
2.7 V
≤
V
DD
< 4.0 V 2.0 V
Target device
1.8 V
≤
V
DD
< 2.7 V 1.6 V
IECUBE
Note
1.8 V
≤
V
DD
≤
5.5 V 2.0 V
Note Use CMOS input if V
DD
is 2.0 V or less.