Renesas mPD720231 User Manual Download

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REVISION HISTORY

PD720231 User’s Manual: Hardware

Description

Rev. Date

Page Summary

1.00

Mar 1, 2013

−

First Edition issued

Summary of Contents for mPD720231

Page 1: ...ime of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Re...

Page 2: ...range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electroni...

Page 3: ...tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be...

Page 4: ...USB logo is a trademark of USB Implementers Forum Inc...

Page 5: ...is manual should already have a general knowledge of electronics logic circuits and microcomputers Notation This manual uses the following conventions Data bit significance High order bits on the left...

Page 6: ...ds 10 4 2 BOS Binary device Object Store Descriptor 11 4 2 1 USB2 0 Extension Descriptor High Full speed only 11 4 2 2 Super Speed USB Device Capability Descriptor High Full speed only 11 4 3 Configur...

Page 7: ...nction 23 6 6 External trigger in 23 7 How to Connect to External Elements 24 7 1 Handling Unused Pins 24 7 2 Upstream Port Connection 25 7 3 RREF Connection 26 7 4 Crystal Connection 26 7 5 External...

Page 8: ...ort Connection 25 Figure 7 2 RREF Connection 26 Figure 7 3 Crystal Connection 26 Figure 7 4 External Serial ROM Connection 27 Figure 7 6 Serial ATA Interface Connection 28 Figure 7 7 On Chip LDO Pin C...

Page 9: ...erface Alternate Setting for each speed mode 8 Table 3 2 Configuration for Super speed UASP mode 8 Table 3 3 Configuration for Super speed BOT mode 9 Table 3 4 Configuration for Super speed UASP mode...

Page 10: ...l speed Supports Mass Storage Class UASP USB Attached SCSI Protocol Supports Mass Storage Class BOT Bulk Only Transport Includes SCSI Command hardware accelerator Supported number of stream is 32 Task...

Page 11: ...t 1 4 Block Diagram Figure 1 1 PD720231 Block Diagram CPU USB LINK Memory Work GPIO CCU SATAIII Host Controller USB2 0 PHY SATA Gen3 PHY PD720231 Regulator ROM Peripherals USB3 0 PHY USB Endpoint Cont...

Page 12: ...HY SATA Gen3 PHY Integrated SATAIII Gen1 1 5Gbps Gen2 3 0Gbps and Gen3 6 0 Gbps compliance transceiver This is controlled by SATAIII host USB Endpoint Controller EPC Transport Protocol layer This bloc...

Page 13: ...3 1 5 Pin Configuration 48 pin QFN 6 x 6 PD720231K8 611 BAE A Figure 1 2 Pin Configuration Top View GPIO0 SPISO VDD33OUT GPIO1 SPISCK VDD10 GPIO2 SPISI GPIO6 ACT VDDGPIO GPIO4 GPIO5 VBUSM V50IN GPIO3...

Page 14: ...3 3 V power supply for regulator analog circuit AVDD33IN2 Note 46 Regulator 3 3 V power supply for regulator analog circuit LX1 44 Regulator 1 0 V output from the on chip regulator FB 47 Regulator Fe...

Page 15: ...e Level Function U3RXP 23 I USB3 USB3 0 receive data D signal for SuperSpeed U3RXN 22 I USB3 USB3 0 receive data D signal for SuperSpeed U3TXP 20 O USB3 USB3 0 transmit data D signal for SuperSpeed U3...

Page 16: ...purpose I O GPIO6 ACT Note1 9 5 V tolerant buffer General purpose I O or Disk Activity LED GPIO7 CLKOUT 41 General purpose I O or 30 MHz clock output GPIO8 37 General purpose I O GPIO9 EXTINT 48 I O 3...

Page 17: ...figuration Interface Alternate Setting Endpoint Protocol 0 1 Bulk OUT 2 Bulk IN BOT Super speed 1 0 1 1 Bulk OUT Stream 2 Bulk IN Stream 3 Bulk OUT 4 Bulk IN Stream UASP 0 1 Bulk OUT 2 Bulk IN BOT Hig...

Page 18: ...Size Stream 0 IN OUT Control 64 bytes 1 1 OUT Bulk 512 bytes 1 Not available 2 IN Bulk 512 bytes 1 Not available 3 OUT Bulk 512 bytes 1 Not available 4 IN Bulk 512 bytes 1 Not available 3 4 High speed...

Page 19: ...s Code 6 bDeviceProtocol 1 00h Protocol Code 7 bMaxPacketSize0 1 09h or 40h Maximum packet size for this speed 09h 512 bytes for Super speed 40h 64 bytes for High Full speed 8 idVender 2 045Bh Vender...

Page 20: ...erating in USB2 0 High speed mode Offset Field Size Value Description 0 bLength 1 07h Size of descriptor 1 bDescriptorType 1 10h Device capability descriptor type 2 bDevCapabilityType 1 02h Capability...

Page 21: ...bus in this configuration when the device is fully operational Expressed in 2 mA units when the device is operating in High Full speed mode and in 8 mA units when operating in Super speed mode 4 4 In...

Page 22: ...as its own descriptor This descriptor contains the information required by the host to determine the bandwidth requirements of each endpoint An endpoint descriptor is always returned as part of the co...

Page 23: ...of descriptor 1 bDescriptorType 1 05h Endpoint descriptor type 2 bEndpointAddress 1 82h Address 2 Direction IN 3 bmAttributes 1 02h Endpoint s attributes Bulk 4 wMaxPacketSize 2 0400h or 0200h or 0040...

Page 24: ...ze 0400h 1024 bytes in Super speed mode 0200h 512 bytes in High speed mode 6 bInterval 1 00h Interval for polling endpoint for data transfers 2 SuperSpeed Endpoint Companion Descriptor Super speed onl...

Page 25: ...in Super speed mode 0200h 512 bytes in High speed mode 6 bInterval 1 00h Interval for polling endpoint for data transfers 2 SuperSpeed Endpoint Companion Descriptor Super speed only Offset Field Size...

Page 26: ...24 bytes in Super speed mode 0200h 512 bytes in High speed mode 6 bInterval 1 00h Interval for polling endpoint for data transfers 2 SuperSpeed Endpoint Companion Descriptor Offset Field Size Value De...

Page 27: ...1024 bytes in Super speed mode 0200h 512 bytes in High speed mode 6 bInterval 1 00h Interval for polling endpoint for data transfers 2 SuperSpeed Endpoint Companion Descriptor Offset Field Size Value...

Page 28: ...with the serial ROM utility Language ID string descriptor index 0 Offset Field Size Value Description 0 bLength 1 4h Size of descriptor 1 bDescriptorType 1 03h String descriptor Type 2 WLANGID 0 2 040...

Page 29: ...9 Reserved 1 00h Reserved for future use 4 8 Other_Speed_Configuration Descriptor High Full speed only An other_speed_configuration descriptor describes a configuration of a high speed capable device...

Page 30: ...irmware and uses parameters and firmware patches from HDD SSD devices Utility tool is used to set these parameters and patches into HDD SSD Please refer to the application note of utility tool in more...

Page 31: ...eneral purpose I O or SPI master output slave input GPIO3 SPICSB General purpose I O or SPI chip select for the external serial flash ROM GPIO4 General purpose I O GPIO5 General purpose I O GPIO6 ACT...

Page 32: ...s level during U3 L2 6 5 Clockout function The PD720231 provides clock signal for external device from GPIO7 CLKOUT GPIO7CLKOUT starts clock output after PD720231 read parameter from external SROM or...

Page 33: ...Direction Connection Method GPIO0 SPISO GPIO1 SPISCK GPIO2 SPISI GPIO3 SPICSB I O Please refer to Table 5 1 GPIO4 GPIO7 CLKOUT GPIO8 GPIO9 EXTINT I O Open GPIO5 GPIO6 ACT I O Pull up or down on board...

Page 34: ...apacitance that can be placed on VBUS line should be less than 10 F for the inrush current limiting requirement specified by USB3 0 specification Please see section 11 4 4 1 in USB3 0 specification fo...

Page 35: ...two or more resistors in series or parallel should not be used in place of a single 1 60 K resistor 7 4 Crystal Connection Figure 7 3 Crystal Connection The following crystal is evaluated on our refe...

Page 36: ...ion EN25F05 EN25F10 EN25F20 EN25LF10 EN25LF20 EN25LF40 Macronix International MX25V512E MX25V1006E MX25V2006E MX25V4005C MX25V4006E MX25L512E MX25L1006E MX25L2006E MX25L4006E MX25L5121E MX25L1021E MX2...

Page 37: ...ements R19UH0094EJ0100 Rev 1 00 Page 28 of 30 Mar 1 2013 7 6 Serial ATA Interface Connection Figure 7 6 Serial ATA Interface Connection PD720231 SATA Connector STXP STXN SRXN SRXP A 0 01 F 0 01 F 0 01...

Page 38: ...r 1 2013 7 7 On Chip LDO 5 V to 3 3 V Connection It is prohibited not to use internal LDO and V50IN must be always supplied Figure 7 7 On Chip LDO Pin Connection VDD33OUT PD720231 3 3V 4 7uF V50IN 5V...

Page 39: ...nded on AVDD33IN1 and AVDD33IN2 Common impedance coupling between AVDD33IN1 and AVDD33IN2 must be avoided In case of not using internal switching regulators please handle each pins as in Figure 7 9 Fi...

Page 40: ...C 1 REVISION HISTORY PD720231 User s Manual Hardware Description Rev Date Page Summary 1 00 Mar 1 2013 First Edition issued...

Page 41: ...PD720231 User s Manual Hardware Publication Date Rev 1 00 Mar 1 2013 Published by Renesas Electronics Corporation...

Page 42: ...05 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21 6887 7858 7898 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Centu...

Page 43: ...PD720231 R19UH0094EJ0100...

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