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PD720231
1.
Overview
R19UH0094EJ0100 Rev 1.00
Page 3 of 30
Mar 1, 2013
CPU
Integrated 32bit RISC CPU.
CPU Peripherals
Includes bus controller, interrupt controller, timer, GPIO and so on.
Work RAM
Integrated Work RAM for data.
ROM
Integrated Boot ROM.
SATA III Host
Controller
The SATA III host supports SATA Gen1 1.5 Gbps, Gen2 3.0 Gbps,
and Gen3 6.0 Gbps. Dedicated bus realizes SuperSpeed interface
between SATA III host and Direct Command Controller.
SATA LINK
Link layer translates data packets between SATA host and SATA
PHY.
SATA Gen3 PHY
Integrated SATAIII Gen1 1.5Gbps, Gen2 3.0Gbps, and Gen3 6.0
Gbps compliance transceiver. This is controlled by SATAIII host.
USB Endpoint
Controller (EPC)
Transport / Protocol layer. This block supports USB Mass Storage
class USB Attached SCSI Protocol and Bulk Only Transport.
USB LINK
Link layer defined in USB specification, which maintains Link
connectivity with USB host controller and hub.
USB3.0 PHY
For SuperSpeed Tx/Rx
USB2.0 PHY
For USB High/Full-speed Tx/Rx
CCU
Integrated clock controller to manage system power consumption, and
system reset controller.
OSC
Internal oscillator block.
3.3 V to 1.0 V
Regulator
Regulator to convert 3.3 V to 1.0 V
5 V to 3.3 V Regulator
Regulator to convert 5 V to 3.3 V
