H8S Family
LCD Display Using 1/4 Duty Drive (LCD Controller/Driver)
REJ06B0486-0100/Rev.1.00
March 2005
Page 15 of 19
5. Flowchart
(1) Main Routine
main()
*
Set the I bit to 1 to disable interrupts
MSTPCRD = H'BF
Clear bit 6 to 0 to clear LCD
controller/driver module stop
mode
lcdram = LCD RAM
Set LCD RAM start address in lcdram
i = 0
i < 20
All 20 bytes of LCD RAM
cleared?
lcdram[i] = 0
i++
Some still not cleared
LPCR = H'C3
Set 1/4 duty and SEG21 to
SEG36 in segment driver
All cleared
LCR = H'31
Separate LCD power supply
split-resistors from V
CC
Operate LCD controller/driver
Display LCD RAM data
Use
φ
SUB/2 as clock source
Frame 64 Hz
LCR2 = H'00
Select A waveform, halt triple
step-up voltage circuit, select 1 as
charge/discharge pulse duty cycle
lcdram[7]=H'76 "H "
lcdram[6]=H'F7 "8 "
lcdram[5]=H'BD "S."
lcdram[4]=H'E3 "2 "
lcdram[3]=H'E3 "2 "
lcdram[2]=H'F5 "6 "
lcdram[1]=H'F7 "8 "
lcdram[0]=H'71 "F "
Set "H8S.2268F" in LCD RAM
Clear the I bit to 0 to enable interrupts
lcdram = H'00000A
Set LCD RAM addresses
corresponding to SEG21 and
SEG22 in lcdram
Note: *In this sample task the stack pointer is set by INIT.SRC
(assembly language).
