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(3) Multiplex Bus, With Wait, Accessing External Memory Area
Table 5.4 and Figure 5.3 show the bus timing in the memory expansion mode and the microprocessor
mode (with wait, accessing external memory area and using multiplex bus).
Table 5.4 Memory expansion mode and microprocessor mode (with wait, multiplex bus)
*1 Calculated by the following formulas accord-
ing to the frequency of BCLK.
Th (RD-AD)=
10
9
f(BCLK)x2
[ns]
*2 Calculated by the following formulas accord-
ing to the frequency of BCLK.
○○○○○○○○○
○○○○○○○○○○○○○○○○○○○
Td (BCLK-AD)
Th (BCLK-AD)
Th (RD-AD)
Th (WR-AD)
Td (BCLK-CS)
Th (BCLK-CS)
Th (RD-CS)
Th (WR-CS)
Td (BCLK-RD)
Th (BCLK-RD)
Td (BCLK-WR)
Th (BCLK-WR)
Td (BCLK-DB)
Th (BCLK-DB)
Td (DB-WR)
Th (WR-DB)
Td (BCLK-ALE)
Th (BCLK-ALE)
Td (AD-ALE)
Th (ALE-AD)
Td (AD-RD)
Td (AD-WR)
Tdz (RD-AD)
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip-select output delay time
Chip-select output hold time (BCLK standard)
Chip-select output hold time (RD standard)
Chip-select output hold time (WR standard)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)
ALE output delay time (BCLK standard)
ALE output hold time (BCLK standard)
ALE output delay time (Address standard)
ALE output hold time (Address standard)
After address RD signal output delay time
After address WR signal output delay time
Address output floating start time
Min.
4
(
*
1)
(
*
1)
4
(
*
1)
(
*
1)
0
0
4
(
*
1)
(
*
1)
-4
(
*
1)
30
0
0
Max.
25
25
25
25
40
25
8
Min.
(
*
2)
(
*
2)
Max.
52
34
35
37
Actual MCU
[ns]
This product
[ns]
Symbol
Item
See left
See left
See left
See left
See left
See left
See left
See left
See left
See left
See left
See left
See left
See left
See left
See left
See left
Th (WR-AD)=
10
9
f(BCLK)x2
[ns]
Th (RD-CS)=
10
9
f(BCLK)x2
[ns]
Th (WR-CS)=
10
9
f(BCLK)x2
[ns]
Td (DB-WR)=
10
9
x3
f(BCLK)x2
-40 [ns]
Th (WR-DB)=
10
9
f(BCLK)x2
[ns]
Td (AD-ALE)=
10
9
f(BCLK)x2
-25 [ns]
Th (RD-AD)=
10
9
f(BCLK)x2
-14 [ns]
Th (WR-AD)=
10
9
f(BCLK)x2
-14 [ns]
Th (RD-CS)=
10
9
f(BCLK)x2
-12 [ns]
Th (WR-CS)=
10
9
f(BCLK)x2
-12 [ns]
Summary of Contents for Emulation Pod M306V2T-RPD-E
Page 8: ... 6 72 MEMO ...
Page 46: ... 44 72 Figure 4 4 Self check procedure ...
Page 59: ... 57 72 Figure 5 7 Connection diagram 2 Control signal ...
Page 62: ... 60 72 MEMO ...
Page 68: ... 66 72 MEMO ...
Page 72: ... 70 72 MEMO ...
