Publication No. REF-000-009-R00
Red Rapids
Page 6
2.4.1 ADC Control Interface
A diagram of the ADC control interface is shown in Figure 2-6. The user has access to
the ADC command and status registers through the control interface SPI port. A list
and description of ADC command and status registers can be found in the device data
sheet listed in section 5.0.
Receiver
ADC
Control
Interface
SPI_CSB
SPI_SDIO
SPI_SCLK
spi_csb(n)
spi_sdi
spi_sdo
spi_clk
Device Configuration
(SPI Bus)
Figure 2-6 ADC Control Interface
2.4.1 ADC Clock Interface
The receiver ADC clock input is sourced by the sample clock distribution network as
shown in Figure 2-7.
Sample Clock
Distribution Network
Receiver
ADC
CLKINP
CLKINM
Figure 2-7 ADC Clock Interface
2.4.2 ADC Data Interface
A diagram of the ADC data interface is shown in Figure 2-8. The interface consists of
a forwarded LVDS data clock, a 16-bit LVDS interleaved data bus and a single over
range LVDS pair. A description of the data transfer protocol can be found in the RX
ADC device data sheet listed in section 5.0.
ADC
Data
Interface
DCOP
DCOM
D(15:0)P
D(15:0)M
rx_clkp
rx_clkn
rx_datap(15:0)
rx_datan(15:0)
rx_ovrp
rx_ovrn
OVRP
OVRM
ADC
Interface
Figure 2-8 ADC Data Interface
