Rx-URME-007 Rev - -2
- Preliminary -
PMC665 Hardware Reference and Installation Manual
Page 8
Ethernet Alliance for 100 Base-FX (which is identical to the FDDI PMD standard - ANSI X.3.166).
The Transceivers are rated for 2000 meter multi-mode fiber cabling.
3.0.6
Control and Data Flow
From the description of the Bridge/co-processor, it will be apparent that control of the Ethernet
interfaces can be either by the host, or the co-processor. This decision can be made on a per-
interface basis. When control is resident in the co-processor, the Ethernet interface is not
detected (or accessible) to the host processor. Data can be transferred between the Ethernet
interface and either the local DRAM buffer or the host PCI bus. Which is appropriate depends
upon the functional requirements to be implemented by the firmware. Allowing data to move
directly from host PCI (and by inference the host memory system) to the Ethernet can reduce
transfer latencies.
Note: (Direct data transfer is not a requirement for sustaining maximum performance. The 100+
Mbytes per second bandwidth of each of the busses on the
PMC665
, combined with their
independent operation provides substantial margin in store (filter) and forward operations.
Thus, implementing sophisticated translation, filtering response or fail-over with the co-
processor does not compromise full Ethernet performance).
3.1
Switch Control (SW1)
SW1 controls the initialization status of the on-card processor. It should
not
be altered from the
factory default which will have been set appropriatly for the ordered configuration. (Processor
Enabled if firmware was specified, Disabled if no firmware was specified)
Switch
Number
Enable
Processor
Disable
Processor
1
Open
Open
2
Open
Open
3
Open
CLOSED
4
Open
CLOSED
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