Rabbit Rabbit 4000, User Manual

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Chapter 4 System Management 31
4. S
YSTEM
M
ANAGEMENT
4.1 Overview
There are a number of basic system peripherals in the Rabbit 4000 processor, some of
which are covered in later chapters. The peripherals covered in this chapter are the periodic
interrupt, the real-time clock, the watchdog timers, the battery-backed onchip-encryption
RAM, and some of the miscellaneous output pins and their control and processor registers
that provide the processor ID and revision numbers.
The periodic interrupt, when enabled, is generated every 16 clocks of the 32 kHz clock
(every 488 µs, or 2.048 kHz). This interrupt can be used to perform periodic tasks.
The real-time clock (RTC) consists of a 48-bit counter that is clocked by the 32 kHz clock.
It is powered by the VBAT pin, and so can be battery-backed. The value in the counter is
not affected by reset, and can only be set to zero by writing to the RTC control register.
The 48-bit width provides a 272-year span before rollover occurs.
There are two watchdog timers in the Rabbit 4000, both clocked by the 32 kHz clock. The
main watchdog timer can be set to time out from 250 ms to 2 seconds, and resets the pro-
cessor if not reloaded within that time. Its purpose is to restart the processor when it
detects that a program gets stuck or disabled.
The secondary watchdog timer can time out from 30.5 µs up to 7.8 ms, and generates a
Priority 3 secondary watchdog interrupt when it is not reset within that time. The primary
use for the secondary watchdog is to act as a safety net for the periodic interrupt — if the
secondary watchdog is reloaded in the periodic interrupt, it will count down to zero if the
periodic interrupt stops occurring. In addition, it can be used as a periodic interrupt on its
own.
The battery-backed onchip-encryption RAM consists of 32 bytes of memory that are
powered by the VBAT pin. Their values are not affected by reset, but are erased if the state
of the SMODE pins changes. These 32 bytes are intended for storing sensitive data (such
as an encryption key) somewhere other than an external memory device. The “tamper-
protection” erase feature prevents loading a program into the onchip-encryption RAM via
the programming port and reading out the bytes.
The following other registers are also described in this chapter.
•
Global Output Control Register (GOCR), which controls the behavior of the CLK,
STATUS, /WDT, and /BUFEN pins
•
Global CPU Register (GCPU), which holds the identification number of the processor.
•
Global Revision Register (GREV), which hold the revision number of the processor.