Rabbit 3000, User Manual

Page: 149 / 266

User’s Manual 141
If it is desired to read the time from the Timer B counter, either during an interrupt caused
by the match pulse or in some other interrupt routine asynchronous to the match pulse, a
special procedure needs to be used to read the counter because the upper 2 bits are in a dif-
ferent register than the lower 8 bits. The following method is suggested.
1. Read the lower 8 bits.
2. Read the upper 2 bits
3. Read the lower 8 bits again
4. If bit 7 changed from 1 to 0 between the first and second read of the lower 8 bits there
has been a carry to the upper 2 bits. In this case read the upper 2 bits again and decre-
ment those 2 bits to get the correct upper 2 bits. Use the first read of the lower 8 bits.
This procedure assumes that the time between reads can be guaranteed to be less than 256
counts. This can be guaranteed in most systems by disabling the priority 1 interrupts,
which will normally be disabled in any case in an interrupt routine.
It is inadvisable to disable the high-priority interrupts (levels 2 and 3) as that defeats their
purpose.
If speed is critical, the three reads of the registers can be performed without testing for the
carry. The three register values can be saved and the carry test can be performed by a
lower priority analysis routine. Since the upper 2 bits are in the register TBCMR at
address 0BEh, and the lower 8 bits are in TBCLR at address 0BFh, both registers can be
read with a single 16-bit I/O instruction. The following sequence illustrates how the regis-
ters could be captured.
; enter from external interrupt on pulse input transition
; 19 clocks latency plus 10 clocks interrupt execution
push af ; 7
push hl
ioi ld a,(TBCLR) ; 11 get lower 8 bits of counter
ioi ld hl,(TBCMR) ;13 get l=upper, h=lower
Timer B can be used for various purposes. The 10-bit counter can be read to record the
time at which an event takes place. If the event creates an interrupt, the timer can be read
in the interrupt routine. The known time of execution of the interrupt routine can be sub-
tracted. The variable interrupt latency is then the uncertainty in the event time. This can be
as little 19 clocks if the interrupt is the highest priority interrupt. If the system clock is 20
MHz, the counter can count as fast as 10 MHz. The uncertainty in a pulse width measure-
ment can be nearly as low as 38 clocks (2 x 19), or about 2 µs for a 20 MHz system clock.
Timer B can be used to change a parallel port output register at a particular specified time
in the future. A pulse train with edges at arbitrary times can be generated with the restric-
tion that two adjacent edges cannot be too close to each other since an interrupt must be
serviced after each edge to set up the time for the next edge. This restriction limits the
minimum pulse width to about 5 µs, depending on the clock speed and interrupt priorities.