Rabbit 3000, User Manual

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User’s Manual 137
The control register (TACR) is laid out as shown in Table 11-4.
The Timer A Prescale Register (TAPR) specifies the main clock for Timer A. By default
Timer A is clocked by peripheral clock divided by two.
The prescale register (TAPR) is laid out as shown in Table 11-4.
The time constant register for each timer (TATxR) is simply an 8-bit data register holding
a number between 0 and 255. This time constant will take effect the next time that the
Timer A counter counts down to zero. The timer counts modulo (divide-by) n+1, where n
is the programmed time constant. The time constant registers are write only. The time
constant registers are listed in Table 11-1.
11.1.2 Practical Use of Timer A
Timer A is disabled (bit 0 in control and status register) on power-up. Timer A is normally
set up while the clock is disabled, but the timer setup can be changed while the timer is
running when there is a need to do so. Timers that are not used should be driven from the
output of A1 and the reload register should be set to 255. This will cause counting to be as
slow as possible and consume minimum power.
As for general-purpose timers, Timer A has seven separate subtimer units, A1 and A2–A7,
that are also referred to as timers.
Most likely, if a serial port is going to be used and a timer is needed to provide the baud clock,
that timer will be set up to be driven directly from the clock, and the interrupt associated with
that timer will be disabled. (Serial port interrupts are generated by the serial port logic.)
The value in the reload register can be changed while the timer is running to change the
period of the next timer cycle. When the reload register is initialized, the contents of the
countdown counter may be unknown, for example, during power-up initialization. If inter-
Table 11-4. Timer A Control Register (adr = 0A4h)
Bit 7
A7
Bit 6
A6
Bit 5
A5
Bit 4
A4
Bit 3
A3
Bit 2
A2
Bits 1, 0
Source A7
0–
pclk
/2
1–A1
Source A6
0–
pclk
/2
1–A1
Source A5
0–
pclk
/2
1–A1
Source A4
0–
pclk
/2
1–A1
Source A3
0–
pclk
/2
1–A1
Source A2
0–
pclk /2
1–A1
00—Interrupt disabled
01—priority 1 interrupt
10—priority 2 interrupt
11—priority 3 interrupt
Table 11-5. Timer A Prescale Register (adr = 0A1h)
Bits 7:1 Bit 0
These bits are
ignored.
0—The main clock for Timer A is the peripheral clock.
1—The main clock for Timer A is the peripheral clock divided by two.