UMTS/HSPA Module Series
WCDMA UGxx Audio Design Note
WCDMA_UGxx_Audio_Design_Note Confidential / Released 10 / 56
For the relations between peripherals, modules and PCM CODEC, please refer to the following figure.
PCM_IN
PCM_OUT
PCM_SYNC
PCM_CLK
I2C_SCL
I2C_SDA
CODEC
Module
VDD_EXT
4.
7K
4.
7K
BCLK
LRCLK
DACDAT
ADCDAT
SCL
SDA
B
IA
S
MICBIAS
MIC+
MIC-
SPK+
SPK-
CLK_OUT
MCLK
Rs
NM
Peripherals
USB
UART
USB
UART
CLK
0R
0R_NM
R1
R2
Figure 2: The Connection Diagram of Peripherals, Module and Codec
1. The communication between the module and peripherals can be realized by UART or USB interface.
2. The MCLK of codec can be provided by peripherals or module. When the MCLK is provided by
module, R1 is mounted and R2 is not mounted. When the MCLK is provided by peripheral, R2 is
mounted and R1 is not mounted.
3. It is recommended to reserve
RC (R=22Ω, C=22pF) circuit on the PCM lines, especially for
PCM_CLK.
4. UGxx modules provide a digital clock output (CLK_OUT) for an external audio codec, the CLK_OUT
function is disabled by default. When CLK_OUT is required, AT command is used to provide the
codec with a 13/26MHz clock generated from the module. A RC (e.g.
R=22Ω, C=47pF) circuit is
recommended to be reserved on CLK_OUT line. Refer to
document [3]
for details. If unused, keep
this pin open.
AT+QPCMON
is used to enable PCM_CLK (BCLK) & PCM_SYNC when there is no audio application.
The
output
frequency
depends
on
the
settings
of
AT+QDAC
:
sync=
<sample_rate>
,
PCM_CLK(BCLK)
=<sample_rate> *
(
<data_length>
+ 1).
AT+QDAC=1,0,0,2,0,0
OK
AT+QPCMON=1
//Enable PCM SYNC & BCLK, SYNC=8k, BCLK=264K
OK
AT+QPCMON=0
//Disable PCM SYNC & BCLK
OK
NOTES
Quectel
Confidential
