Quectel RM500Q-AE, Manual

Page: 10 / 87

5G Module Series
RM500Q-AE&RM502Q-AE Hardware Design
RM500Q-AE&RM502Q-AE_Hardware_Design 10 / 83
Figure Index
Figure 1: Functional Diagram ..................................................................................................................... 18
Figure 2: Pin Assignment ........................................................................................................................... 21
Figure 3: Power Supply Limits during Radio Transmission ....................................................................... 27
Figure 4: Reference Circuit of VCC Pins ................................................................................................... 28
Figure 5: Reference Design of Power Supply ............................................................................................ 28
Figure 6: Turn-on Timing of the Module ..................................................................................................... 29
Figure 7: Turn on the Module with a Host GPIO ........................................................................................ 30
Figure 8: Turn-off Timing through FULL_CARD_POWER_OFF# ............................................................. 31
Figure 9: Turn-off Timing through AT Command and FULL_CARD_POWER_OFF# .............................. 31
Figure 10: Reference Circuit of RESET_N with NPN Driving Circuit ........................................................ 32
Figure 11: Reference Circuit of RESET_N with NMOS Driving Circuit ..................................................... 33
Figure 12: Reference Circuit of RESET_N with Button ...................................................
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Figure 13: Resetting Timing of the Module ................................................................................................ 33
Figure 14: Reference Circuit for Normally Closed (U)SIM Card Connector .............................................. 35
Figure 15: Reference Circuit for Normally Open (U)SIM Card Connector ................................................ 35
Figure 16: Reference Circuit for a 6-Pin (U)SIM Card Connector ............................................................. 36
Figure 17: Reference Circuit of USB 3.1 & 2.0 Interface ........................................................................... 38
Figure 18: PCIe Interface Reference Circuit .............................................................................................. 40
Figure 19: PCIe Power-on Timing Requirements of M.2 Specification ..................................................... 41
Figure 20: PCIe Power-on Timing Requirements of the Module ............................................................... 41
Figure 21: Primary Mode Timing ................................................................................................................ 43
Figure 22: Auxiliary Mode Timing .............................................................................................................. 44
Figure 23: W_DISABLE1# and W_DISABLE2# Reference Circuit ........................................................... 47
Figure 24: WWAN_LED# Reference Circuit .............................................................................................. 47
Figure 25: WAKE_ON_WAN# Signal Reference Circuit ........................................................................... 48
Figure 26: Recommended Circuit of Configuration Pins ........................................................................... 51
Figure 27: RM500Q-AE&RM502Q-AE Reference Circuit of RF Antenna ................................................. 56
Figure 28: Microstrip Design on a 2-layer PCB ......................................................................................... 58
Figure 29: Coplanar Waveguide Design on a 2-layer PCB ....................................................................... 58
Figure 30: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) .................... 58
Figure 31: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) .................... 59
Figure 32: RM500Q-AE Antenna Connectors ........................................................................................... 60
Figure 33: RM502Q-AE Antenna Connectors ........................................................................................... 60
Figure 34: RM500Q-AE&RM502Q-AE RF Connector Dimensions (Unit: mm) ......................................... 63
Figure 35: Specifications of Mating Plugs Using Ø0.81 mm Coaxial Cables ............................................ 64
Figure 36: Connection between RF Connector and Mating Plug Using Ø0.81 mm Coaxial Cable .......... 64
Figure 37: Connection between RF Connector and Mating Plug Using Ø1.13 mm Coaxial Cable .......... 65
Figure 38: Thermal Dissipation Area on Bottom Side of Module .............................................................. 74
Figure 39: Mechanical Dimensions of the Module (Unit: mm) ................................................................... 76
Figure 40: RM500Q-AE Top View and Bottom view ................................................................................. 77
Figure 41: RM502Q-AE Top View and Bottom View ................................................................................. 77