Quectel QuecOpen BG952A-GL Hardware Design Download | Manualshive

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LPWA Module Series

BG952A-GL_QuecOpen_Hardware_Design

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Figure 10: Reference Circuit of RESET_N with a Driving Circuit

Another way to control the RESET_N is by using a button directly.

Figure 11: Reference Circuit of RESET_N with a Button

The reset scenario is illustrated in the following figure.

Figure 12: Reset Timing

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Summary of Contents for QuecOpen BG952A-GL

Page 1: ...BG952A GL QuecOpen Hardware Design LPWA Module Series Version 1 0 0 Date 2022 04 30 Status Preliminary www quectel com ...

Page 2: ... Disclaimer While Quectel has made efforts to ensure that the functions and features under development are free from errors it is possible that these functions and features could contain errors inaccuracies and omissions Unless otherwise provided by valid agreement Quectel makes no warranties of any kind implied or express with respect to the use of features and functions under development To the ...

Page 3: ...ment of damages All rights are reserved in the event of a patent grant or registration of a utility model or design Copyright Quectel Wireless Solutions Co Ltd 2022 All rights reserved Hereby Quectel Wireless Solutions Co Ltd declares that the radio equipment type BG952A GL is in compliance with Directive 2014 53 EU The full text of the EU declaration of conformity is available at the following in...

Page 4: ...may cause interference on sensitive medical equipment so please be aware of the restrictions on the use of wireless devices when in hospitals clinics or other healthcare facilities Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions such as when the mobile bill is unpaid or the U SIM card is invalid When emergency hel...

Page 5: ...LPWA Module Series BG952A GL_QuecOpen_Hardware_Design 4 72 metal powders ...

Page 6: ...ries BG952A GL_QuecOpen_Hardware_Design 5 72 About the Document Revision History Version Date Author Description 2022 04 30 Arvin WU Ben JIANG Creation of the document 1 0 0 2022 04 30 Arvin WU Ben JIANG Preliminary ...

Page 7: ...nt 18 3 3 Pin Description 19 3 4 Pins Multiplexing 25 3 5 Operating Modes 25 3 5 1 Recovery Mode 26 3 6 Power Saving Mode 27 3 7 Power Supply 28 3 7 1 Power Supply Pins 28 3 7 2 DVoltage Stability Requirements 28 3 7 3 Power Supply Monitoring 29 3 8 Turn on 29 3 8 1 Turn on Module with PWRKEY 29 3 8 2 Turn off Module 32 3 8 2 1 Turn off Module with PWRKEY 32 3 9 Reset the Module 33 3 10 PON_TRIG I...

Page 8: ...51 5 4 Antenna Installation 53 5 4 1 Antenna Requirements 53 5 4 2 Recommended RF Connector for Antenna Installation 53 6 Reliability Radio and Electrical Characteristics 56 6 1 Absolute Maximum Ratings 56 6 2 Power Supply Ratings 56 6 3 Operating and Storage Temperatures 57 6 4 Power Consumption 57 6 5 Tx Power 60 6 6 RF Receiving Sensitivity 60 6 7 ESD 61 7 Mechanical Dimensions 62 7 1 Mechanica...

Page 9: ... 19 Pin Definition of NET_STATUS 43 Table 20 Operating Status of NET_STATUS 44 Table 21 Pin Definition of STATUS 44 Table 22 Pin Definition of GRFC Interfaces 45 Table 23 Truth Table of GRFC Interfaces 45 Table 24 GNSS Performance 46 Table 25 Pin Definition of the Main Antenna Interface 48 Table 26 BG952A GL QuecOpen Operating Frequency 48 Table 27 Pin Definition of GNSS Antenna Interface 50 Table...

Page 10: ...LPWA Module Series BG952A GL_QuecOpen_Hardware_Design 9 72 Table 42 Terms and Abbreviations 71 ...

Page 11: ...40 Figure 18 Main UART Reference Design Transistor Circuit 41 Figure 19 Reference Design of I2C Interface with an External I2C Interface Sensor 42 Figure 20 Reference Design of NET_STATUS 44 Figure 21 Reference Design of STATUS 45 Figure 22 Reference Design of Main Antenna Interface 49 Figure 23 Reference Design of GNSS Antenna Interface 50 Figure 24 Microstrip Design on a 2 layer PCB 51 Figure 25...

Page 12: ... image update Improve cost performance ratio of products and enhance product competitiveness BG952A GL QuecOpen is based on the processor core is ARM Cortex M4 the maximum frequency is up to 80 MHz and the RAM size is 128K byte You can use this module as the basis for developing QuecOpen applications This document describing BG952A GL QuecOpen module and its air interface and hardware interfaces c...

Page 13: ...tween WWAN and GNSS Rx chains Given the relaxed latency requirements of most LPWA applications time division sharing of resources can be made largely transparent to applications For more details see document 1 BG952A GL QuecOpen is an industrial grade module for industrial and commercial applications only The following table shows the frequency bands of BG952A GL QuecOpen module Table 2 Frequency ...

Page 14: ...E Cat NB1 NB2 Rel 13 Cat M1 300 kbps DL 375 kbps UL Cat NB1 27 2 kbps DL 62 5 kbps UL Rel 14 Cat M1 588 kbps DL 1119 kbps UL Cat NB2 127 kbps DL 158 kbps UL Internet Protocol Features PPP TCP UDP SSL MQTT FTP S HTTP S LwM2M IPv4 IPv6 TLS DTLS PING CoAP NITZ protocols Supports PAP and CHAP for PPP connections SMS Text and PDU mode Point to point MO and MT SMS cell broadcast SMS storage ME by defaul...

Page 15: ... slave which can be multiplexed from GPIOs MCU SPIM0 Supports master mode only Up to 25 MHz MCU SPIM1 Supports master mode only Up to 25 MHz MCU SPIS Supports slave mode only Up to 25 MHz I2C Interface Supports 2 channels of MCU I2C interfaces GNSS GPS GLONASS AT Commands 3GPP TS 27 007 and 3GPP TS 27 005 AT commands Quectel enhanced AT commands Network Indication One NET_STATUS pin for network co...

Page 16: ...thin the extended temperature range the module remains the ability to establish and maintain functions such as SMS and data transmission without any unrecoverable malfunction Radio spectrum and radio network are not influenced while one or more specifications such as Pout may exceed the specified tolerances of 3GPP When the temperature returns to the operating temperature range the module meets 3G...

Page 17: ...n Board To facilitate application design with the module conveniently Quectel supplies the evaluation board LTE OPEN EVB a USB to RS 232 converter cable a micro USB cable an earphone antennas and other peripherals to control or test the module For more details see document 2 ...

Page 18: ...n BG952A GL QuecOpen is equipped with 102 LGA pins The subsequent chapters provide detailed descriptions of the following interfaces Power supply PON_TRIG interface U SIM interface USB interface UART interfaces PCM and I2C interfaces SPI interfaces ADC interfaces Status indication interfaces GRFC interfaces ...

Page 19: ...LPWA Module Series BG952A GL_QuecOpen_Hardware_Design 18 72 3 2 Pin Assignment The following figure shows the pin assignment of the module Figure 2 Pin Assignment Top View ...

Page 20: ...odule 5 The LNA is integrated inside the module It is not recommended to use an external LNA It is strongly recommended to keep GNSS_LNA_EN pin 51 and VDD_RF pin 99 unconnected 3 3 Pin Description The following tables show the pin definition alternate functions and GPIO pull up down resistance of the module Table 4 Definition of I O Parameters Type Description AI Analog Input AO Analog Output AIO ...

Page 21: ...00 102 Turn on off Pin Name Pin No I O Description DC Characteristics Comment PWRKEY 15 DI Turn on off the module VILmax 0 3 V VIHmin 1 0 V Internally pulled up with a 470 kΩ resistor RESET_N 17 DI Reset the module VILmax 0 3 V VIHmin 1 3 V Status Indication Interfaces Pin Name Pin No I O Description DC Characteristics Comment PSM_IND 1 DO Indicate the module s power saving mode VOLmax 0 36 V VOHm...

Page 22: ...nt USIM_DET 42 DI U SIM card hot plug detect VILmin 0 2 V VILmax 0 54 V VIHmin 1 26 V VIHmax 2 0 V 1 8 V power domain If unused keep these pins open USIM_VDD 43 PO U SIM card power supply Vmax 1 9 V Vmin 1 7 V Only 1 8 V U SIM card is supported USIM_RST 44 DO U SIM card reset VOLmax 0 36 V VOHmin 1 44 V 1 8 V power domain USIM_DATA 45 DIO U SIM card data VILmin 0 2 V VILmax 0 54 V VIHmin 1 26 V VI...

Page 23: ... Comment CLI_RXD2 94 DI CLI UART2 receive VILmin 0 2 V VILmax 0 54 V VIHmin 1 26 V VIHmax 2 0 V 1 8 V power domain It is recommended to reserve one set of test points CLI_TXD2 94 DO CLI UART2 transmit VOLmax 0 36 V VOHmin 1 44 V CLI_TXD1 27 DO CLI UART1 transmit CLI_RXD1 28 DI CLI UART1 receive VILmin 0 2 V VILmax 0 54 V VIHmin 1 26 V VIHmax 2 0 V Debug UART Interfaces Pin Name Pin No I O Descript...

Page 24: ...domain Pulled up by default When this pin is at low level the module enters airplane mode If this pin is unused keep it open Can be configured as GPIOs AP_READY 19 DI Application processor ready 1 8 V power domain If this pin is unused keep it open Can be configured as GPIOs Antenna Interfaces Pin Name Pin No I O Description DC Characteristics Comment ANT_MAIN 60 AIO Main antenna interface 50 Ω im...

Page 25: ...ut VOLmax 0 36 V VOHmin 1 44 V VILmin 0 2 V VILmax 0 54 V VIHmin 1 26 V VIHmax 2 0 V VIHmax 2 0 V 1 8 V power domain If unused keep these pins open GPIO2 5 DIO GPIO3 6 DIO GPIO4 7 DIO GPIO5 25 DIO GPIO6 26 DIO GPIO7 40 DIO GPIO8 41 DIO GPIO9 64 DIO GPIO10 65 DIO GPIO11 66 DIO GPIO12 85 DIO GPIO13 86 DIO GPIO14 87 DIO GPIO15 88 DIO GRFC Interfaces Pin Name Pin No I O Description DC Characteristics ...

Page 26: ...le 3 5 Operating Modes The operating mode of the module is combined with internal Modem Application Processor MAP mode and MCU mode Table 6 Overview of MAP Operating Modes Mode Details Normal Operation Connected The module remains registered on the network and is ready to send and receive data In this mode the software is active Idle The module is connected to the network Its current consumption v...

Page 27: ...d to a low level Power OFF Mode The module s power supply is shut down by its power management unit In this mode the software is inactive the serial interfaces are inaccessible while the operating voltage connected to VBAT_RF and VBAT_BB remains applied Power Saving Mode PSM PSM is similar to power off but the module remains registered on the network and there is no need to re attach or re establi...

Page 28: ...TS while in other modes they are GPIO pins 2 Since the baud rate of the serial port required to download firmware to the baseband chip is 3 Mbps the flow control pins of the CLI serial port need to be reserved Otherwise you can only download with a 921600 baud rate which is very slow It is recommended to reserve the test points of the CLI UART interface including pin 25 pin 26 pin 94 and pin 95 an...

Page 29: ...e should be higher than 2 2 V 3 7 2 Voltage Stability Requirements The power supply range of the module is from 2 2 V to 4 35 V Make sure that the input voltage never drops below 2 2 V Figure 3 Power Supply Limits during Burst Transmission To decrease voltage drop a bypass capacitor of about 100 µF with low ESR should be used and a multi layer ceramic chip capacitor MLCC array should also be reser...

Page 30: ...VSs with low leakage current and suitable reverse stand off voltage and also it is recommended to place them as close to the VBAT pins as possible The following figure shows the star structure of the power supply Figure 4 Star Structure of the Power Supply Power design for a module is critical to its performance The power supply of the module should be able to provide a sufficient current of at le...

Page 31: ... information on the XC6119 voltage detector With the above circuit the module automatically powers on when the power supply is switched on and keeps PWRKEY at a high level after successful power on With this design if you intend to power on the module again after you power it off with an API or AT command switch off the power supply of the module and remain in switch off state for at least 200 ms ...

Page 32: ... using a button directly When pressing the button electrostatic strike may generate from the finger Therefore a TVS component is indispensable to be placed nearby the button for ESD protection A reference circuit is shown in the following figure Figure 7 Turn on the Module with a Button The power up scenario is illustrated in the following figure ...

Page 33: ...ter the module is turned off or enters PSM do not pull up any I O pin of the module Otherwise the module will have additional power consumption and may have damaged pins 3 8 2 1 Turn off Module with PWRKEY When the module is powered on drive PWRKEY low for 650 1500 ms before you release it and then module will execute power down procedure The power down timing is illustrated in the following figur...

Page 34: ...ESET_N signal is sensitive to interference so it is recommended to route the trace as short as possible and surround it with ground Table 11 Pin Definition of RESET_N The recommended circuit is similar to the PWRKEY control circuit An open drain collector driver or button can be used to control RESET_N Pin Name Pin No I O Description RESET_N 45 DI Reset the module Internally pulled up with a 470 k...

Page 35: ... Figure 10 Reference Circuit of RESET_N with a Driving Circuit Another way to control the RESET_N is by using a button directly Figure 11 Reference Circuit of RESET_N with a Button The reset scenario is illustrated in the following figure Figure 12 Reset Timing ...

Page 36: ...Table 12 Pin Definition of PON_TRIG Interface PON_TRIG is used to wake up the internal MCU If the low power consumption mode of the MCU is not required it is strongly recommended to reserve a PON_TRIG test point A reference design is shown in the following figure Figure 13 Reference Circuit of PON_TRIG VDD_1V8 is powered by an external LDO Pin Name Pin No I O Description Comment PON_TRIG 96 DI Use...

Page 37: ... card is supported USIM_RST 44 DO U SIM card reset 1 8 V power domain USIM_DATA 45 DIO U SIM card data 1 8 V power domain USIM_CLK 46 DO U SIM card clock 1 8 V power domain USIM_GND 47 Specified ground for U SIM card The module supports U SIM card hot plug via USIM_DET and both high and low level detections are supported The function is disabled by default and see AT QSIMDET in document 3 for more...

Page 38: ...he same electric potential Make sure the bypass capacitor between USIM_VDD and USIM_GND is less than 1 μF and place it as close to U SIM card connector as possible If the system ground plane is complete USIM_GND can be connected to the system ground directly To avoid cross talk between USIM_DATA and USIM_CLK keep them away from each other and shield them with surrounded ground USIM_RST should also...

Page 39: ...AIO USB differential data For more details about USB 2 0 specification visit http www usb org home It is recommended to reserve test points for debugging and firmware upgrading in your designs Figure 16 Reference Design of USB Interface To ensure USB data signal integrity if possible reserve a 0 Ω resistor on USB_DP and USB_DM traces respectively Resistors R1 and R2 should be placed close to the m...

Page 40: ...interfaces main UART and CLI UART interfacethe The following are the features of the UART interfaces The main UART interface is used to communicate with peripherals which can be multiplexed as GPIOs The CLI UART interface supports 9600 19200 38400 57600 115200 230400 460800 921600 and 3000000 bps baud rates and the default is 115200 bps It is used for firmware upgrade software debugging log and GN...

Page 41: ...gn of the main UART interface Figure 17 Main UART Reference Design Translator Chip Visit http www ti com for more information on the translator chip Another example with transistor circuit is shown as below For the design of circuits in dotted lines refer to that of circuits in solid lines but pay attention to the direction of connection MAIN_RI 39 DO Main UART ring indication Pin Name Pin No I O ...

Page 42: ...shifting chip without internal pull up such as TXB0108PWR for voltage level translation 3 14 I2C Interface The module provides two Inter Integrated Circuit I2C interface for data communication The interface supports fast mode plus and master mode only The pins of I2C interface are open drain and are multiplexed from GPIOs The pull up resistors should be provided externally The pins of I2C interfac...

Page 43: ...nterface supports slave mode only up to 25 MHz The power domain of the SPI interface is 1 8 V A voltage level translator should be used between the module and the host if your application is equipped with a 3 3 V processor or device interface 3 16 ADC Interfaces The module provides two analog to digital converter ADC interfaces by default The other two ADC interfaces can be multiplexed from GPIOs ...

Page 44: ...e no less than 1 4 After the module is turned off or enters PSM do not pull up any pin of ADC interfaces Otherwise the module will have additional power consumption and may have damaged pins 3 17 Network Status Indication The module provides one network status indication pin NET_STATUS The pin is used to drive a network status indication LED The following tables describe the pin definition and log...

Page 45: ...vel when the module powers on Table 21 Pin Definition of STATUS The following figure shows a reference circuit of STATUS Pin Name Indicator Status Logic Level Changes Network Status NET_STATUS Flicker slowly 200 ms High 1800 ms Low Network searching Flicker slowly 1800 ms High 200 ms Low Idle Flicker quickly 125 ms High 125 ms Low Data transfer is ongoing Always High Voice calling Pin Name Pin No ...

Page 46: ...tuners Table 22 Pin Definition of GRFC Interfaces Table 23 Truth Table of GRFC Interfaces Pin Name Pin No I O Description Comment GRFC1 83 DO Generic RF controller 1 8 V power domain If unused keep these pins open GRFC2 84 DO Generic RF controller GRFC1 Level GRFC2 Level Frequency Range MHz Band Low Low 880 2200 B1 B2 B3 B4 B8 B25 B66 Low High 791 894 B5 B18 B19 B20 B26 B27 High Low 698 803 B12 B1...

Page 47: ...772A GL QuecOpen GNSS engine is switched off It has to be switched on via AT command The module does not support concurrent operation of WWAN and GNSS For more details about GNSS engine technology and configurations see document 1 4 2 GNSS Performance Table 24 GNSS Performance Parameter Description Conditions Typ Unit Sensitivity GNSS Cold start Autonomous 145 dBm Reacquisition Autonomous 153 dBm ...

Page 48: ...r executing cold start command 4 3 Layout Guidelines The following layout guidelines should be taken into account in application designs Maximize the distance between the GNSS antenna and the main antenna Digital circuits such as U SIM card USB interface camera module display connector and SD card should be kept away from the antennas Use ground vias around the GNSS trace and sensitive analog sign...

Page 49: ...Table 25 Pin Definition of the Main Antenna Interface 5 1 2 Operating Frequency Table 26 BG952A GL QuecOpen Operating Frequency Pin Name Pin No I O Description Comment ANT_MAIN 60 AIO Main antenna interface 50 Ω impedance 3GPP Band Transmit Receive Unit LTE HD FDD B1 1920 1980 2110 2170 MHz LTE HD FDD B2 1850 1910 1930 1990 MHz LTE HD FDD B3 1710 1785 1805 1880 MHz LTE HD FDD B4 1710 1755 2110 215...

Page 50: ...ot mounted by default Figure 22 Reference Design of Main Antenna Interface 4 LTE HD FDD B17 is supported in Cat NB1 Cat NB2 only 5 LTE HD FDD B26 and B27 are supported in Cat M1 only LTE HD FDD B13 777 787 746 756 MHz LTE HD FDD B17 4 704 716 734 746 MHz LTE HD FDD B18 815 830 860 875 MHz LTE HD FDD B19 830 845 875 890 MHz LTE HD FDD B20 832 862 791 821 MHz LTE HD FDD B25 1850 1915 1930 1995 MHz L...

Page 51: ...erface 50 Ω impedance 5 2 2 GNSS Operating Frequency Table 28 GNSS Operating Frequency 5 2 3 Reference Design A reference design of GNSS antenna interface is shown as below Figure 23 Reference Design of GNSS Antenna Interface The module is designed with a built in LNA and supports passive GNSS antenna only Active antenna and external LNA are not supported Type Frequency Unit GPS 1575 42 1 023 MHz ...

Page 52: ... width W the materials dielectric constant the height from the reference ground to the signal layer H and the spacing between RF traces and grounds S Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance The following are reference designs of microstrip or coplanar waveguide with different PCB structures Figure 24 Microstrip Design on a 2 layer PCB Fig...

Page 53: ...s and should be fully connected to ground The distance between the RF pins and the RF connector should be as short as possible and all the right angle traces should be changed to curved ones The recommended trace angle is 135 There should be clearance under the signal pin of the antenna connector or solder joint The reference ground of RF traces should be complete Meanwhile adding some ground vias...

Page 54: ...nded RF Connector for Antenna Installation If RF connector is used for antenna connection it is recommended to use U FL R SMT connectors provided by HIROSE Antenna Type Requirements GNSS Frequency range 1559 1609 MHz Polarization RHCP or linear VSWR 2 Typ Passive antenna gain 0 dBi LTE VSWR 2 Efficiency 30 Max Input Power 50 W Input Impedance 50 Ω Cable Insertion Loss 1 dB LB 1 GHz 1 5 dB MB 1 2 3...

Page 55: ...he U FL R SMT Connector Unit mm U FL LP serial connectors listed in the following figure can be used to match the U FL R SMT Figure 29 Mechanicals of U FL LP Connectors The following figure describes the space factor of mated connectors Figure 30 Space Factor of Mated Connectors Unit mm ...

Page 56: ...LPWA Module Series BG952A GL_QuecOpen_Hardware_Design 55 72 For more details visit http www hirose com ...

Page 57: ...olute Maximum Ratings 6 2 Power Supply Ratings Table 31 Power Supply Ratings Parameter Min Max Unit VBAT_BB 0 2 4 5 V VBAT_RF 0 2 4 5 V USB_VBUS 1 19 2 0 V Voltage at Digital Pins 0 3 2 0 V Parameter Description Conditions Min Typ Max Unit VBAT_BB Power supply for the module s baseband part The actual input voltages must be kept between the minimum and the maximum values BG95 MF 2 2 3 3 4 35 V VBA...

Page 58: ...tions such as SMS and data transmission without any unrecoverable malfunction Radio spectrum and radio network are not influenced while one or more specifications such as Pout may exceed the specified tolerances of 3GPP When the temperature returns to the operating temperature range the module meets 3GPP specifications again 6 4 Power Consumption Table 33 Power Consumption Power Supply 3 3 V Room ...

Page 59: ...s DRX 1 28 s TBD mA LTE Cat M1 data transfer GNSS OFF LTE HD FDD B1 22 8 dBm TBD mA LTE HD FDD B2 23 37 dBm TBD mA LTE HD FDD B3 23 22 dBm TBD mA LTE HD FDD B4 23 25 dBm TBD mA LTE HD FDD B5 23 32 dBm TBD mA LTE HD FDD B8 23 56 dBm TBD mA LTE HD FDD B12 23 49 dBm TBD mA LTE HD FDD B13 23 16 dBm TBD mA LTE HD FDD B18 23 24 dBm TBD mA LTE HD FDD B19 23 34 dBm TBD mA LTE HD FDD B20 23 37 dBm TBD mA L...

Page 60: ...Passive antenna TBD mA LTE HD FDD B66 23 19 dBm TBD mA LTE Cat NB1 data transfer GNSS OFF LTE HD FDD B1 22 7 dBm TBD mA LTE HD FDD B2 22 72 dBm TBD mA LTE HD FDD B3 23 24 dBm TBD mA LTE HD FDD B4 23 19 dBm TBD mA LTE HD FDD B5 23 32 dBm TBD mA LTE HD FDD B8 22 71 dBm TBD mA LTE HD FDD B12 22 8 dBm TBD mA LTE HD FDD B13 23 23 dBm TBD mA LTE HD FDD B17 22 73 dBm TBD mA LTE HD FDD B18 23 28 dBm TBD m...

Page 61: ... Power Min Tx Power LTE HD FDD B1 B2 B3 B4 B5 B8 B12 B13 B17 6 B18 B19 B20 B25 B26 7 B27 7 B28 B66 23 dBm 2 7 dB 39 dBm Frequency Band Primary Diversity Receiving Sensitivity dBm Cat M1 3GPP Cat NB18 3GPP LTE HD FDD B1 Supported 106 6 102 3 115 3 107 5 LTE HD FDD B2 106 2 100 3 114 3 107 5 LTE HD FDD B3 106 2 99 3 114 107 5 LTE HD FDD B4 106 6 102 3 114 107 5 LTE HD FDD B5 106 8 100 8 115 107 5 LT...

Page 62: ...otective components to the ESD sensitive interfaces and points in the product design Table 37 Electrostatic Discharge Characteristics 25 ºC 45 Relative Humidity Tested Interfaces Contact Discharge Air Discharge Unit VBAT GND TBD TBD kV Main GNSS Antenna Interfaces TBD TBD kV 9 LTE HD FDD B26 and B27 are supported in Cat M1 only LTE HD FDD B19 107 102 3 115 3 107 5 LTE HD FDD B20 106 6 99 8 114 6 1...

Page 63: ...echanical Dimensions This chapter describes the mechanical dimensions of the module All dimensions are measured in millimeter mm and the dimensional tolerances are 0 05 mm unless otherwise specified 7 1 Mechanical Dimensions Figure 31 Module Top and Side Dimensions ...

Page 64: ...10 1 00 8 50 0 85 1 70 1 00 1 00 1 70 1 70 0 55 1 90 1 10 0 50 0 70 0 25 0 25 0 25 19 90 0 20 23 60 0 20 40x1 0 40x1 0 62x0 7 62x1 10 1 00 1 00 1 10 0 25 Figure 32 Bottom Dimensions Bottom View The package warpage level of the module conforms to the JEITA ED 7306 standard Pin 1 NOTE ...

Page 65: ... 70 5 95 5 95 4 25 4 25 7 65 7 65 9 70 9 60 1 70 0 85 2 55 4 25 5 95 4 25 5 95 1 70 1 70 2 50 2 50 1 10 1 10 1 10 1 10 1 10 0 70 1 00 1 00 0 25 0 25 0 25 0 20 0 15 Figure 33 Recommended Footprint Top View 1 Keep at least 3 mm between the module and other components on the motherboard to improve soldering quality and maintenance convenience 2 All reserved pins must be kept open 3 For stencil design...

Page 66: ...re_Design 65 72 7 3 Top and Bottom Views Figure 34 Top and Bottom Views Images above are for illustration purpose only and may differ from the actual module For authentic appearance and label please refer to the module received from Quectel NOTE ...

Page 67: ...must be processed in reflow soldering or other high temperature operations within 168 hours Otherwise the module should be stored in an environment where the relative humidity is less than 10 e g a drying cabinet 4 The module should be pre baked to avoid blistering cracks and inner layer separation in PCB under the following circumstances The module is not stored in Recommended Storage Condition V...

Page 68: ...for the baking procedure 8 2 Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil thus making the paste fill the stencil openings and then penetrate to the PCB The force on the squeegee should be adjusted properly to produce a clean stencil surface on a single pass To ensure the module soldering quality the thickness of stencil for the module is recomme...

Page 69: ... the SMT process complexity please contact Quectel Technical Support in advance regarding any situation that you are not sure about or any process e g selective soldering ultrasonic soldering that is not mentioned in document 6 8 3 Packaging The module is delivered in a tape carrier packaging and details are as follows 8 3 1 Carrier Tape Dimension details Factor Recommendation Soak Zone Max slope ...

Page 70: ...igure 36 Carrier Tape Dimension Drawing Table 39 Carrier Tape Dimension Table Unit mm 8 3 2 Plastic Reel Figure 37 Plastic Reel Dimension Drawing Table 40 Plastic Reel Dimension Table Unit mm W P T A0 B0 K0 K1 F E 44 32 0 35 20 2 24 3 15 6 65 20 2 1 75 øD1 øD2 W ...

Page 71: ... them then wind the heat sealed carrier tape on the plastic reel and use the protective tape for protection One plastic reel can load 250 modules Place the packaged plastic reel humidity indicator card and desiccant bag inside a vacuum bag then vacuumize it Place the vacuum packed plastic reel inside a pizza box Place 4 pizza boxes inside 1 carton and seal it One carton can pack 1000 modules ...

Page 72: ...pgrade Over The Air DL Downlink e I DRX Extended Idle Mode Discontinuous Reception EDGE Enhanced Data Rates for GSM Evolution SN Document Name 1 Quectel_BG770A GL BG95xA GL_GNSS_Application_Note 2 Quectel_LTE_OPEN_EVB_User_Guide 3 Quectel_BG77xA GL BG95xA GL_AT_Commands_Manual 4 Quectel_BG77xA GL BG95xA GL_QCFG_AT_Commands_Manual 5 Quectel_RF_Layout_Application_Note 6 Quectel_Module_Secondary_SMT_...

Page 73: ... Communications HSS Home Subscriber Server I2C Inter Integrated Circuit LED Light Emitting Diode LNA Low Noise Amplifier LTE Long Term Evolution MO Mobile Originated MS Mobile Station MSL Moisture Sensitivity Level MT Mobile Terminated PA Power Amplifier PAP Password Authentication Protocol PCB Printed Circuit Board PDU Protocol Data Unit PPP Point to Point Protocol PSM Power Saving Mode RF Radio ...

Page 74: ...odule Vmax Maximum Voltage Value Vnom Nominal Voltage Value Vmin Minimum Voltage Value VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VOHmin Minimum Output High Level Voltage Value VOLmax Maximum Output Low Level Voltage Value VSWR Voltage Standing Wave Ratio WWAN ...

Page 75: ...his device is a mobile device And the following conditions must be met 1 This Modular Approval is limited to OEM installation for mobile and fixed applications only The antenna installation and operating configurations of this transmitter including any applicable source based time averaging duty factor antenna gain and cable loss must satisfy MPE categorical Exclusion Requirements of 2 1091 2 The ...

Page 76: ...tions of finished products Please refer to KDB784748 D01 v07 section 8 Page 6 7 last two paragraphs A certified modular has the option to use a permanently affixed label or an electronic label For a permanently affixed label the module must be labeled with an FCC ID Section 2 926 see 2 2 Certification labeling requirements above The OEM manual must provide clear instructions explaining to the OEM ...

Page 77: ... two conditions 1 This device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation Changes or modifications not expressly approved by the manufacturer could void the user s authority to operate the equipment IC Statement IRSS GEN This device complies with Industry Canada s licence exempt RSSs Operation ...

Page 78: ... 11 000dBi Catm LTE Band4 66 8 000dBi Catm LTE Band5 26 12 541dBi Catm LTE Band12 11 798dBi Catm LTE Band13 12 214dBi Catm LTE Band85 11 798dBi NB LTE Band2 25 11 000dBi NB LTE Band4 66 8 000dBi NB LTE Band5 12 541 dBi NB LTE Band12 11 798dBi NB LTE Band13 12 214dBi The host product shall be properly labelled to identify the modules within the host product The Innovation Science and Economic Devel...

Page 79: ...ion Sciences et Développement économique Canada d un module doit être clairement visible en tout temps lorsqu il est installédans le produit hôte sinon le produit hôte doit porter une étiquette indiquant le numéro de certification d Innovation Sciences et Développement économique Canada pour le module précédé du mot Contient ou d un libellé semblable exprimant la même signification comme suit Cont...

Page 80: ...LPWA Module Series BG952A GL_QuecOpen_Hardware_Design 79 72 ...

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