Quectel MC60, Hardware Design

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GSM/GPRS/GNSS Module Series
MC60 Series Hardware Design
MC60_Series_Hardware_Design Confidential / Released 8 / 114
Figure Index
FIGURE 1: MODULE FUNCTIONAL DIAGRAM ............................................................................................... 17
FIGURE 2: PIN ASSIGNMENT ......................................................................................................................... 19
FIGURE 3: ALL-IN-ONE SOLUTION SCHEMATIC DIAGRAM ......................................................................... 26
FIGURE 4: STAND-ALONE SOLUTION SCHEMATIC DIAGRAM ................................................................... 26
FIGURE 5: VOLTAGE RIPPLE DURING TRANSMITTING (GSM PART) ........................................................ 28
FIGURE 6: REFERENCE CIRCUIT FOR THE VBAT INPUT (GSM PART) ..................................................... 29
FIGURE 7: REFERENCE CIRCUIT FOR THE GNSS_VCC INPUT ................................................................. 29
FIGURE 8: REFERENCE CIRCUIT FOR POWER SUPPLY OF THE GSM PART .......................................... 30
FIGURE 9: REFERENCE CIRCUIT DESIGN FOR GNSS PART IN ALL-IN-ONE SOLUTION ........................ 31
FIGURE 10: REFERENCE CIRCUIT DESIGN FOR GNSS PART IN STAND-ALONE SOLUTION ................ 32
FIGURE 11: INTERNAL
GNSS’S BACKUP DOMAIN POWER CONSTRUCTION .......................................... 33
FIGURE 12: VRTC IS POWERED BY A RECHARGEABLE BATTERY ........................................................... 33
FIGURE 13: VRTC IS POWERED BY A CAPACITOR ...................................................................................... 34
FIGURE 14: OPERATION MECHANISM OF PERIODIC MODE ...................................................................... 40
FIGURE 15: POWER CONSUMPTION IN DIFFERENT SCENARIOS (ALWAYSLOCATE
TM
MODE) ............. 41
FIGURE 16: TURN ON THE MODULE WITH AN OPEN-COLLECTOR DRIVER ............................................ 44
FIGURE 17: TURN ON THE MODULE WITH A BUTTON ................................................................................ 45
FIGURE 18: TURN-ON TIMING ........................................................................................................................ 46
FIGURE 19: TURN-OFF TIMING BY USING THE PWRKEY PIN .................................................................... 47
FIGURE 20: TURN-OFF TIMING OF GNSS PART BY USING AT COMMAND ............................................... 48
FIGURE 21: TURN-ON TIMING OF GSM PART .............................................................................................. 50
FIGURE 22: TURN-OFF TIMING OF GSM PART BY USING THE PWRKEY PIN .......................................... 52
FIGURE 23: REFERENCE DESIGN FOR FULL-FUNCTION UART ................................................................ 56
FIGURE 24: REFERENCE DESIGN FOR UART PORT (THREE LINE CONNECTION)................................. 57
FIGURE 25: REFERENCE DESIGN FOR UART PORT WITH HARDWARE FLOW CONTROL .................... 57
FIGURE 26: REFERENCE DESIGN FOR FIRMWARE UPGRADE ................................................................. 58
FIGURE 27: REFERENCE DESIGN FOR DEBUG PORT ............................................................................... 58
FIGURE 28: AUXILIARY AND GNSS UART PORT CONNECTION IN ALL-IN-ONE SOLUTION .................... 59
FIGURE 29: AUXILIARY AND GNSS UART PORT CONNECTION IN STAND-ALONE SOLUTION .............. 60
FIGURE 30: LEVEL MATCH DESIGN FOR 3.3V SYSTEM.............................................................................. 60
FIGURE 31: SKETCH MAP FOR RS-232 INTERFACE MATCH ...................................................................... 61
FIGURE 32: REFERENCE DESIGN FOR AIN ................................................................................................. 63
FIGURE 33: HANDSET INTERFACE DESIGN FOR AOUT1 ........................................................................... 64
FIGURE 34: SPEAKER INTERFACE DESIGN WITH AN AMPLIFIER FOR AOUT1 ....................................... 64
FIGURE 35: EARPHONE INTERFACE DESIGN .............................................................................................. 65
FIGURE 36: LOUD SPEAKER INTERFACE DESIGN ...................................................................................... 65
FIGURE 37: TIMING DIAGRAM FOR LONG FRAME SYNCHRONIZATION .................................................. 68
FIGURE 38: TIMING DIAGRAM FOR SHORT FRAME SYNCHRONIZATION ................................................ 68
FIGURE 39: REFERENCE DESIGN FOR PCM ............................................................................................... 69
FIGURE 40: REFERENCE CIRCUIT FOR (U)SIM1 CARD INTERFACE WITH AN 8-PIN (U)SIM CARD
CONNECTOR .................................................................................................................................................... 71
Quectel
Confidential