M50 Hardware Design
M50_HD_V2.0
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Module (DCE)
Host (DTE)
Controller
TXD
RXD
GND
TXD_AUX
RXD_AUX
GND
Figure 23: Reference design for Auxiliary UART port
3.9.4. UART application
The reference design of 3.3V level match is shown as below. If the host is a 3V system, please
change the 5.6K resistor to 15K.
MCU/ARM
/TXD
/RXD
1K
TXD
RXD
RTS
CTS
DTR
RI
/RTS
/CTS
GPIO
EINT
GPIO
DCD
Module
1K
1K
Voltage level:3.3V
5.6K
5.6K
5.6K
1K
1K
1K
1K
GND
GND
Figure 24
: Level match design for 3.3V system
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