M50 Hardware Design
M50_HD_V2.0
- 20 -
3.1. Pin of module
3.1.1. Pin assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Top view
75
76
77
78
79
80
81
82
83
SIM_PRESENCE
RESERVED
VRTC
VDD_EXT
GND
GND
RF_ANT
GND
GND
GND
VBAT
VBAT
VBAT
VBAT
RESERVED
RESERVED
RESERVED
RESERVED
ADC1
ADC0
RESERVED
NETLIGHT
SPK2P
AGND
MIC2P
MIC2N
MIC1P
MIC1N
SPK1N
SPK1P
LOUDSPKN
LOUDSPKP
STATUS
PWRKEY
EMERG_OFF
PCM_IN
PCM_CLK
RESERVED
RESERVED
TXD_AUX
RXD_AUX
DBG_TXD
DBG_RXD
RESERVED
DCD
RI
DTR
CTS
RTS
RXD
TXD
SIM1_GND
SIM1_RST
SIM1_CLK
SIM1_DATA
SIM1_VDD
VBAT
GND
PCM
RF
UART
Power
SIM
Reserved
Audio
ADC
Other
SD
PCM_OUT
PCM_SYNC
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
SD_CMD
SD_CLK
SD_DATA0
GND
RESERVED
RESERVED
RESERVED
RESERVED
GND
GND
GND
GND
Figure 2: Pin assignment
Quecctel
Confidential