LPWA Module Series
BG770A-GL Hardware Design
BG770A-GL_Hardware_Design 30 / 75
The following figure shows the connection between the module and the host.
Figure 3: Sleep Mode Application via UART
When BG770A-GL has a URC to report, MAIN_RI signal will wake up the host. See
Chapter 3.14
for
details about MAIN_RI behavior.
Driving the MAIN_DTR low will wake up the module.
AP_READY* will detect the sleep state of the host (can be configured to high voltage level or low
voltage level detection). See
AT+QCFG="apready"
in
document [3]
for details.
3.5. Power Supply
3.5.1. Power Supply Pins
BG770A-GL provides VBAT_BB and VBAT_RF two pins for connection with an external power supply.
The following table shows the details of VBAT_BB and VBAT_RF pins and ground pins.
Table 7: VBAT and GND Pins
Pin Name
Pin No.
Description
Min.
Typ.
Max.
Unit
VBAT_BB
1)
19
Power supply for the
module’s baseband part
2.2
3.3
4.35
V
VBAT_RF
1)
20
Power supply for the
module’s RF part
3.1
3.3
4.2
V
GND
22–25, 27, 28, 30, 31, 47, 52–56, 58, 66, 73–75,
84–86, 88, 89
-
-
-
-
