LTE-A Module Series
EM12-G Hardware Design
EM12-G_Hardware_Design 36 / 62
PCM_SYNC
28
IO
PCM data frame
synchronization signal
1.8V power domain.
PCM_CLK
20
IO
PCM data bit clock
1.8V power domain.
In master mode, it is an output
signal. In slave mode, it is an
input signal.
If unused, keep it open.
I2C_SCL
58
DO
I2C serial clock
Used for external codec.
Require an external pull-up to
1.8V.
I2C_SDA
56
IO
I2C serial data
The clock and mode can be configured by AT command, and the default configuration is master mode
using short frame synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC. Please refer to
document [2]
for details about
AT+QDAI
command.
The following figure shows a reference design of PCM interface with an external codec IC.
PCM_IN
PCM_OUT
PCM_SYNC
PCM_CLK
I2C_SCL
I2C_SDA
Module
1.8V
4
.7
K
BCLK
LRCK
DAC
ADC
SCL
SDA
B
IA
S
MICBIAS
INP
INN
LOUTP
LOUTN
Codec
4
.7
K
Figure 19: Reference Circuit of PCM Application with Audio Codec
1. It is recommended to reserve an RC (R=22
Ω, C=22pF) circuit on the PCM lines, especially for
PCM_CLK.
2. EM12-G works as a master device pertaining to I2C interface.
3.10. Control and Indicator Signals
The following table shows the pin definition of control and indicator signals.
NOTES