LTE Module Series
EC21 Hardware Design
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SGMII_MDATA
EPHY_INT_N
MDIO
RSTN
MDC
R1
R2
10K
VDD_EXT
Module
AR8033
1.5K
USIM2_VDD
EPHY_RST_N
INT
SGMII_MCLK
C1
C2
C3
C4
SGMII_TX_M
SGMII_TX_P
SGMII_RX_P
SGMII_RX_M
SIP
SIN
SOP
SON
Close to Module
Close to AR8033
Control
SGMII Data
0.1uF
0.1uF
0.1uF
0.1uF
USIM2_VDD
USIM2_VDD
Figure 28: Reference Circuit of SGMII Interface with PHY AR8033 Application
In order to enhance the reliability and availability in your application, please follow the criteria below in the
Ethernet PHY circuit design:
Keep SGMII data and control signals away from RF and VBAT trace.
Keep the maximum trace length less than 10inch and keep skew on the differential pairs less than
20mil.
The differential impedance of SGMII data trace is 100ohm±10%.
To minimize crosstalk, the distance between separate adjacent pairs that are on the same layer must
be equal to or larger than 40mil.
For more information about SGMII application, please refer to
document [5]
and
document [7]
.
NOTE
Quectel
Confidential
