LTE Standard Module Series
EC200T Series Hardware Design
EC200T_Series_Hardware_Design 34 / 90
Figure 6: Power Supply Limits during Burst Transmission
To decrease voltage drop, a bypass capacitor of about 100 µF with low ESR (ESR = 0.7
Ω
) should be
used, and a multi-layer ceramic chip (MLCC) capacitor array should also be reserved due to its ultra-low
ESR. It is recommended to use three ceramic capacitors (100 nF, 33 pF, 10 pF) for composing the MLCC
array, and place these capacitors close to the VBAT_BB and VBAT_RF pins. The main power supply from
an external application has to be a single voltage source and can be expanded to two sub paths with star
structure. The width of VBAT_BB trace should be no less than 1mm; and the width of VBAT_RF trace
should be no less than 2 mm. In principle, the longer the VBAT trace is, the wider it will be.
In addition, in order to ensure the stability of power source, it is suggested that a TVS diode of which
reverse stand-off voltage is 4.7 V and peak pulse power is up to 2550 W should be used. The following
figure shows the star structure of the power supply.
Figure 7: Star Structure of Power Supply
3.6.3. Reference Design for Power Supply
Power design for the module is very important, as the performance of the module largely depends on the
power source. The power supply should be able to provide sufficient current up to 2.0 A at least to the
module. If the voltage drop between the input and output is not too high, it is suggested that an LDO
should be used to supply power for the module. If there is a big voltage difference between the input
source and the desired output (VBAT), a buck converter is preferred to be used as the power supply.
