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PROJECT

TITLE

Radom.XIANG

CHECKED BY

Mountain.ZHOU

DRAWN BY

OF

A

6

5

4

3

2

1

SHEET

A

B

C

D

1

2

3

4

5

6

D

C

B

Quectel Wireless Solutions

SIZE

VER

8

3

1.0

DATE

2015/3/30

EC20 Reference Design

A2

e.g. 5V

LDO Application

It is used when the input voltage is below 7V.

VBAT = (R302/R303+1)*1.24 = 3.88V

DC-DC Application

It is used when the input voltage is above 7V. Use DC-DC to convert high input

e.g. DC12V IN

DC-DC DC 5V out

LDO

DC 3.8V out for module

voltage to 5V, and LDO will generate 3.8V typical voltage for the module.

VDD_3.0V = (R305/R306+1)*1.207 = 3.0V

Supply Power for PCM Codec and SD Card

Close to the module VBAT pins

Note:

VBAT should be routed in star mode to VBAT_BB and VBAT_RF pins.

Power Supply Design

VBAT Design

Connect to VBAT_BB pins

Connect to VBAT_RF pins

Power Design

+

C303

470uF

1

EN

2

IN

3

GND

4

OUT

5

ADJ

U301 MIC29302WU

C304

100nF

C302

100nF

+

C301

470uF

R302

100K
1%

R303
47K

1%

1

IN

3

EN

5

OUT

4

BP

2

GND

U302

SGM2019-ADJ

C316

4.7uF

R305
63.4K

1%

R306
42.2K
1%

C317

100nF

R304

51K

C314

1uF

C315

100nF

+

C305

100uF

D301

PZ3D4V2H

R301

51K

C306

100nF

C307

33pF

C308

10pF

C310

100nF

C311

33pF

C312

10pF

+

C309

100uF

R307
470R

D302

TVS

Q301

DTC043ZEBTL

DC_IN

VBAT

VDD_3.0V

VBAT

[1,3,8]

VBAT

[1,3,8]

VBAT

VBAT

[2] VBAT_EN

Quectel 

Confidential

Summary of Contents for EC20

Page 1: ...9 RESERVED 40 RESERVED 41 I2C_SCL 42 I2C_SDA 43 RESERVED 44 ADC1 45 ADC0 46 GND 47 ANT_GNSS 48 GND 49 ANT_MAIN 50 GND 51 GND 52 GND 53 GND 54 GND 55 RESERVED 56 GND 57 VBAT_RF 58 VBAT_RF 59 VBAT_BB 60...

Page 2: ...ware_Design and Quectel_EC20_AT_Commands_Manual AP_READY High level detection AP_READY Low level detection 4 Transistor circuits Q203 Q207 are used for level translation The necessary control circuit...

Page 3: ..._3 0V R305 R306 1 1 207 3 0V Supply Power for PCM Codec and SD Card Close to the module VBAT pins Note VBAT should be routed in star mode to VBAT_BB and VBAT_RF pins Power Supply Design VBAT Design Co...

Page 4: ...ith RTS interface and the RI and DCD transistor circuit is similar with CTS interface C401 100nF 1 2 3 4 5 6 U401 ESDA6V8AV6 C403 33pF C404 33pF C402 33pF R401 22R R402 22R R403 22R R404 15K GND VPP I...

Page 5: ...T1 23 LRCK1 26 SCL 27 SDA 28 GPIO1 IRQ1 29 DBVDD 30 DCVDD 31 MICVDD 32 MICBIAS1 8 VREF2 24 BCLK1 1 JD1 9 LOUTL P 17 HPO_R 25 MCLK 33 DGND U501 ALC5616 C505 4 7uF C504 4 7uF C503 100nF R501 0R C502 4 7...

Page 6: ...ose an external LDO according to the active antenna to supply power VDD left Notes GNSS Antenna Circuit 2 If you design the antenna circuit with passive antenna the R603 and L603 are not needed Active...

Page 7: ...ore than 2x line width 5 The parasitic capacitance of ESD components should be smaller than 15pF SD Design C702 33pF C701 0 1uF R702 33R R703 0R R705 0R R706 0R R707 0R R713 120K D707 ESD9X3 3ST5G R71...

Page 8: ...put Reserved Test Points Notes 1 Both USB and debug UART interface are reserved for software debug 3 Keep USB test points as close as possible to USB pins Other Design 2 USB interface can be used to u...

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