LPWA Module Series
BG96 Hardware Design
BG96_Hardware_Design 17 / 79
3.1. Pin Assignment
The following figure shows the pin assignment of BG96.
PSM_IND
PCM_SYNC
PCM_CLK
PCM_IN
PCM_OUT
RESERVED
RESERVED
PWRKEY
1)
RESERVED
RESET_N
W_DISABLE#
1
2
3
4
5
6
7
11
12
13
14
15
16
17
50
51
52
53
54
55
58
59
60
61
62
USB_DM
AP
_
R
E
A
D
Y
S
T
A
T
U
S
N
E
T
L
IG
H
T
DB
G
_
R
X
D
D
B
G
_
T
X
D
A
DC
0
R
E
S
E
R
V
E
D
G
P
IO
26
U
A
R
T
3
_
T
X
D
U
A
R
T
3
_
R
X
D
V
D
D
_
E
X
T
D
T
R
G
N
D
USIM_CLK
USIM_DATA
USIM_RST
USIM_VDD
RI
DCD
CTS
TXD
RXD
VBAT_BB
VBAT_BB
USIM_GND
GND
R
E
S
E
R
V
E
D
31
30
29
28
27
26
23
22
21
20
19
10
9
USB_DP
USB_VBUS
ADC1
GND
RESERVED
RESERVED
RTS
I2C_SCL
I2C_SDA
8
49
48
47
46
45
44
43
40
41
42
39
38
37
36
35
34
33
32
24
57
56
G
N
D
G
N
D
A
N
T
_
M
A
IN
G
N
D
G
N
D
V
B
A
T
_
RF
V
B
A
T
_
RF
G
N
D
G
N
D
ANT_GNSS
R
E
S
E
R
V
E
D
G
N
D
USIM_PRESENCE
63
64
65
66
67
68
83
84
85
86
87
88
98
97
96
95
94
93
78
77
76
75
74
73
91
92
89
90
71
72
69
70
80
79
82
81
100
99
102
101
POWER
USB
UART
(U)SIM
OTHERS
GND
RESERVED
PCM
ANT
25
RE
S
E
RV
E
D
USB_BOOT
18
GPIO64
Figure 2: Pin Assignment (Top View)
