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and receive clocks. These clocks can be programmed in WR11 to come from the RTXC pin, the
TRXC pin, the output of the BRG, or the transmit output of the DPLL. Programming of the
clocks should be done before enabling the receiver, transmitter, BRG, or DPLL.

Table 11

SCC write register description.

External/Status interrupt control

WR15

Miscellaneous control bits: baud rate generator, DPLL control, auto
echo

WR14

Lower byte of baud rate time constant

WR13

Lower byte of baud rate time constant

WR12

Clock mode and source control

WR11

Miscellaneous transmitter/receiver control bits, NRZI, NRZ, FM
coding, CRC reset

WR10

Master interrupt control and reset

WR9

Transmit buffer

WR8

Special HDLC Enhancement Register

WR7'

Sync character (2nd byte) or SDLC Flag

WR7

Sync character (1st byte) or SDLC address field

WR6

Transmitter initialization and control

WR5

Transmit/Receive miscellaneous parameters and codes, clock rate,
stop bits, parity

WR4

Receiver initialization and control

WR3

Interrupt vector

WR2

Interrupt control, Wait/DMA request control

WR1

Command Register, Register Pointer, CRC initialization, resets for
various modes

WR0

For more information regarding the SCC registers please refer to the manufacturer's

technical manual for the specific part being used.

MPA-100 User's Manual

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Summary of Contents for MPA-100

Page 1: ... 100 RS 232 SYNCHRONOUS ADAPTER CARD User s Manual QUATECH INC TEL 330 665 9000 5675 Hudson Industrial Parkway FAX 330 665 9010 Hudson Ohio 44236 http www quatech com INTERFACE CARDS FOR IBM PC AT AND PS 2 ...

Page 2: ......

Page 3: ... will Quatech Inc be liable for damages of any kind incidental or consequential in regard to or arising out of the performance or form of the materials presented herein and in the program s accompanying this document No representation is made regarding the suitability of this product for any particular purpose Quatech Inc reserves the right to edit or append to this document or the product s to wh...

Page 4: ...eteness In no event will Quatech Inc be liable for damages of any kind incidental or consequential in regard to or arising out of the performance or form of the materials presented in this document or any software programs that might accompany this document Quatech Inc encourages feedback about this document Please send any written comments to the Technical Support department at the address listed...

Page 5: ...ds 6 5 6 2 Baud Rate Generator Programming 6 2 6 1 Accessing the Registers 6 1 6 SCC GENERAL INFORMATION 6 4 5 6 SYNCA to RLEN Control J7 5 3 5 5 Receive DMA Selection J9 5 3 5 4 Transmit DMA Selection J8 5 2 5 3 Interrupt Level Selection J5 J6 5 1 5 2 Interrupt Sharing Configuration J4 5 1 5 1 DTE DCE Configuration J2 J11 J12 5 1 5 JUMPER CONFIGURATIONS 4 2 4 1 Using Terminal Count to Generate In...

Page 6: ...MPA 100 User s Manual iv ...

Page 7: ...ocated anywhere within the available I O address space in the system Communication on the MPA 100 is controlled by a serial communications controller hereafter referred to as the SCC U17 The MPA 100 is compatible with several different types of SCC all of which can support asynchronous formats byte oriented protocols such as IBM Bisync and bit oriented protocols such as HDLC and SDLC The SCCs also...

Page 8: ...MPA 100 User s Manual 1 2 ...

Page 9: ... 4 and 7 for detailed information on how to set the address IRQ and DMA levels 2 Turn off the power of the computer system in which the MPA 100 is to be installed 3 Remove the system cover according to the instructions provided by the computer manufacturer 4 Install the MPA 100 in any vacant expansion slot The board should be secured by installing the Option Retaining Bracket ORB screw 5 Replace t...

Page 10: ...MPA 100 User s Manual 2 2 ...

Page 11: ...W2 SW1 allows the user to select the higher address signals A15 A8 SW2 allows the user to select the lower address signals A7 A3 The sixth position of SW2 is not used and can be ignored Figure 2 shows some examples of different base addresses Figure 2 Address switch selection examples ON ON ON O N 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 1 1 2 2 3 3 4 4 5 5 6 6 Base Address 300H Base Address 3F8H SW1 SW2 S...

Page 12: ...ed Base 7 Reserved Base 6 Configuration Register Base 5 Communications Register Base 4 SCC Control Port Channel B Base 3 SCC Data Port Channel B Base 2 SCC Control Port Channel A Base 1 SCC Data Port Channel A Base 0 Register Description Address Information on the internal registers of the SCC can be found in Section 6 The two onboard registers give the user additional options pertaining to DMA in...

Page 13: ...things that an ISR must do to allow proper system operation 1 Do a software interrupt acknowledge to the SCC This is accomplished by reading the interrupt vector register read register 2 in channel B of the SCC The value supplied by this read can also be used to vector to the appropriate part of the ISR 2 Service the interrupt read the receiver buffer write to the transmit buffer etc 3 Write a Res...

Page 14: ...l Count TC signal is asserted Terminal Count is an indicator generated by the system s DMA controller which signals that the number of transfers programed into the DMA controller s transfer register have occurred This board feature only works when theinterrupt sharing feature is selected on jumper J4 MPA 100 User s Manual 4 2 ...

Page 15: ... 9 10 11 12 13 14 15 16 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 16 J11 no connection 1 2 J2 DCE DTE Default J11 and J12 may be configured for DTE by setting all jumpers vertical on the board and for DCE by setting all jumpers horizontal on the board 5 2 Interrupt Sharing Configuration J4 J4 is a three pin jumper which determines the configuration for the interrupts By selecting pins 1 2 the user has t...

Page 16: ...n J6 Table 5 and Table 6 summarize the jumper block selections for J5 and J6 The IRQ levels are also marked on the MPA 100 silkscreen for easy identification Table 5 Jumper block J5 selections 6 12 IRQ7 5 11 IRQ6 4 10 IRQ5 Default 3 9 IRQ4 2 8 IRQ3 1 7 IRQ2 9 Pins Interrupt Level Table 6 Jumper block J6 selections 5 10 IRQ15 4 9 IRQ14 3 8 IRQ12 2 7 IRQ11 1 6 IRQ10 Pins Interrupt Level MPA 100 User...

Page 17: ...ctions 6 12 5 11 Channel 3 Default 4 10 3 9 Channel 2 2 8 1 7 Channel 1 Pins DMA Channel 5 5 Receive DMA Selection J9 J9 selects the DMA channel to be used for Receive DMA Three channels 1 3 are available on the MPA 100 for DMA When selecting a DMA channel both the DMA acknowledge DACK and the DMA request DRQ for the appropriate channel need to be selected Table 8 summarizes the jumper block selec...

Page 18: ...N Control J7 J7 controls the signal path from the RLEN bit in the Communications Register to the SYNCA input to the SCC If J7 is installed and the SCC is in external SYNC mode setting the RLEN bit high will assert the SYNCA pin Note the RLEN output is still affected when used to control the SYNCA pin Table 9 Jumper J7 Selections no connections RLEN Default 1 2 SYNCA Jumper J1 Function MPA 100 User...

Page 19: ...acter 1 1 1 2 or 2 stop bits Odd even or no parity Times 1 16 32 or 64 x clock modes Break generation and detection Parity overrun and framing error detection 2 Byte oriented Synchronous Communications Internal external character synchronization 1 or 2 sync characters in separate registers Automatic Cyclic Redundancy Check CRC generation detection 3 SDLC HDLC Bit Synchronous Communications Abort s...

Page 20: ...t the operation and address for the appropriate channel The second step is to either read data from or write data to the control port The only exception to this rule is when accessing the transmit and receive data buffers These registers can be accessed with the two step process described or with a single read or write to the data port The following examples illustrate how to access the internal r...

Page 21: ...upt vector RR2 Special Receive Condition status residue codes error conditions RR1 Transmit Receive buffer statuses and external status RR0 The SCC can perform three basic forms of I O operations polling interrupts and block transfer Polling transfers data without interrupts by reading the status of RR0 and then reading or writing data to the SCC buffers via CPU port accesses Interrupts on the SCC...

Page 22: ...us transmitter receiver control bits NRZI NRZ FM coding CRC reset WR10 Master interrupt control and reset WR9 Transmit buffer WR8 Special HDLC Enhancement Register WR7 Sync character 2nd byte or SDLC Flag WR7 Sync character 1st byte or SDLC address field WR6 Transmitter initialization and control WR5 Transmit Receive miscellaneous parameters and codes clock rate stop bits parity WR4 Receiver initi...

Page 23: ...o the time constant is given below while Table 12 shows the time constants associated with a number of popular baud rates when using the standard MPA 100 9 8304 MHz clock Baud_Const Clock_Frequency 2 Baud_Rate Clock_Mode 2 Where Clock_Frequency crystal frequency of 9 8304MHz Clock_Mode value programmed in WR4 Baud_Rate desired baud rate Table 12 Time constants for common baud rates for 9 8304 MHz ...

Page 24: ...igital phase locked loop DPLL that can be programmed to operate in NRZI or FM modes Also the SCC contains two features for diagnostic purposes controlled by bits in WR14 They are local loopback and auto echo For further information on these subjects or any others involving the SCC contact the manufacturer of the SCC being used for a complete technical manual MPA 100 User s Manual 6 6 ...

Page 25: ...sired channel but not yet enabled Next the SCC should be programmed for DMA request on receive on the desired DMA source The two sources for DMA request on receive are either the W REQA pin pin 10 of channel A or the W REQB pin pin 30 of channel B The source is then determined by bit D1 on the Configuration Register After programming the SCC for DMA one should enable the DMA on the MPA 100 by sett...

Page 26: ... Even though the W REQA pin can be used for both DMA transmit and DMA receive obviously it cannot be used for both simultaneously Therefore bits D0 and D1 of the Configuration Register should never be cleared at the same time while bits D2 and D3 are both set This situation may result in damage to the system Figure 3 Block Diagram of DMA on MPA 100 W REQA DTR REQA W REQB SCC DMATRQ DMARRQ J8 J9 PA...

Page 27: ...The three options are interrupt on terminal count INTTC interrupt from the SCC INTSCC and interrupt on Test Mode INTTM When the source is set that interrupt becomes enabled Below is the mapping for these bits Table 14 Interrupt Sources INTTM 1 1 INTSCC 0 1 INTTC 1 0 Interrupts Disabled 0 0 Interrupt INTS0 INTS1 D3 DMREN RECEIVE DMA ENABLE When set logic 1 the signal from the SCC s receive DMA sour...

Page 28: ...e for Transmit DMA to come from the DTR REQA pin of channel A on the SCC When cleared logic 0 the source for Transmit DMA comes from the W REQA pin of channel A of the SCC NOTE Even though the W REQA pin can be used for both DMA transmit and DMA receive obviously it cannot be used for both simultaneously Therefore bits D0 and D1 of the Configuration Register should never be cleared at the same tim...

Page 29: ...annot be performed simultaneously Thus bits D5 and D4 of the Communications Register should not be set logic 1 simultaneously Table 15 Communications Register Read Write 0 0 TCKEN RCKEN RLEN LLEN 0 TM ST D0 D1 D2 D3 D4 D5 D6 D7 D7 TEST MODE STATUS This bit can read the status of the Test Mode signal on a MPA 100 configured as DTE allowing the user to monitor this signal without generating any inte...

Page 30: ...tted serial data D3 RECEIVE CLOCK ENABLE DCE only When set logic 1 this bit allows the DCE to transmit its Receive Clock RCLK When cleared logic 0 the DCE receives RCLK Since a DTE can only receive RCLK writing to this bit has no effect on a DTE D2 TRANSMIT CLOCK ENABLE DTE only When set logic 1 this bit allows the DTE to transmit its Transmit Clock TCLK When cleared logic 0 the DTE receives TCLK ...

Page 31: ...pin out and clocking options In order to simplify matters an in depth description of each configuration is provided in the next two sections NOTE Because the connector used for the DCE configuration is the same one as is used for the DTE configuration the MPA 100 does not have a true DCE implementation The DCE configuration is provided to allow the head to head connection of two MPA 100 boards one...

Page 32: ...on the DCDB pin pin 21 on channel B Depending on TCKEN bit D2 of the Communications Register the DTE can either transmit its Transmit Clock TCLK from the TRXCA pin pin 14 of the SCC or receive its TCLK on the same pin RCKEN bit D3 of the Communications Register is always deasserted on a DTE configured MPA 100 therefore the DTE can receive its Receive Clock RCLK on the RTXC pins pin 12 28 of the SC...

Page 33: ...g the jumper packs J2 J11 and J12 See Section 5 Table 3 for this configuration information It is noted that because the connector used for the DCE configuration is the same one used for the DTE configuration the MPA 100 does not have a true DCE implementation However the pin out is correct for a one to one wired connection with a DTE The RS232C standard defines each signal with respect to the DTE ...

Page 34: ...ceive Clock on the RTXC pins pins 12 and 28 of the SCC TCKEN bit D2 of the Communications Register is always asserted on a DTE configured MPA 100 therefore the DCE can transmit its Transmit Clock TCLK from the TRXCA pin pin 14 but as per the EIA 232D specification the DCE cannot receive its Transmit Clock For clarity the DCE clock configuration is shown in Figure 5 Figure 5 DCE Clock Configuration...

Page 35: ... RL Bit D5 of Comm Reg X LL RTXC TRXCB pin of SCC X X RxCLK TRXCA pin of SCC X TxCLK DTR REQB pin of SCC X CD DTR REQA pin of SCC X DSR DCDA of SCC X DTR RTSA pin of SCC X CTS CTSA pin of SCC X RTS SCC Pin or Register Bit Generated Received Signal MPA 100 User s Manual 10 5 ...

Page 36: ...MPA 100 User s Manual 10 6 ...

Page 37: ...ations The definitions of the interchange circuits according to the RS 232 D standard can be found in Section 12 Table 18 DTE Connector Pin Definitions D7 of COMM REG X TEST MODE 25 TRXCA on SCC X TXCLK DTE 24 N C 23 N C 22 D4 of COMM REG X RL 21 DTR REQA on SCC X DTR 20 N C 19 D5 of COMM REG X LL 18 TRXCA on SCC X RXCLK DCE 17 N C 16 TRXCB on SCC X TXCLK DCE 15 N C 14 N C 13 N C 12 N A N A N A RX...

Page 38: ...N C 19 D5 of COMM REG X LL 18 RTXC pins on SCC X RXCLK DCE 17 N C 16 TRXCA on SCC X TXCLK DCE 15 N C 14 N C 13 N C 12 N A N A N A RXCLK DTE 11 N C 10 N C 9 DTR REQB on SCC X CD 8 DGND 7 DTR REQA on SCC X DSR 6 RTSA on SCC X CTS 5 CTSA on SCC X RTS 4 TXDA on SCC X RXD 3 RXDA on SCC X TXD 2 CGND 1 SOURCE GENERATED RECEIVED SIGNAL PIN MPA 100 User s Manual 11 2 ...

Page 39: ...N C 13 N C 12 RxCLK DTE 11 N C 10 N C 9 CD 8 DGND 7 DSR 6 CTS 5 RTS 4 RxD 3 TxD 2 CGND 1 Figure 7 MPA 100 DCE Output Connector Configuration 14 N C 15 TxCLK DCE 16 N C 17 RxCLK DCE 18 LLBK Output 19 N C 20 DSR 21 RLBK Output 22 N C 23 N C 24 TxCLK DTE 25 TestMode Input CGND 1 RxD 2 TxD 3 CTS 4 RTS 5 DTR 6 DGND 7 CD 8 N C 9 N C 10 RxCLK DTE 11 N C 12 N C 13 MPA 100 User s Manual 11 3 ...

Page 40: ...MPA 100 User s Manual 11 4 ...

Page 41: ... Received Data CONNECTOR NOTATION RXD DIRECTION From DCE This signal transfers the data generated by the DCE in response to data channel line signals received from a remote DTE data station to the DTE CIRCUIT DA Transmit Signal Element Timing TxCLK DTE Source CONNECTOR NOTATION TXCLK DTE DIRECTION To DCE This signal generated by the DTE provides the DCE with element timing information pertaining t...

Page 42: ...d to transmit data on the communication channel CIRCUIT CF Received Line Signal Detector CARRIER DETECT CONNECTOR NOTATION CD DIRECTION From DCE This signal indicates to the DTE whether the DCE is conditioned to receive data from the communication channel but does not indicate the relative quality of the data signals being received CIRCUIT CD DTE Ready Data Terminal Ready CONNECTOR NOTATION DTR DI...

Page 43: ...h up to and through the remote DCE to the DTE interface and the similar return transmission path CIRCUIT TM Test Mode CONNECTOR NOTATION TEST MODE DIRECTION From DCE This signal indicates to the DTE that the DCE is in a test condition The DCE generates this signal when it has received a local loopback or remote loopback signal from the DTE MPA 100 User s Manual 12 3 ...

Page 44: ...MPA 100 User s Manual 12 4 ...

Page 45: ... connector Transmit drivers RS 232 MC1488 or compatible Receive buffers RS 232 MC1489 or compatible I O Address range 0000H FFFFH Interrupt levels IRQ 2 7 10 12 14 15 DMA levels DMA Channel 1 2 and 3 on transmit and receive Physical Dimensions 4 2 x 7 65 Power requirements 12 36 25 12 36 25 5 1402 1248 Supply Voltage Volts IMax mA ITyp mA MPA 100 User s Manual 13 1 ...

Page 46: ...MPA 100 User s Manual Version 4 12 March 2004 Part No 940 0037 412 MPA 100 User s Manual 13 2 ...

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