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                              F U N C T I O N A L   D E S C R I P T I O N

     G .   M O D E M   S T A T U S   R E G I S T E R

        +------+
    D7  | DCD  |----- Data carrier detect
        +------+
    D6  |  RI  |----- Ring indicator
        +------+
    D5  | DSR  |----- Data set ready
        +------+
    D4  | CTS  |----- Clear to send
        +------+
    D3  | DDCD |----- Delta data carrier detect
        +------+
    D2  | TERI |----- Trailing edge ring indicator
        +------+
    D1  | DDSR |----- Delta data set ready
        +------+
    D0  | DCTS |----- Delta clear to send
        +------+
  Figure 13.  MODEM status register bit definitions.

DCD  - Data Carrier Detect:

Complement of the DCD input.

RI   - Ring Indicator:

Complement of the RI input.

DSR  - Data Set Ready:

Complement of the DSR input.

CTS  - Clear To Send:

Complement of the CTS input.

B i t s   D D C D ,   T E R I ,   D D S R ,   a n d   D C T S   a r e   t h e   s o u r c e s   o f
M O D E M   s t a t u s   i n t e r r u p t s .     T h e s e   b i t s   a r e   r e s e t   w h e n
the MODEM status register is read.

DDCD - Delta Data Carrier Detect:

I n d i c a t e s   t h e   D a t a   C a r r i e r   D e t e c t   i n p u t   h a s
changed state.

TERI - Trailing Edge Ring Indicator:

I n d i c a t e s   t h e   R i n g   I n d i c a t o r   i n p u t   h a s   c h a n g e d
from a low to a high state.

DDSR - Delta Data Set Ready:

I n d i c a t e s   t h e   D a t a   S e t   R e a d y   i n p u t   h a s   c h a n g e d
state.

DCTS - Delta Clear To Send:

I n d i c a t e s   t h e   C l e a r   t o   S e n d     i n p u t   h a s   c h a n g e d
state.

                           iii

Summary of Contents for DS-3000

Page 1: ...hough every attempt has been made to guarantee the accuracy of this manual Qua Tech Inc assumes no l i a b i l i t y f o r d a m a g e s r e s u l t i n g f r o m e r r o r s i n t h i s document Qua...

Page 2: ...GISTER 5 C FIFO CONTROL REGISTER 7 D LINE CONTROL REGISTER 8 E MODEM CONTROL REGISTER 10 F LINE STATUS REGISTER 11 G MODEM STATUS REGISTER 13 H SCRATCHPAD REGISTER 14 IV FIFO INTERRUPT MODE OPERATION...

Page 3: ...ol register 10 Figure 12 Line status register 11 Figure 13 MODEM status register 13 Figure 14 Input clock frequency options 15 Figure 15 Divisor latch options 15 Figure 16 POS implementation 17 Figure...

Page 4: ...itional FIFO mode that reduces CPU overhead at higher data rates The DS 2000 supports sixteen base addresses for each A C E t h r o u g h t h e P r o g r a m m a b l e O p t i o n S e l e c t P O S in...

Page 5: ...FUNCTIONAL DESCRIPTION F i g u r e 1 D S 2 0 0 0 b o a r d l a y o u t iii...

Page 6: ...able baud rate character length parity and number of stop bits Automatic addition and removal of start stop and parity bits Independent and prioritized transmit receive and status interrupts Transmitt...

Page 7: ...ic 1 enables interrupt on clear to send data set ready ring indicator and data carrier detect ELSI Receiver Line Status Interrupt When set logic 1 enables interrupt on overrun parity and framing error...

Page 8: ...s FFE FIFO Enable When logic 1 indicates FIFO mode enabled IIDx Interrupt Identification Indicates highest priority interrupt pending if any See IP and figure 5 NOTE IID2 is always a logic 0 in charac...

Page 9: ...been reached The interrupt is reset when the FIFO drops below the the trigger level Character Timeout FIFO mode only Indicates no characters have been removed from or i n p u t t o t h e r e c e i v...

Page 10: ...h e t r i g g e r l e v e l f o r t h e F I F O interrupt as given in figure 7 below RCVR FIFO RXT1 RXT0 Trigger level bytes 0 0 1 0 1 4 1 0 8 1 1 14 Figure 7 FIFO trigger levels DMAM DMA Mode Select...

Page 11: ...n t r o l r e g i s t e r a r e w r i t t e n t o o r t h e b i t s w i l l b e ignored D LINE CONTROL REGISTER D7 DLAB Divisor latch access bit D6 BKCN Break control D5 STKP Stick parity D4 EPS Even...

Page 12: ...EPS PEN Parity x x 0 None 0 0 1 Odd 0 1 1 Even 1 0 1 Logic 1 1 1 1 Logic 0 Figure 9 16550 parity selections STB Number of Stop Bits Sets the number of stop bits transmitted See WLSx and figure 10 WLSx...

Page 13: ...t a p a t h s T r a n s m i t a n d r e c e i v e i n t e r r u p t s s t i l l o p e r a t e n o r m a l l y b u t M O D E M c o n t r o l i n t e r r u p t s a r e n o w controlled by the MODEM cont...

Page 14: ...r o r s o r b r e a k i n d i c a t i o n s i n t h e r e c e i v e r FIFO FFRX is reset by reading the line status register TEMT Transmitter Empty Indicates the transmitter holding register or F I F...

Page 15: ...s t a t e l o g i c 1 a n d a v a l i d s t a r t b i t i s received FE Framing Error Indicates the received character had an invalid stop bit The stop bit following the last data or parity bit was a...

Page 16: ...DSR Data Set Ready Complement of the DSR input CTS Clear To Send Complement of the CTS input Bits DDCD TERI DDSR and DCTS are the sources of MODEM status interrupts These bits are reset when the MODEM...

Page 17: ...receiver FIFO and is cleared when the FIFO is empty V BAUD RATE SELECTION T h e 1 6 5 5 0 U A R T d e t e r m i n e s t h e b a u d r a t e o f t h e s e r i a l o u t p u t f r o m a c o m b i n a t...

Page 18: ...8432 MHz T h e b a u d r a t e m a y n o w b e c a l c u l a t e d u s i n g t h e equation crystal frequency baud rate 16 x divider x DL where divider the clock divider setting of jumper J1 DL the va...

Page 19: ...l m a y s e l e c t a separate interrupt or one may be shared by both channels If interrupt sharing is used the interrupt pending IP bit in the interrupt identification register should be used to test...

Page 20: ...not be written to by user software The bit definitions of these registers are given in figures 16 a and 16 b D7 CHEN1 Channel enable D6 INS11 Interrupt select D5 INS10 D4 ADS13 a D3 ADS12 Address sele...

Page 21: ...1 3228H Serial 4 0 1 0 0 4220H Serial 5 0 1 0 1 4228H Serial 6 0 1 1 0 5220H Serial 7 0 1 1 1 5228H Serial 8 1 0 0 0 83F8H 1 0 0 1 82F8H 1 0 1 0 B220H 1 0 1 1 B228H 1 1 0 0 C220H 1 1 0 1 C228H 1 1 1 0...

Page 22: ...d by looping the RTS output back to the CTS input This is accomplished by connecting pins 1 and 5 of the jumper block figures 22 and 23 RCLK is the input to the 16550 which controls the s h i f t r a...

Page 23: ...o n t r o l r e g i s t e r e n a b l e s t r a n s m i s s i o n W r i t i n g a l o g i c 0 disables transmission In this configuration trans mission is disabled on power up Enable1 DTR DTR 4 o o o...

Page 24: ...diagram AUXIN RCLK CTS DTR 5 o o o o 8 1 o o o o 4 RTS driver enable AUXOUT XCLK J2 _ Channel 1 J3 _ Channel 2 Function Connect Disconnect RTS CTS loopback 1 5 1 2 Transmit RTS 5 6 6 7 Receive CTS 1 2...

Page 25: ...CLK CTS DTR 5 o o o o 8 1 o o o o 4 RTS driver enable AUXOUT XCLK J2 _ Channel 1 J3 _ Channel 2 Figure 22 Jumper configuration showing 1 RTS CTS loopback 2 XCLK transmission 3 RCLK reception 4 Full du...

Page 26: ...on PIN SIGNAL DESCRIPTION 1 AUX OUT When combined with AUX OUT provides the auxiliary channel output defined by jumpers J2 J3 2 DATA OUT When combined with DATA OUT provides the serial data output 3 S...

Page 27: ...9 Select Change configuration or Run automatic configuration and follow instructions After the initial installation the reference diskette w i l l c o n t a i n t h e c o n f i g u r a t i o n f i l e...

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