F U N C T I O N A L D E S C R I P T I O N
C . F I F O C O N T R O L R E G I S T E R
+------+
D7 | RXT1 |--+
+------+ +-- Receiver trigger
D6 | RXT0 |--+
+------+
D5 | x |--+
+------+ +-- Reserved
D4 | x |--+
+------+
D3 | DMAM |----- DMA mode select
+------+
D2 | XRST |----- Transmit FIFO reset
+------+
D1 | RRST |----- Receive FIFO reset
+------+
D0 | FE |----- FIFO enable
+------+
Figure 6. FIFO control register bit definitions.
RXTx - Receiver FIFO Trigger Level:
D e t e r m i n e s t h e t r i g g e r l e v e l f o r t h e F I F O
interrupt as given in figure 7 below.
+-----------+-----------------------+
| | RCVR FIFO |
| RXT1 RXT0 | Trigger level (bytes) |
+-----------+-----------------------+
| 0 0 | 1 |
| 0 1 | 4 |
| 1 0 | 8 |
| 1 1 | 14 |
+-----------+-----------------------+
Figure 7. FIFO trigger levels.
DMAM - DMA Mode Select:
W h e n s e t ( l o g i c 1 ) , R x R D Y a n d T x R D Y c h a n g e f r o m
mode 0 to mode 1. (DMA mode not supported on DS-
2000.)
XRST - Transmit FIFO Reset:
W h e n s e t ( l o g i c 1 ) , a l l b y t e s i n t h e t r a n s m i t t e r
F I F O a r e c l e a r e d a n d t h e c o u n t e r i s r e s e t . T h e
s h i f t r e g i s t e r i s n o t c l e a r e d . X R S T i s s e l f -
clearing.
iii
